GATE 2026 Analog and Digital Electronics Questions and Solutions

1 mark, numerical answer. A single-phase bridge rectifier is fed from a 50 Hz sinusoidal source of peak value 20 V and feeds a pure resistive load. Each diode has a constant forward drop of 0.7 V when conducting and is an open circuit otherwise. The filter capacitor is absent. The average (DC) value of the load voltage, in volts rounded off to two decimal places, is _____.

Solution

In a bridge rectifier two diodes conduct in series during each half cycle, so the load sees the source magnitude reduced by two forward drops. Conduction starts when the source magnitude exceeds \(1.4\,\mathrm{V}\); since \(1.4\,\mathrm{V}\) is only 7 % of the 20 V peak, the standard GATE approximation of full half-cycle conduction is used, and the load waveform is a rectified sine of peak \(V_m - 2V_D\).

The average over a half period of a full-wave rectified sine is \(2V_m/\pi\), and the constant diode drop simply subtracts:

See Full-wave diode rectifier for the derivation of the \(2V_m/\pi\) result.

1 mark, multiple choice. A BJT common-emitter amplifier is biased at a collector current of \(1\,\mathrm{mA}\). The collector resistor is \(R_C = 5\,\mathrm{k}\Omega\), and an emitter resistor \(R_E = 100\,\Omega\) is left unbypassed. The thermal voltage is \(V_T = 25\,\mathrm{mV}\), the base-width modulation is neglected (\(r_o \to \infty\)) and \(\beta\) is large enough that base current may be ignored. The small-signal midband voltage gain \(v_o/v_i\) is

1. \(-200\)
2. \(-50\)
3. \(-40\)
4. \(-8\)

Solution

The transconductance at the given bias point is

With an unbypassed emitter resistor the signal current through the collector is \(i_c = g_m v_{be}\) while the input is \(v_i = v_{be} + i_e R_E \approx v_{be}(1 + g_m R_E)\). Hence

Background: BJT amplifiers.

2 marks, numerical answer. An n-channel enhancement MOSFET has \(V_{TH} = 1\,\mathrm{V}\) and \(k_n = \mu_n C_{ox}(W/L) = 2\,\mathrm{mA/V^2}\), and channel-length modulation is neglected. It is biased from \(V_{DD} = 10\,\mathrm{V}\) by a gate divider that holds the gate at a DC potential of \(4\,\mathrm{V}\) with respect to ground (the divider resistors are large enough that the gate current, which is zero, causes no loading). The drain resistor is \(R_D = 2\,\mathrm{k}\Omega\) and the source resistor is \(R_S = 1\,\mathrm{k}\Omega\), the source resistor returning to ground. The drain current, in mA rounded off to two decimal places, is _____.

Solution

Assume saturation, so that with \(I_D\) in mA and resistances in \(\mathrm{k}\Omega\),

Substituting \(k_n/2 = 1~\mathrm{mA/V^2}\):

The root \(I_D = 5.30\,\mathrm{mA}\) gives \(V_{GS} = 4 - 5.30 = -1.30\,\mathrm{V}\), which is below \(V_{TH}\) and therefore inconsistent with conduction. The physical root is

Check the saturation assumption: \(V_{GS} = 4 - 1.6972 = 2.303\,\mathrm{V}\), so \(V_{OV} = 1.303\,\mathrm{V}\), while

so the device is indeed saturated and the answer stands. Background: MOSFET.

2 marks, numerical answer. An ideal op-amp is connected as an inverting integrator: the input source drives resistor \(R = 100\,\mathrm{k}\Omega\) into the inverting terminal, a capacitor \(C = 0.1\,\mu\mathrm{F}\) connects the inverting terminal to the output, and the non-inverting terminal is grounded. The capacitor is initially uncharged. At \(t = 0\) the input voltage steps from 0 to \(-2\,\mathrm{V}\) and stays there. The output voltage at \(t = 5\,\mathrm{ms}\), in volts, is _____.

Solution

The inverting terminal is a virtual ground, so the resistor current is \(v_i/R\) and all of it flows into the capacitor towards the output:

With a constant input of \(-2\,\mathrm{V}\) and \(v_o(0)=0\) the output ramps linearly:

The output ramps positive because the integrator inverts. Background: Op-amp circuits.

2 marks, numerical answer. A Wien-bridge oscillator uses an ideal op-amp. The frequency-selective network is the usual one: a series branch of \(R = 10\,\mathrm{k}\Omega\) with \(C = 10\,\mathrm{nF}\) in series, feeding a parallel branch of an identical \(R = 10\,\mathrm{k}\Omega\) with \(C = 10\,\mathrm{nF}\) in parallel, and the junction of the two branches drives the non-inverting terminal. The frequency of sustained oscillation, in Hz rounded off to two decimal places, is _____.

Solution

Let \(Z_s = R + 1/(sC)\) be the series branch and \(Z_p = R \parallel 1/(sC) = R/(1+sCR)\) the parallel branch. The feedback factor is the divider ratio

Putting \(s = j\omega\), the denominator is \(1 - (\omega CR)^2 + j3\omega CR\). The Barkhausen phase condition requires \(\beta\) to be real, which happens when the real part of the denominator vanishes:

At this frequency \(\beta = 1/3\), so the amplifier must supply a gain of exactly 3, i.e. the inverting-side resistor ratio must be \(R_f/R_1 = 2\). Background: Electronic oscillators.

2 marks, numerical answer. A second-order Sallen-Key low-pass filter uses equal resistors \(R\) and equal capacitors \(C\), with the op-amp connected as a non-inverting amplifier of DC gain \(K\) whose output feeds back through the first capacitor. Its transfer function is

The filter is to have a maximally flat (Butterworth) magnitude response. The required value of \(K\), rounded off to three decimal places, is _____.

Solution

Comparing with the standard second-order form \(s^2 + 2\zeta\omega_0 s + \omega_0^2\) gives \(2\zeta = 3-K\), i.e. a pole quality factor

A maximally flat second-order response has no peaking in \(|H(j\omega)|\); writing \(u = (\omega/\omega_0)^2\),

The \(u\) term disappears, leaving the flattest possible denominator, when \((3-K)^2 = 2\), that is \(\zeta = 1/\sqrt{2}\) and \(Q = 0.7071\). Hence

The non-inverting amplifier therefore needs a feedback ratio \(R_b/R_a = K - 1 = 0.586\). Background: Active filters.

1 mark, multiple choice. A logic family has the following worst-case specifications: \(I_{OL(max)} = 20\,\mathrm{mA}\), \(I_{IL(max)} = 2\,\mathrm{mA}\), \(I_{OH(max)} = 0.8\,\mathrm{mA}\) and \(I_{IH(max)} = 50\,\mu\mathrm{A}\). The current directions follow the usual convention, so that a driving output must sink the LOW input currents of all the gates it drives and source their HIGH input currents. The fan-out of one gate of this family is

1. 8
2. 10
3. 16
4. 40

Solution

In the LOW state the driver sinks \(N I_{IL}\) and must not exceed \(I_{OL(max)}\):

In the HIGH state the driver sources \(N I_{IH}\):

Both states must be satisfied simultaneously, so the fan-out is the smaller of the two, \(N = \min(10, 16) = 10\).

2 marks, multiple choice. A combinational circuit realises the four-variable Boolean function

where \(A\) is the most significant variable. The minimal expression for \(F\) is

1. \(A \oplus C\)
2. \(\overline{B \oplus D}\)
3. \(B \oplus D\)
4. \(\overline{A \oplus C}\)

Solution

Write the minterms as \(ABCD\):

In the first group \(B = 0\) and \(D = 0\) while \(A\) and \(C\) take all four combinations, so those four cells merge into the single term \(\overline{B}\,\overline{D}\). In the second group \(B = 1\) and \(D = 1\) with \(A\) and \(C\) again taking all four combinations, giving \(BD\). Therefore

which is the exclusive-NOR of \(B\) and \(D\): the output is 1 exactly when \(B\) and \(D\) agree, and \(A\) and \(C\) are don't-cares. Background: Digital electronics revision notes.

2 marks, numerical answer. Five positive-edge-triggered D flip-flops are connected as a Johnson (twisted-ring) counter: the output of each flip-flop drives the D input of the next, and the complemented output of the last flip-flop is fed back to the D input of the first. All five flip-flops share a common clock of frequency 2 MHz and the counter starts from the all-zero state. The frequency of the waveform at any one flip-flop output, in kHz, is _____.

Solution

Starting from \(00000\), the inverted feedback shifts in ones until the register fills, then shifts in zeros until it empties:

The sequence closes after 10 clock pulses, so an \(n\)-stage Johnson counter has \(2n = 10\) distinct states. Every flip-flop output therefore stays HIGH for five clocks and LOW for five clocks, one complete output cycle spanning 10 clock periods:

2 marks, numerical answer. A 4-bit successive-approximation ADC uses an internal R-2R ladder DAC whose output is \(V_{DAC} = V_{ref}\,(N/16)\), where \(N\) is the decimal value of the 4-bit code and \(V_{ref} = 8\,\mathrm{V}\). The comparator keeps a trial bit if \(V_{DAC} \le V_{in}\) and clears it otherwise, testing bits from the MSB downwards. For an analog input held constant at \(5.2\,\mathrm{V}\), the DAC output voltage at the end of conversion, in volts, is _____.

Solution

The DAC step size is

Successive approximation then proceeds one bit per clock:

The final code is \(1010_2 = 10\), and the DAC settles at

The residual quantisation error is \(5.2 - 5.0 = 0.2\,\mathrm{V}\), which is less than one step, as it must be.