MOSFET Characteristics and Biasing

About this problem set

Enhancement and depletion MOSFET bias work: pulling the conduction parameter k out of a data sheet, solving drain-feedback and voltage-divider bias from the square law, running a depletion device on both sides of zero gate voltage, deciding between the ohmic and saturation regions, and a full E24 bias design verified against specification.

Each problem below is solved in full — the given data is listed first, the governing relation is stated, and the arithmetic is carried through to a boxed answer. Work through the statement yourself before opening the solution. The underlying theory is covered in the Electronic Devices lecture series.

PROBLEM 01

Extracting k from an E-MOSFET Data Sheet

Problem Statement

The data sheet of an n-channel enhancement MOSFET gives a threshold voltage \(V_{GS(\text{th})} = 3~\text{V}\) and a single on-point: \(I_{D(\text{on})} = 10~\text{mA}\) at \(V_{GS(\text{on})} = 8~\text{V}\). Above threshold and in saturation the device follows \(I_D = k\left(V_{GS} - V_{GS(\text{th})}\right)^2\).

Extract the conduction parameter \(k\).
Find \(I_D\) at \(V_{GS} = 6~\text{V}\), and the transconductance there.
Find the \(V_{GS}\) needed for \(I_D = 20~\text{mA}\).
Tabulate the transfer characteristic from 3 V to 9 V.

Solution

\(V_T \equiv V_{GS(\text{th})} = 3~\text{V}\)
One data-sheet point: \(I_D = 10~\text{mA}\) at \(V_{GS} = 8~\text{V}\)
Saturation (active) region assumed; channel-length modulation neglected.

Part (a) — the conduction parameter

The single on-point is enough, because the square law has only one free constant once \(V_T\) is known:

\[\begin{aligned} k &= \frac{I_{D(\text{on})}}{\left(V_{GS(\text{on})} - V_T\right)^2}= \frac{10~\text{mA}}{(8 - 3)^2~\text{V}^2} \\ &= \frac{10}{25} = 0.400~\text{mA/V}^2 \end{aligned}\]

\(k = 0.400~\text{mA/V}^2 = 400~\mu\text{A/V}^2\)

Part (b) — current and slope at \(V_{GS} = 6~\text{V}\)

\[\begin{aligned} I_D &= k(V_{GS} - V_T)^2 = 0.4(6 - 3)^2 = 0.4(9) = 3.600~\text{mA} \\ g_m &= \frac{dI_D}{dV_{GS}} = 2k(V_{GS} - V_T) = 2(0.4)(3) = 2.400~\text{mS} \end{aligned}\]

\(I_D = 3.60~\text{mA}\), \(g_m = 2.40~\text{mS}\)

Part (c) — the equation inverted

\[\begin{aligned} V_{GS} &= V_T + \sqrt{\frac{I_D}{k}} = 3 + \sqrt{\frac{20}{0.4}} \\ &= 3 + \sqrt{50} = 3 + 7.071 = 10.071~\text{V} \end{aligned}\]

\(V_{GS} = 10.07~\text{V}\) for \(I_D = 20~\text{mA}\)

Part (d) — transfer characteristic

\(V_{GS}\) (V)	\(V_{GS} - V_T\) (V)	\(I_D\) (mA)
3.0	0.0	0.000
4.0	1.0	0.400
5.0	2.0	1.600
6.0	3.0	3.600
7.0	4.0	6.400
8.0	5.0	10.000
9.0	6.0	14.400

The curve starts at zero at \(V_{GS} = V_T = 3~\text{V}\) and rises as a parabola — there is no current at all below threshold.

Unlike the JFET, whose curve is pinned by the two measurable end points \(I_{DSS}\) and \(V_P\), the E-MOSFET curve needs a threshold plus one point on the parabola. Two data-sheet numbers, one square law.

PROBLEM 02

Drain-Feedback Bias Q-Point

Problem Statement

An E-MOSFET is drain-feedback biased: \(V_{DD} = 12~\text{V}\), a 2 k\(\Omega\) drain resistor from the rail to the drain, a 10 M\(\Omega\) resistor from drain to gate, and the source grounded. The device has \(V_T = 3~\text{V}\) and \(k = 0.3~\text{mA/V}^2\).

Show that \(V_{GS} = V_{DS}\) and set up the quadratic in \(V_{GS}\).
Solve for the Q-point \((I_{DQ}, V_{DSQ})\).
Explain why this topology can never leave the saturation region, and give \(g_m\) at the Q-point.

Solution

\(V_{DD} = 12~\text{V}\), \(R_D = 2~\text{k}\Omega\), \(R_G = 10~\text{M}\Omega\) (drain to gate)
\(V_T = 3~\text{V}\), \(k = 0.3~\text{mA/V}^2\)
\(I_G = 0\), so no current and no drop in \(R_G\).

Part (a) — the feedback constraint

With zero gate current there is no drop across \(R_G\), so the gate sits at the drain potential:

\[\begin{aligned} V_{GS} &= V_{DS} = V_{DD} - I_D R_D \\ \Rightarrow\; I_D &= \frac{V_{DD} - V_{GS}}{R_D}\quad\text{(the bias line)} \\ k(V_{GS} - V_T)^2 &= \frac{V_{DD} - V_{GS}}{R_D} \end{aligned}\]

Multiplying out with \(k = 0.3~\text{mA/V}^2\) and \(R_D = 2~\text{k}\Omega\):

\[0.60V_{GS}^2 - 2.60V_{GS} - 6.60 = 0\]

Part (b) — solving

\[\begin{aligned} V_{GS} &= \frac{2.60 \pm \sqrt{(-2.60)^2 - 4(0.60)(-6.60)}}{2(0.60)}= \frac{2.60 \pm 4.7539}{1.20} \\ &= 6.1283~\text{V}\quad\text{or}\quad -1.7950~\text{V (rejected: below } V_T) \\ I_D &= \frac{12 - 6.1283}{2~\text{k}\Omega} = 2.9359~\text{mA} \end{aligned}\]

Check against the device law: \(k(V_{GS}-V_T)^2 = 0.3(3.1283)^2 = 2.9359~\text{mA}\) — consistent.

\(I_{DQ} = 2.94~\text{mA}\), \(V_{DSQ} = V_{GSQ} = 6.13~\text{V}\)

Part (c) — guaranteed saturation, and \(g_m\)

Saturation requires \(V_{DS} > V_{GS} - V_T\). Here \(V_{DS} = V_{GS}\) exactly, and \(V_T > 0\), so

\[V_{DS} - (V_{GS} - V_T) = V_T = 3~\text{V} > 0\quad\text{always}\]

\[g_m = 2k(V_{GS} - V_T) = 2(0.3)(3.128) = 1.877~\text{mS}\]

The device is always saturated, by \(V_T = 3~\text{V}\) of margin; \(g_m = 1.88~\text{mS}\).

The feedback is self-correcting: if \(I_D\) drifts up, \(V_D\) falls, which pulls the gate down and reduces \(I_D\) again. One resistor buys both bias stability and guaranteed saturation — at the cost of shunting the signal path with \(R_G\).

PROBLEM 03

Voltage-Divider Bias of an E-MOSFET

Problem Statement

An E-MOSFET stage runs from \(V_{DD} = 40~\text{V}\). The gate divider is \(R_1 = 22~\text{M}\Omega\) (rail to gate) and \(R_2 = 18~\text{M}\Omega\) (gate to ground); \(R_D = 3~\text{k}\Omega\) and \(R_S = 0.82~\text{k}\Omega\). The data sheet gives \(V_{GS(\text{th})} = 5~\text{V}\) and \(I_{D(\text{on})} = 3~\text{mA}\) at \(V_{GS} = 10~\text{V}\).

Find \(k\) and the gate voltage \(V_G\).
Solve the bias quadratic for \(I_{DQ}\) and \(V_{GSQ}\).
Find \(V_{DS}\) and confirm the device is saturated.

Solution

\(V_{DD} = 40~\text{V}\), \(R_1 = 22~\text{M}\Omega\), \(R_2 = 18~\text{M}\Omega\)
\(R_D = 3~\text{k}\Omega\), \(R_S = 0.82~\text{k}\Omega\)
\(V_T = 5~\text{V}\); \(I_D = 3~\text{mA}\) at \(V_{GS} = 10~\text{V}\)
\(I_G = 0\), so the divider is unloaded; currents in mA, resistances in k\(\Omega\).

Part (a) — device constant and gate voltage

\[\begin{aligned} k &= \frac{3~\text{mA}}{(10-5)^2} = 0.120~\text{mA/V}^2 \\ V_G &= \frac{R_2 V_{DD}}{R_1 + R_2} = \frac{18(40)}{22 + 18} = 18.00~\text{V} \end{aligned}\]

\(k = 0.120~\text{mA/V}^2\), \(V_G = 18~\text{V}\)

Part (b) — the bias quadratic

\[\begin{aligned} V_{GS} &= V_G - I_D R_S = 18.0 - 0.82I_D \\ I_D &= k(V_{GS} - V_T)^2 = 0.12\left(13.0 - 0.82I_D\right)^2 \\ 0.08069I_D^2 - 3.5584I_D + 20.2800 &= 0 \\ I_D &= \frac{3.5584 \pm \sqrt{6.1168}}{2(0.08069)} = 6.7246\ \text{or}\ 37.376~\text{mA} \end{aligned}\]

The large root would require \(V_{GS} = -12.65~\text{V}\), below threshold — the device would be off, so it is rejected.

\[V_{GSQ} = 18.0 - 0.82(6.7246) = 12.4859~\text{V}\]

\(I_{DQ} = 6.72~\text{mA}\), \(V_{GSQ} = 12.49~\text{V}\)

Part (c) — drain circuit and region check

\[\begin{aligned} V_S &= I_D R_S = 5.514~\text{V},\qquad V_D = 40 - I_D R_D = 19.826~\text{V} \\ V_{DS} &= V_{DD} - I_D(R_D + R_S) = 40 - (6.7246)(3.82) = 14.312~\text{V} \\ V_{GS} - V_T &= 7.486~\text{V} \;<\; V_{DS} = 14.312~\text{V}\quad\checkmark \end{aligned}\]

\(V_{DSQ} = 14.31~\text{V}\), saturated with 6.83 V of margin; \(g_m = 1.80~\text{mS}\).

Note the gate must sit above the source by more than \(V_T\), so unlike the JFET the divider has to supply a large positive \(V_G\) — 18 V here. That is why E-MOSFET dividers use tens of megohms: the current wasted in the divider would otherwise be significant.

PROBLEM 04

Depletion MOSFET Self-Bias and Positive Gate Drive

Problem Statement

A depletion-type n-channel MOSFET has \(I_{DSS} = 6~\text{mA}\) and \(V_{GS(\text{off})} = -3~\text{V}\). It obeys the same Shockley law as a JFET but, having an insulated gate, may also be driven with \(V_{GS} > 0\).

In a self-bias circuit with \(R_S = 750~\Omega\) and the gate returned to ground, find \(I_D\) and \(V_{GS}\).
Find \(I_D\) at \(V_{GS} = +1~\text{V}\) and comment on the result.
The circuit is rebuilt with a divider holding \(V_G = +1.5~\text{V}\), \(R_S = 150~\Omega\), \(R_D = 1.2~\text{k}\Omega\) and \(V_{DD} = 18~\text{V}\). Find the Q-point and check the region of operation.

Solution

\(I_{DSS} = 6~\text{mA}\), \(V_P = -3~\text{V}\)
\(I_D = I_{DSS}(1 - V_{GS}/V_P)^2\) holds for \(V_{GS}\) either side of zero, up to the gate-oxide rating
\(I_G = 0\); currents in mA, resistances in k\(\Omega\).

Part (a) — self-bias, depletion mode

\[\begin{aligned} V_{GS} &= -I_D R_S = -0.75 I_D \\ I_D &= 6\left(1 - \frac{0.75 I_D}{3}\right)^2 = 6(1 - 0.25 I_D)^2 \\ 0.3750 I_D^2 - 4.0000 I_D + 6.0000 &= 0 \\ I_D &= 1.8057~\text{mA},\qquad V_{GS} = -1.3542~\text{V} \end{aligned}\]

\(I_D = 1.81~\text{mA}\) at \(V_{GS} = -1.35~\text{V}\) — depletion mode, \(I_D < I_{DSS}\).

Part (b) — positive gate drive

\[\begin{aligned} I_D &= 6\left(1 - \frac{+1}{-3}\right)^2 = 6\left(1 + \tfrac{1}{3}\right)^2 = 6(1.3333)^2 \\ &= 10.667~\text{mA} \end{aligned}\]

\(I_D = 10.7~\text{mA}\), which exceeds \(I_{DSS}\) — the device is in enhancement mode.

A positive gate attracts extra electrons into the induced channel instead of depleting it. A JFET cannot do this: forward-biasing its gate junction would draw gate current.

Part (c) — divider bias with a small \(R_S\)

\[\begin{aligned} V_{GS} &= V_G - I_D R_S = 1.5 - 0.15 I_D \\ I_D &= 6\left(1 - \frac{1.5 - 0.15 I_D}{-3}\right)^2 \\ 0.0150I_D^2 - 1.9000I_D + 13.5000 &= 0 \\ I_D &= 7.5560~\text{mA}\quad(\text{other root }119.111~\text{mA rejected}) \\ V_{GS} &= 1.5 - 0.15(7.5560) = 0.3666~\text{V} \end{aligned}\]

\[\begin{aligned} V_{DS} &= V_{DD} - I_D(R_D + R_S) = 18 - (7.5560)(1.35) = 7.799~\text{V} \\ V_{GS} - V_P &= 0.367 + 3 = 3.367~\text{V} < V_{DS}\quad\checkmark \end{aligned}\]

\(I_{DQ} = 7.56~\text{mA}\), \(V_{GSQ} = +0.367~\text{V}\), \(V_{DSQ} = 7.80~\text{V}\); saturated, \(g_m = 4.49~\text{mS}\).

The Q-point now sits above \(I_{DSS}\), on the enhancement side of the transfer curve, which is exactly where a D-MOSFET buys extra \(g_m\) over a JFET of the same \(I_{DSS}\) and \(V_P\).

PROBLEM 05

Ohmic or Saturation Region of Operation

Problem Statement

An n-channel E-MOSFET with \(k = 0.5~\text{mA/V}^2\) and \(V_T = 2~\text{V}\) is used as a common-source stage from \(V_{DD} = 10~\text{V}\) with the source grounded and the gate held at \(V_{GS} = 5~\text{V}\). The boundary between the ohmic (triode) and saturation regions is \(V_{DS} = V_{GS} - V_T\), and in the ohmic region \(I_D = k\left[2(V_{GS}-V_T)V_{DS} - V_{DS}^2\right]\).

With \(R_D = 1~\text{k}\Omega\), find the region of operation and \(I_D\).
Repeat with \(R_D = 2~\text{k}\Omega\).
Find the largest \(R_D\) that keeps the device saturated.
For \(V_{DS} \ll V_{GS}-V_T\) the device behaves as a resistor. Find that \(r_{DS(\text{on})}\).

Solution

\(k = 0.5~\text{mA/V}^2\), \(V_T = 2~\text{V}\), \(V_{GS} = 5~\text{V}\)
Overdrive \(V_{OV} = V_{GS} - V_T = 3~\text{V}\); \(V_{DD} = 10~\text{V}\)
Method: assume saturation, solve, then test \(V_{DS} > V_{OV}\). If the test fails, redo in the ohmic region.

Part (a) — \(R_D = 1~\text{k}\Omega\)

\[\begin{aligned} I_D &= k V_{OV}^2 = 0.5(3)^2 = 4.50~\text{mA}\quad(\text{assumed saturated}) \\ V_{DS} &= 10 - (4.50)(1) = 5.50~\text{V} \\ V_{DS} = 5.50~\text{V} &> V_{OV} = 3~\text{V}\quad\checkmark\ \text{assumption holds} \end{aligned}\]

Saturation region; \(I_D = 4.50~\text{mA}\), \(V_{DS} = 5.50~\text{V}\).

Part (b) — \(R_D = 2~\text{k}\Omega\)

\[\begin{aligned} V_{DS} &= 10 - (4.50)(2) = 1.00~\text{V} \\ V_{DS} = 1.00~\text{V} &< V_{OV} = 3~\text{V}\quad\times\ \text{contradiction} \end{aligned}\]

The saturation assumption fails, so the device is in the ohmic region. Equate the ohmic device law with the load line \(I_D = (V_{DD}-V_{DS})/R_D\):

\[\begin{aligned} \frac{10 - V_{DS}}{2} &= 0.5\left[2(3)V_{DS} - V_{DS}^2\right] \\ 10 - V_{DS} &= 6V_{DS} - V_{DS}^2 \\ V_{DS}^2 - 7V_{DS} + 10 &= 0 \;\Rightarrow\; V_{DS} = 2.0~\text{V or } 5.0~\text{V} \\ I_D &= \frac{10 - 2.0}{2} = 4.00~\text{mA} \end{aligned}\]

Only \(V_{DS} = 2.0~\text{V}\) is below \(V_{OV} = 3~\text{V}\); the 5.0 V root lies in the saturation region where the ohmic equation does not apply. Check with the ohmic law: \(0.5[2(3)(2.0) - 2.0^2] = 4.00~\text{mA}\).

Ohmic (triode) region; \(I_D = 4.00~\text{mA}\), \(V_{DS} = 2.00~\text{V}\).

Part (c) — the boundary load resistance

At the edge, \(V_{DS} = V_{OV} = 3~\text{V}\) while the device still carries the saturation current 4.50 mA:

\[R_{D(\max)} = \frac{V_{DD} - V_{OV}}{k V_{OV}^2} = \frac{10 - 3}{4.5~\text{mA}} = 1.5556~\text{k}\Omega\]

\(R_D < 1.56~\text{k}\Omega\) keeps the stage in saturation — which is why the 2 k\(\Omega\) case failed.

Part (d) — on-resistance as a switch

For small \(V_{DS}\) the \(V_{DS}^2\) term is negligible:

\[\begin{aligned} I_D &\approx 2k V_{OV} V_{DS} \;\Rightarrow\; r_{DS(\text{on})} = \frac{V_{DS}}{I_D} = \frac{1}{2kV_{OV}} \\ &= \frac{1}{2(0.5~\text{mA/V}^2)(3~\text{V})} = \frac{1}{3.0~\text{mS}} = 333.3~\Omega \end{aligned}\]

\(r_{DS(\text{on})} = 333~\Omega\)

The same device is an amplifier in saturation and a voltage-controlled resistor in the ohmic region. Raising \(V_{GS}\) lowers \(r_{DS(\text{on})}\) as \(1/V_{OV}\), which is exactly why power MOSFETs are driven with 10-15 V gate drive rather than just above threshold.

PROBLEM 06

Design of an E-MOSFET Bias Network

Problem Statement

Design. An E-MOSFET has \(V_T = 2.5~\text{V}\) and \(k = 0.25~\text{mA/V}^2\). From \(V_{DD} = 15~\text{V}\), design a voltage-divider-biased common-source stage with \(I_D = 3~\text{mA}\), \(V_{DS} = 7~\text{V}\) and a source voltage of 2 V for bias stability. Use E24 resistors and a divider drawing only a few microamps, then verify the design exactly.

Size \(R_S\) and \(R_D\).
Find the required \(V_{GS}\) and \(V_G\), and choose \(R_1\), \(R_2\).
Verify the achieved Q-point with the chosen values and quote the errors.
Confirm saturation and state the available negative drain swing.

Solution

Target: \(I_D = 3~\text{mA}\), \(V_{DS} = 7~\text{V}\), \(V_S = 2~\text{V}\), \(V_{DD} = 15~\text{V}\)
\(V_T = 2.5~\text{V}\), \(k = 0.25~\text{mA/V}^2\), \(I_G = 0\)
E24 resistors; the rounded value is carried forward at every step.

Step 1 — source and drain resistors

\[\begin{aligned} R_S &= \frac{V_S}{I_D} = \frac{2~\text{V}}{3~\text{mA}} = 666.7~\Omega \;\Rightarrow\; R_S = 680~\Omega \\ R_D &= \frac{V_{DD} - V_{DS} - V_S}{I_D} = \frac{15 - 7 - 2}{3~\text{mA}} = 2.000~\text{k}\Omega \;\Rightarrow\; R_D = 2.0~\text{k}\Omega \end{aligned}\]

\(R_S = 680~\Omega\), \(R_D = 2.0~\text{k}\Omega\)

Step 2 — the gate divider

\[\begin{aligned} V_{GS} &= V_T + \sqrt{\frac{I_D}{k}} = 2.5 + \sqrt{\frac{3}{0.25}} = 2.5 + 3.4641 = 5.9641~\text{V} \\ V_G &= V_{GS} + V_S = 5.9641 + 2 = 7.9641~\text{V} \\ \frac{R_2}{R_1 + R_2} &= \frac{7.964}{15} = 0.5309 \end{aligned}\]

Because \(I_G = 0\) the divider may be made very high-impedance. Fix \(R_2 = 1~\text{M}\Omega\); then

\[R_1 = R_2\,\frac{V_{DD} - V_G}{V_G} = 1~\text{M}\Omega\times\frac{7.036}{7.964} = 883.5~\text{k}\Omega \;\Rightarrow\; R_1 = 910~\text{k}\Omega\]

\[V_G = \frac{15(1000)}{910 + 1000} = 7.8534~\text{V},\qquad I_{\text{divider}} = \frac{15~\text{V}}{1.91~\text{M}\Omega} = 7.85~\mu\text{A}\]

\(R_1 = 910~\text{k}\Omega\), \(R_2 = 1~\text{M}\Omega\), giving \(V_G = 7.853~\text{V}\) at 7.85 \(\mu\)A of divider current.

Step 3 — exact verification

\[\begin{aligned} I_D &= 0.25\left(7.853 - 2.5 - 0.68 I_D\right)^2 \\ 0.11560I_D^2 - 2.8202I_D + 7.1647 &= 0 \;\Rightarrow\; I_D = 2.8807~\text{mA} \\ V_S &= 1.959~\text{V},\qquad V_{GS} = 5.8945~\text{V} \\ V_{DS} &= 15 - (2.8807)(2.68) = 7.280~\text{V} \end{aligned}\]

Quantity	Specified	Achieved	Error
\(I_D\) (mA)	3.000	2.881	-3.98%
\(V_{DS}\) (V)	7.000	7.280	4.00%
\(V_S\) (V)	2.000	1.959	-2.06%

Achieved \(I_D = 2.88~\text{mA}\) and \(V_{DS} = 7.28~\text{V}\), both within 4.0% of specification.

Step 4 — saturation and swing

\[\begin{aligned} V_{OV} &= V_{GS} - V_T = 5.895 - 2.5 = 3.395~\text{V} \\ V_{DS} &= 7.280~\text{V} > 3.395~\text{V}\quad\checkmark \\ \Delta V_{D(\text{neg})} &= V_{DS} - V_{OV} = 3.885~\text{V},\qquad g_m = 1.697~\text{mS} \end{aligned}\]

Saturated; the drain may fall 3.89 V before the device enters the ohmic region.

The 4% shortfall in \(I_D\) comes entirely from rounding \(R_1\) down to 910 k\(\Omega\), which drops \(V_G\) by about 0.11 V. With a square-law device the current error is roughly twice the overdrive error, so gate-bias tolerances matter more here than in a BJT divider.