JFET Characteristics and Biasing

About this problem set

Q-point work for the n-channel JFET: Shockley's square law used in both directions, transconductance from the transfer curve, and the fixed-bias, self-bias and voltage-divider topologies solved from the bias quadratic, ending in a full E24 design that is checked for pinch-off operation and device spread.

Each problem below is solved in full — the given data is listed first, the governing relation is stated, and the arithmetic is carried through to a boxed answer. Work through the statement yourself before opening the solution. The underlying theory is covered in the Electronic Devices lecture series.

PROBLEM 01

Shockley Equation and the Transfer Curve

Problem Statement

An n-channel JFET is specified by \(I_{DSS} = 10~\text{mA}\) and a pinch-off voltage \(V_P = V_{GS(\text{off})} = -4~\text{V}\). It is operated in the pinch-off (saturation) region, where the drain current obeys Shockley's law \(I_D = I_{DSS}\left(1 - V_{GS}/V_P\right)^2\).

Find \(I_D\) at \(V_{GS} = -1.5~\text{V}\).
Find the gate-source voltage that produces \(I_D = 2.5~\text{mA}\).
Verify the two standard plotting shortcuts: \(I_D\) at \(V_{GS} = V_P/2\), and \(V_{GS}\) at \(I_D = I_{DSS}/2\).

Solution

\(I_{DSS} = 10~\text{mA}\), \(V_P = -4~\text{V}\) (n-channel, so \(V_P\) is negative)
Pinch-off region assumed throughout, and \(I_G = 0\).

Part (a) — the equation used forwards

\[\begin{aligned} I_D &= I_{DSS}\left(1 - \frac{V_{GS}}{V_P}\right)^2= 10~\text{mA}\left(1 - \frac{-1.5}{-4}\right)^2 \\ &= 10\,(1 - 0.375)^2 = 10\,(0.6250)^2 = 3.906~\text{mA} \end{aligned}\]

\(I_D = 3.91~\text{mA}\)

Part (b) — the equation used backwards

Take the square root and solve for \(V_{GS}\). Only the root that keeps \(V_P < V_{GS} \le 0\) is physical:

\[\begin{aligned} V_{GS} &= V_P\left(1 - \sqrt{\frac{I_D}{I_{DSS}}}\right)= -4\left(1 - \sqrt{\frac{2.5}{10}}\right) \\ &= -4\,(1 - 0.500) = -2.000~\text{V} \end{aligned}\]

\(V_{GS} = -2.00~\text{V}\)

Part (c) — the two plotting shortcuts

\[\begin{aligned} V_{GS} = \tfrac{1}{2}V_P = -2~\text{V}:\quad I_D &= 10\,(1 - 0.5)^2 = 2.500~\text{mA} = \tfrac{1}{4}I_{DSS} \\ I_D = \tfrac{1}{2}I_{DSS} = 5~\text{mA}:\quad V_{GS} &= -4\,(1 - \sqrt{0.5}) = -1.172~\text{V} = 0.293\,V_P \end{aligned}\]

\(V_{GS}\) (V)	\(1 - V_{GS}/V_P\)	\(I_D\) (mA)
0.00	1.000	10.000
-1.00	0.750	5.625
-1.50	0.625	3.906
-2.00	0.500	2.500
-3.00	0.250	0.625
-4.00	0.000	0.000

At \(V_{GS} = V_P/2\), \(I_D = I_{DSS}/4 = 2.50~\text{mA}\); at \(I_D = I_{DSS}/2\), \(V_{GS} = 0.293V_P = -1.17~\text{V}\).

Those two points plus the end points \((0, I_{DSS})\) and \((V_P, 0)\) fix the transfer curve well enough to draw it by hand. Note the curve is not linear: half the gate voltage gives a quarter of the current, not half.

PROBLEM 02

JFET Transconductance from the Shockley Equation

Problem Statement

A JFET has \(I_{DSS} = 8~\text{mA}\) and \(V_{GS(\text{off})} = -4~\text{V}\). Transconductance is the slope of the transfer curve, \(g_m = \partial I_D/\partial V_{GS}\).

Differentiate Shockley's law to obtain \(g_{m0}\), the value at \(V_{GS} = 0\), and evaluate it.
Find \(g_m\) and \(I_D\) at \(V_{GS} = -1~\text{V}\), then confirm \(g_m\) from the alternative form written in terms of \(I_D\).
At what \(V_{GS}\) has \(g_m\) fallen to \(2~\text{mS}\), and what is \(I_D\) there?

Solution

\(I_{DSS} = 8~\text{mA}\), \(V_P = -4~\text{V}\)
Pinch-off region; \(g_m\) quoted in mS (equivalently \(\mu\)S \(\times 10^3\)).

Part (a) — differentiating the square law

\[\begin{aligned} g_m &= \frac{d}{dV_{GS}}\left[I_{DSS}\left(1-\frac{V_{GS}}{V_P}\right)^2\right]= \frac{-2I_{DSS}}{V_P}\left(1-\frac{V_{GS}}{V_P}\right) \\ g_{m0} &\equiv g_m\big|_{V_{GS}=0} = \frac{2I_{DSS}}{|V_P|}= \frac{2(8~\text{mA})}{4~\text{V}} = 4.000~\text{mS} \end{aligned}\]

\(g_{m0} = 4.00~\text{mS} = 4000~\mu\text{S}\)

Part (b) — at \(V_{GS} = -1~\text{V}\)

\[\begin{aligned} g_m &= g_{m0}\left(1 - \frac{V_{GS}}{V_P}\right) = 4.0\left(1 - \frac{-1}{-4}\right) = 4.0(0.75) = 3.000~\text{mS} \\ I_D &= 8\,(0.75)^2 = 4.500~\text{mA} \end{aligned}\]

Cross-check with the form that avoids \(V_{GS}\) altogether:

\[g_m = \frac{2\sqrt{I_{DSS}I_D}}{|V_P|} = \frac{2\sqrt{(8)(4.5)}}{4} = 3.000~\text{mS}\]

\(g_m = 3.00~\text{mS}\) at \(I_D = 4.50~\text{mA}\) — the two routes agree.

Part (c) — where \(g_m\) halves

\[\begin{aligned} \frac{g_m}{g_{m0}} &= 1 - \frac{V_{GS}}{V_P} = \frac{2.0}{4.0} = 0.5 \\ V_{GS} &= 0.5\,V_P = -2.000~\text{V} \\ I_D &= 8\,(0.5)^2 = 2.000~\text{mA} \end{aligned}\]

\(g_m = 2~\text{mS}\) at \(V_{GS} = -2.0~\text{V}\), where \(I_D = 2.00~\text{mA}\).

\(g_m\) falls linearly with \(V_{GS}\) but \(I_D\) falls as the square, so biasing a JFET further towards pinch-off costs gain more slowly than it saves current — the opposite of a BJT, where \(g_m = I_C/V_T\) is strictly proportional to the bias current.

PROBLEM 03

Fixed-Bias JFET Q-Point and Region Check

Problem Statement

A fixed-bias JFET stage runs from \(V_{DD} = 16~\text{V}\). A 2 k\(\Omega\) drain resistor connects the +16 V rail to the drain, the source is grounded, and the gate is returned through a 1 M\(\Omega\) resistor to a \(-2~\text{V}\) bias supply. The device has \(I_{DSS} = 8~\text{mA}\) and \(V_P = -4~\text{V}\).

Find \(V_{GS}\), \(I_D\) and \(V_{DS}\).
Find the node voltages \(V_G\), \(V_S\) and \(V_D\).
Confirm the device is in the pinch-off region and quote \(g_m\) at the Q-point.

Solution

\(V_{DD} = 16~\text{V}\), \(R_D = 2~\text{k}\Omega\), \(R_G = 1~\text{M}\Omega\), \(V_{GG} = -2~\text{V}\)
\(I_{DSS} = 8~\text{mA}\), \(V_P = -4~\text{V}\)
The gate junction is reverse biased, so \(I_G = 0\) and there is no drop across \(R_G\).

Part (a) — gate loop, then drain loop

With \(I_G = 0\) the whole bias supply appears across the gate-source terminals:

\[\begin{aligned} V_{GS} &= -I_G R_G - V_{GG}\;\Rightarrow\; V_{GS} = -2.0~\text{V}\quad(\text{fixed, independent of } I_D) \\ I_D &= I_{DSS}\left(1 - \frac{V_{GS}}{V_P}\right)^2 = 8\left(1 - \frac{-2}{-4}\right)^2 = 8(0.5)^2 = 2.000~\text{mA} \\ V_{DS} &= V_{DD} - I_D R_D = 16 - (2.0~\text{mA})(2~\text{k}\Omega) = 12.000~\text{V} \end{aligned}\]

\(V_{GS} = -2.00~\text{V}\), \(I_D = 2.00~\text{mA}\), \(V_{DS} = 12.0~\text{V}\)

Part (b) — node voltages

\[\begin{aligned} V_S &= 0\ (\text{source grounded}) \\ V_G &= V_{GS} + V_S = -2.00~\text{V} \\ V_D &= V_{DS} + V_S = 12.00~\text{V} \end{aligned}\]

\(V_G = -2.00~\text{V}\), \(V_S = 0\), \(V_D = 12.0~\text{V}\)

Part (c) — region check and \(g_m\)

A JFET stays in pinch-off while \(V_{DS} > V_{GS} - V_P\):

\[\begin{aligned} V_{GS} - V_P &= -2 - (-4) = 2.00~\text{V} \\ V_{DS} &= 12.00~\text{V} \;>\; 2.00~\text{V}\quad\checkmark \\ g_m &= \frac{2I_{DSS}}{|V_P|}\left(1-\frac{V_{GS}}{V_P}\right) = 4.0(0.5) = 2.000~\text{mS} \end{aligned}\]

Pinch-off confirmed with 10.0 V of margin; \(g_m = 2.00~\text{mS}\).

Fixed bias pins \(V_{GS}\) but not \(I_D\): a device from the other end of the same production bin, say \(I_{DSS} = 12~\text{mA}\) with \(V_P = -6~\text{V}\), would give \(I_D = 5.33~\text{mA}\) at the same \(V_{GS}\). That is why fixed bias needs a second supply and still does not hold the Q-point.

PROBLEM 04

Self-Bias JFET Q-Point by Quadratic

Problem Statement

A self-biased JFET stage has no gate supply: a 1 M\(\Omega\) gate resistor returns the gate to ground, a 300 \(\Omega\) source resistor sets the bias, and a 1.8 k\(\Omega\) drain resistor connects the drain to the \(V_{DD} = 20~\text{V}\) rail. The JFET has \(I_{DSS} = 12~\text{mA}\), \(V_P = -3~\text{V}\).

Write the bias equation and solve the resulting quadratic for \(I_D\), saying why one root is discarded.
Find \(V_{GS}\), \(V_S\), \(V_D\) and \(V_{DS}\).
Check the region of operation and find \(g_m\).

Solution

\(I_{DSS} = 12~\text{mA}\), \(V_P = -3~\text{V}\)
\(R_S = 0.3~\text{k}\Omega\), \(R_D = 1.8~\text{k}\Omega\), \(R_G = 1~\text{M}\Omega\), \(V_{DD} = 20~\text{V}\)
\(I_G = 0\), so \(V_G = 0\) and \(I_S = I_D\). Currents in mA, resistances in k\(\Omega\).

Part (a) — the self-bias line meets the transfer curve

The gate sits at ground while the source sits at \(I_D R_S\) above it, so the device biases itself negative:

\[V_{GS} = V_G - V_S = -I_D R_S\]

Substituting into Shockley's law gives one equation in \(I_D\):

\[\begin{aligned} I_D &= I_{DSS}\left(1 + \frac{I_D R_S}{V_P}\right)^2 = 12\left(1 - 0.1I_D\right)^2 \\ 0.1200I_D^2 - 3.4000I_D + 12.0000 &= 0 \\ I_D &= \frac{3.400 \pm \sqrt{5.800}}{2(0.1200)} = 4.132~\text{mA}\ \text{or}\ 24.201~\text{mA} \end{aligned}\]

The large root implies \(V_{GS} = -(24.20)(0.3) = -7.26~\text{V}\), well beyond \(V_P = -3~\text{V}\) — the device would be cut off, so that root is spurious and is discarded.

\(I_{DQ} = 4.13~\text{mA}\)

Part (b) — voltages

\[\begin{aligned} V_{GS} &= -I_D R_S = -(4.132)(0.3) = -1.240~\text{V} \\ V_S &= I_D R_S = 1.240~\text{V},\qquad V_G = 0 \\ V_D &= V_{DD} - I_D R_D = 20 - (4.132)(1.8) = 12.562~\text{V} \\ V_{DS} &= V_D - V_S = 12.562 - 1.240 = 11.323~\text{V} \end{aligned}\]

\(V_{GS} = -1.24~\text{V}\), \(V_S = 1.24~\text{V}\), \(V_D = 12.56~\text{V}\), \(V_{DS} = 11.32~\text{V}\)

Part (c) — region and transconductance

\[\begin{aligned} V_{GS} - V_P &= -1.240 + 3 = 1.760~\text{V} \\ V_{DS} &= 11.32~\text{V} \gg 1.76~\text{V}\quad\checkmark\ \text{pinch-off} \\ g_m &= \frac{2(12)}{3}\left(1 - \frac{-1.240}{-3}\right) = 8.000(0.5868) = 4.694~\text{mS} \end{aligned}\]

Pinch-off region; \(g_m = 4.69~\text{mS}\).

Graphically, part (a) is the intersection of the transfer curve with the straight self-bias line \(I_D = -V_{GS}/R_S\), which passes through the origin with slope \(1/R_S\). A larger \(R_S\) tilts that line down and moves the Q-point towards pinch-off.

PROBLEM 05

Voltage-Divider Bias of a JFET

Problem Statement

A JFET is biased from a single \(V_{DD} = 16~\text{V}\) rail by a divider: \(R_1 = 2.1~\text{M}\Omega\) from the rail to the gate and \(R_2 = 270~\text{k}\Omega\) from the gate to ground. The drain resistor is \(R_D = 2.4~\text{k}\Omega\) and the source resistor \(R_S = 1.5~\text{k}\Omega\). The device has \(I_{DSS} = 8~\text{mA}\), \(V_P = -4~\text{V}\).

Find the gate voltage \(V_G\).
Solve for \(I_D\) and \(V_{GS}\).
Find \(V_D\), \(V_S\) and \(V_{DS}\), and confirm pinch-off operation.

Solution

\(V_{DD} = 16~\text{V}\), \(R_1 = 2.1~\text{M}\Omega\), \(R_2 = 270~\text{k}\Omega\)
\(R_D = 2.4~\text{k}\Omega\), \(R_S = 1.5~\text{k}\Omega\)
\(I_{DSS} = 8~\text{mA}\), \(V_P = -4~\text{V}\), \(I_G = 0\) so the divider is unloaded.

Part (a) — gate voltage

No gate current flows, so the divider is exactly unloaded — unlike the BJT case, no approximation is needed:

\[V_G = \frac{R_2 V_{DD}}{R_1 + R_2} = \frac{(270~\text{k}\Omega)(16~\text{V})}{2100 + 270~\text{k}\Omega} = 1.8228~\text{V}\]

\(V_G = 1.823~\text{V}\)

Part (b) — the bias line and the quadratic

\[\begin{aligned} V_{GS} &= V_G - I_D R_S = 1.8228 - 1.5\,I_D \\ I_D &= 8\left(1 - \frac{1.8228 - 1.5 I_D}{-4}\right)^2 \\ 1.1250I_D^2 - 9.7342I_D + 16.9524 &= 0 \\ I_D &= \frac{9.734 \pm \sqrt{18.468}}{2(1.1250)} = 2.416~\text{mA}\ \text{or}\ 6.236~\text{mA} \end{aligned}\]

The larger root gives \(V_{GS} = -7.53~\text{V}\), past cut-off at \(V_P = -4~\text{V}\), so it is rejected:

\[I_{DQ} = 2.4163~\text{mA},\qquad V_{GSQ} = 1.823 - 1.5(2.4163) = -1.802~\text{V}\]

\(I_{DQ} = 2.42~\text{mA}\), \(V_{GSQ} = -1.80~\text{V}\)

Part (c) — drain circuit and region check

\[\begin{aligned} V_S &= I_D R_S = (2.416)(1.5) = 3.624~\text{V} \\ V_D &= V_{DD} - I_D R_D = 16 - (2.416)(2.4) = 10.201~\text{V} \\ V_{DS} &= V_{DD} - I_D(R_D + R_S) = 16 - (2.416)(3.9) = 6.576~\text{V} \\ V_{GS} - V_P &= 2.198~\text{V} < V_{DS}\quad\checkmark \end{aligned}\]

\(V_S = 3.62~\text{V}\), \(V_D = 10.2~\text{V}\), \(V_{DS} = 6.58~\text{V}\) — comfortably in pinch-off.

Because \(V_G\) is positive, \(R_S\) can be made much larger than in pure self-bias while still delivering the same \(V_{GS}\). The steeper the bias line, the less the Q-point moves when \(I_{DSS}\) and \(V_P\) change from device to device.

PROBLEM 06

Design of a JFET Self-Bias Network

Problem Statement

Design. From a single \(V_{DD} = 18~\text{V}\) rail, bias a JFET with \(I_{DSS} = 10~\text{mA}\) and \(V_P = -4~\text{V}\) at \(I_D = 4~\text{mA}\) with \(V_{DS} = 9~\text{V}\). Round every resistor to the nearest E24 value and carry the rounded value forward.

Choose \(R_S\) for the specified drain current using self-bias, then recompute the achieved \(I_D\).
Choose \(R_D\) for the specified \(V_{DS}\).
Verify that the device is in the pinch-off region and state the margin.
The design is to be built with devices spread over \(I_{DSS} = 8\)-\(10~\text{mA}\) and \(V_P = -3.5\) to \(-4~\text{V}\). Compare the resulting drain-current spread with that of a voltage-divider bias using \(R_1 = 3.3~\text{M}\Omega\), \(R_2 = 910~\text{k}\Omega\) and \(R_S = 1.3~\text{k}\Omega\).

Solution

Target: \(I_D = 4~\text{mA}\), \(V_{DS} = 9~\text{V}\), \(V_{DD} = 18~\text{V}\)
Nominal device: \(I_{DSS} = 10~\text{mA}\), \(V_P = -4~\text{V}\)
\(I_G = 0\); E24 resistor series; pinch-off operation required.

Step 1 — the source resistor

Invert Shockley's law to find the gate-source voltage the target current demands, then let \(R_S\) generate exactly that voltage:

\[\begin{aligned} V_{GS} &= V_P\left(1 - \sqrt{\frac{I_D}{I_{DSS}}}\right) = -4\left(1 - \sqrt{0.4}\right) = -1.4702~\text{V} \\ R_S &= \frac{-V_{GS}}{I_D} = \frac{1.4702~\text{V}}{4~\text{mA}} = 367.5~\Omega \;\Rightarrow\; R_S = 360~\Omega\ \text{(E24)} \end{aligned}\]

Recompute with the rounded value — 360 \(\Omega\) is slightly smaller, so the current comes out slightly high:

\[\begin{aligned} 0.0810I_D^2 - 2.8000I_D + 10.0000 &= 0 \\ I_D &= 4.0447~\text{mA},\qquad V_{GS} = -(4.0447)(0.36) = -1.4561~\text{V} \end{aligned}\]

\(R_S = 360~\Omega\), giving \(I_D = 4.04~\text{mA}\) (1.1% high).

Step 2 — the drain resistor

\[\begin{aligned} V_{DD} &= I_D(R_D + R_S) + V_{DS} \\ R_D + R_S &= \frac{18 - 9}{4.0447~\text{mA}} = 2.2251~\text{k}\Omega \\ R_D &= 2.2251 - 0.360 = 1.8651~\text{k}\Omega \;\Rightarrow\; R_D = 1.8~\text{k}\Omega\ \text{(E24)} \\ V_{DS} &= 18 - (4.0447)(2.16) = 9.263~\text{V} \end{aligned}\]

\(R_D = 1.8~\text{k}\Omega\), giving \(V_{DS} = 9.26~\text{V}\) (2.9% high).

Step 3 — pinch-off verification

\[\begin{aligned} V_{GS} - V_P &= -1.456 + 4 = 2.544~\text{V} \\ V_{DS} &= 9.263~\text{V} > 2.544~\text{V}\quad\checkmark \\ \text{margin} &= 6.720~\text{V},\qquad g_m = 3.180~\text{mS} \end{aligned}\]

Pinch-off with 6.72 V of margin — the drain may swing 6.72 V negative before the device enters the ohmic region.

Step 4 — device spread, self-bias against divider bias

For the divider, \(V_G = 18(910)/(3300+910) = 3.891~\text{V}\), and \(R_S = 1.3~\text{k}\Omega\) is over three times larger for the same nominal \(V_{GS}\). Solving both circuits for the two extreme devices:

Circuit	\(I_D\), nominal device (mA)	\(I_D\), \(I_{DSS}=8~\text{mA}\), \(V_P=-3.5~\text{V}\) (mA)	Change
Self-bias, \(R_S = 360~\Omega\)	4.045	3.392	-16.1%
Divider, \(R_S = 1.3~\text{k}\Omega\)	4.100	3.824	-6.73%

The self-biased Q-point moves by 16.1%, the divider-biased one by only 6.73%.

Both circuits deliver about 4 mA nominally, but the divider does it with a steeper bias line: a large \(R_S\) offset by a positive \(V_G\). The price is the DC drop across \(R_S\), which eats into the available \(V_{DS}\) headroom — the usual bias-stability versus signal-swing trade.