BJT Fundamentals and Characteristics

Six worked problems on the bipolar transistor itself: converting between alpha, beta and gamma, the amplification of leakage current through ICEO = (beta+1)ICBO, reading the region of operation from measured terminal voltages, extracting DC and AC beta and the Early voltage from common-emitter characteristics, checking dissipation against a derated PD,max, and the Q-point spread produced by a 4-to-1 beta range.

Each problem below is solved in full — the given data is listed first, the governing relation is stated, and the arithmetic is carried through to a boxed answer. Work through the statement yourself before opening the solution. The underlying theory is covered in the Electronic Devices lecture series.

For a bipolar transistor the three current gains are \( \alpha = I_C/I_E \) (common base), \( \beta = I_C/I_B \) (common emitter) and \( \gamma = I_E/I_B \) (common collector).

1. A transistor has \( \beta = 120 \) and is biased at \( I_B = 40~\mu\text{A} \). Find \( \alpha \), \( \gamma \), \( I_C \) and \( I_E \).

2. A second transistor has \( \alpha = 0.985 \) and \( I_E = 5~\text{mA} \). Find \( \beta \), \( \gamma \), \( I_C \) and \( I_B \).

3. By how much does \( \beta \) change if \( \alpha \) improves from 0.985 to 0.990?

• KCL for the device: \( I_E = I_C + I_B \).

• Leakage neglected throughout (see the next problem for its effect).

Step 1 — The relations, derived once

Divide \( I_E = I_C + I_B \) by \( I_B \) and by \( I_E \) in turn:

Part (a) — Starting from \( \beta \)

Check: \( I_C/I_E = 4.80/4.84 = 0.99174 = \alpha \;\checkmark \)

(a) \( \alpha = 0.99174 \), \( \gamma = 121 \), \( I_C = 4.80~\text{mA} \), \( I_E = 4.84~\text{mA} \).

Part (b) — Starting from \( \alpha \)

(b) \( \beta = 65.67 \), \( \gamma = 66.67 \), \( I_C = 4.925~\text{mA} \), \( I_B = 75~\mu\text{A} \).

Part (c) — Sensitivity of \( \beta \) to \( \alpha \)

(c) A 0.5% improvement in \( \alpha \) raises \( \beta \) by \( 33.3 \), i.e. by about 51%.

That extreme sensitivity, \( d\beta/d\alpha = 1/(1-\alpha)^2 \), is why \( \beta \) is never a controlled parameter: a data sheet quotes it as a 3-to-1 or 4-to-1 range, and good bias circuits are designed so the answer barely depends on it.

A silicon transistor has \( \beta = 100 \) and a collector–base leakage \( I_{CBO} = 50~\text{nA} \) at \( 25^\circ\text{C} \), doubling for every \( 10^\circ\text{C} \) rise. It is biased at \( I_B = 20~\mu\text{A} \).

1. Find \( I_{CEO} \) and the collector current at \( 25^\circ\text{C} \), and the percentage error made by writing \( I_C = \beta I_B \).

2. Repeat at \( 75^\circ\text{C} \).

3. At what temperature does the leakage contribute 10% of \( I_C \)?

• \( \beta = 100 \), \( I_B = 20~\mu\text{A} \), \( I_{CBO}(25^\circ\text{C}) = 50~\text{nA} \).

• \( I_{CBO} \) doubles per \( 10^\circ\text{C} \); \( \beta \) assumed constant with temperature so that the leakage effect is isolated.

Step 1 — Why the leakage is multiplied by \( \beta + 1 \)

\( I_{CBO} \) is the reverse current of the collector–base junction, measured with the emitter open. In common emitter that current has to leave through the base, where it acts exactly like signal base current and is amplified in its turn. Summing both paths:

Part (a) — At 25 °C

(a) \( I_{CEO} = 5.05~\mu\text{A} \), \( I_C = 2.00505~\text{mA} \); the error in using \( I_C = \beta I_B \) is only \( 0.252~\% \) — entirely negligible.

Part (b) — At 75 °C

(b) At 75 °C, \( I_{CEO} = 161.6~\mu\text{A} \), \( I_C = 2.162~\text{mA} \), an error of \( 8.08~\% \).

Part (c) — The 10% point

Require \( (\beta+1)I_{CBO} = 0.10\,\beta I_B = 200~\mu\text{A} \), i.e. \( I_{CBO} = 1.980~\mu\text{A} \), which is \( 39.6 \) times its 25 °C value:

(c) \( T \approx 78~^\circ\text{C} \).

Leakage grows exponentially while \( \beta I_B \) does not, so a bias design that is fine on the bench can drift badly in a hot enclosure. Germanium, with \( I_{CBO} \) in microamps at room temperature, is a thousand times worse — historically the main reason silicon displaced it.

An npn silicon transistor is wired with \( V_{CC} = +12~\text{V} \), \( R_C = 2.2~\text{k}\Omega \) from the supply to the collector and \( R_E = 1~\text{k}\Omega \) from the emitter to ground; the base is driven from some external network. Three different drive conditions give the terminal voltages below (all measured with respect to ground).

Identify the region of operation in each case, and for the cases where the transistor conducts find \( I_E \), \( I_C \), \( I_B \) and the current gain.

• npn silicon: \( V_{BE(on)} \approx 0.7~\text{V} \), \( V_{BE(sat)} \approx 0.8~\text{V} \), \( V_{CE(sat)} \approx 0.2~\text{V} \).

• \( V_{CC} = 12~\text{V} \), \( R_C = 2.2~\text{k}\Omega \), \( R_E = 1~\text{k}\Omega \).

Step 1 — The test to apply

Read the two junction voltages and classify. For an npn:

Case A

The collector is \( V_{CB} = 7.64 - 2.70 = 4.94~\text{V} \) above the base, so the collector junction is reverse biased: forward-active. Now the currents:

Case A: active; \( I_E = 2.00~\text{mA} \), \( I_C = 1.98~\text{mA} \), \( I_B = 20.0~\mu\text{A} \), \( \beta = 99 \).

Case B

\( V_{CE} \) has collapsed to 0.2 V and the base is \( 0.60~\text{V} \) above the collector, so the collector junction is now forward biased too: saturation.

Case B: saturated; \( I_C = 3.66~\text{mA} \), \( I_B = 100~\mu\text{A} \), forced \( \beta = 36.6 \). The base is driven about \( 2.7\times \) harder than the active region would need.

Case C

\( V_{BE} = 0 \), so no injection occurs; the emitter resistor carries nothing and the collector floats up to the supply through \( R_C \).

Case C: cut-off; \( I_B = I_C = I_E \approx 0 \), \( V_C = 12~\text{V} \).

The quickest field test is the one used above: if \( V_{CE} \) is a couple of tenths of a volt with the base forward biased, the transistor is a closed switch, not an amplifier — and its collector current is then set by the external resistors alone.

The common-emitter output characteristics of a transistor give the following readings.

1. Find \( \beta_{dc} \) at each of the two base currents, at \( V_{CE} = 6~\text{V} \).

2. Find \( \beta_{ac} = h_{fe} \) about that operating point.

3. From the slope at \( I_B = 30~\mu\text{A} \), find the output resistance \( r_o \) and the Early voltage, and hence \( g_m \) and \( r_\pi \) at \( I_C = 3~\text{mA} \).

• Characteristic read at \( V_{CE} = 6~\text{V} \); room temperature, \( V_T = 25.85~\text{mV} \).

• \( \beta_{dc} = I_C/I_B \) at a point; \( \beta_{ac} = \partial I_C/\partial I_B \) at constant \( V_{CE} \).

Part (a) — DC beta

(a) \( \beta_{dc} = 100.0 \) and \( 92.5 \) — it is not a constant, it falls as the device is pushed harder.

Part (b) — AC beta

\( \beta_{ac} \) is the spacing of the curves, not the ratio at a point:

(b) \( \beta_{ac} = h_{fe} = 70 \).

Part (c) — Output resistance, Early voltage and small-signal parameters

Extrapolating the characteristic back to \( I_C = 0 \) gives the Early voltage:

(c) \( r_o = 20~\text{k}\Omega \), \( V_A = 54~\text{V} \), \( g_m = 116.1~\text{mS} \), \( r_\pi = 0.603~\text{k}\Omega \).

\( \beta_{ac} < \beta_{dc} \) here because the curves are crowding together — the device is already past the peak of its gain-versus-current curve. Bias calculations use \( \beta_{dc} \); small-signal gain calculations must use \( \beta_{ac} \).

A transistor in a common-emitter stage has \( V_{CC} = 24~\text{V} \) and a collector resistor \( R_C = 100~\Omega \) (the emitter is grounded). It is biased with \( I_B = 1~\text{mA} \) and has \( \beta = 100 \). The device is rated \( P_{D,\max} = 2~\text{W} \) at \( 25^\circ\text{C} \), derated linearly at \( 16~\text{mW}/^\circ\text{C} \) above that.

1. Find the quiescent point and the dissipation there.

2. Find the worst-case dissipation anywhere on the DC load line.

3. Find the maximum ambient temperature at which the device is safe (i) at the Q-point and (ii) for the worst case, and state the derated rating at \( 60^\circ\text{C} \).

• \( V_{CC} = 24~\text{V} \), \( R_C = 100~\Omega \), \( \beta = 100 \), \( I_B = 1~\text{mA} \).

• \( P_{D,\max} = 2~\text{W} \) at \( 25^\circ\text{C} \), derating \( 16~\text{mW}/^\circ\text{C} \).

• \( P_D \approx V_{CE}I_C \); the base term \( V_{BE}I_B = 0.7~\text{mW} \) is negligible.

Part (a) — Q-point

(a) \( Q = (14~\text{V},\ 100~\text{mA}) \), \( P_D = 1.40~\text{W} \).

Part (b) — Worst point on the load line

Along the load line \( I_C = (V_{CC}-V_{CE})/R_C \), so

a downward parabola in \( V_{CE} \). Differentiating, it peaks at the midpoint \( V_{CE} = V_{CC}/2 \):

(b) \( P_{D,\text{worst}} = 1.44~\text{W} \) at \( V_{CE} = 12~\text{V} \), \( I_C = 120~\text{mA} \).

Part (c) — Derating

(c) Safe to \( 62.5~^\circ\text{C} \) at the Q-point but only to \( 60.0~^\circ\text{C} \) if the signal can swing the operating point to mid-line; the derated rating at \( 60^\circ\text{C} \) is \( 1.44~\text{W} \), exactly the worst-case dissipation.

Note the trap: the quiescent dissipation is not the number to design against. A resistively loaded Class-A stage dissipates most when the output sits at half the supply, so the rating check must be made at \( V_{CC}/2 \), not at the Q-point.

A fixed-bias stage uses \( V_{CC} = 12~\text{V} \), a base resistor \( R_B = 470~\text{k}\Omega \) from the supply to the base, and \( R_C = 2.2~\text{k}\Omega \) in the collector. The transistor is silicon (\( V_{BE} = 0.7~\text{V} \), \( V_{CE(sat)} = 0.2~\text{V} \)) and the data sheet quotes \( \beta \) anywhere from 80 to 320.

1. Find \( I_B \), and the Q-point for \( \beta = 80 \).

2. Find the Q-point for \( \beta = 320 \), and the value of \( \beta \) at which the stage saturates. Hence give the spread in \( I_C \).

3. Design: choose a new \( R_B \) so that the transistor stays in the active region over the whole \( \beta \) range, with \( I_C \) not exceeding 4 mA. Give the resulting Q-point spread.

• \( V_{CC} = 12~\text{V} \), \( R_B = 470~\text{k}\Omega \), \( R_C = 2.2~\text{k}\Omega \), \( \beta = 80 \ldots 320 \).

• Fixed bias: \( I_B \) is set by \( R_B \) alone and does not depend on \( \beta \).

Part (a) — Base current and the low-\( \beta \) corner

(a) \( I_B = 24.04~\mu\text{A} \); with \( \beta = 80 \), \( Q = (7.77~\text{V},\ 1.923~\text{mA}) \) — nicely in the active region.

Part (b) — The high-\( \beta \) corner

Naively, \( I_C = 320 \times 24.04~\mu\text{A} = 7.69~\text{mA} \), which would give \( V_{CE} = 12 - (7.69)(2.2) = -4.93~\text{V} \) — impossible. The transistor has run into saturation, where the collector current is limited by the load line, not by \( \beta \):

Saturation begins when \( \beta I_B \) first reaches this value:

(b) For \( \beta = 320 \) the stage is saturated: \( I_C = 5.364~\text{mA} \), \( V_{CE} = 0.2~\text{V} \). Over the quoted \( \beta \) range \( I_C \) runs from \( 1.923~\text{mA} \) to \( 5.364~\text{mA} \) (a factor \( 2.79 \)) and the stage stops amplifying once \( \beta > 223 \).

Part (c) — Redesigning \( R_B \)

Impose the ceiling at the worst corner, \( \beta = 320 \):

Take the standard \( R_B = 1~\text{M}\Omega \):

(c) \( R_B = 1~\text{M}\Omega \) keeps the transistor active for the whole range: \( I_C \) between \( 0.904~\text{mA} \) and \( 3.616~\text{mA} \), \( V_{CE} \) between \( 4.04~\text{V} \) and \( 10.01~\text{V} \).

The Q-point still moves by the full 4:1 of the \( \beta \) spread — fixed bias cannot do better, because \( I_C = \beta I_B \) with \( I_B \) held constant. All the redesign bought was keeping both corners out of saturation. To make \( I_C \) itself insensitive to \( \beta \) you need emitter degeneration, which is the subject of the biasing problem set.