Q-point calculations for the four standard BJT bias topologies — fixed, emitter, voltage-divider and collector-feedback — together with the stability factor S(ICO) that ranks them, and a full four-resistor bias design worked to standard resistor values.
Each problem below is solved in full — the given data is listed first, the governing relation is stated, and the arithmetic is carried through to a boxed answer. Work through the statement yourself before opening the solution. The underlying theory is covered in the Electronic Devices lecture series.
Fixed-Bias Q-Point and Load-Line Limits
An npn silicon transistor is fixed-biased from a \(V_{CC} = 12~\text{V}\) rail: a 470 k\(\Omega\) resistor runs from the +12 V rail to the base, and a 2.2 k\(\Omega\) collector resistor runs from the same rail to the collector. The emitter is grounded. Take \(\beta = 100\) and \(V_{BE} = 0.7~\text{V}\).
Find the Q-point \( (I_{BQ},\, I_{CQ},\, V_{CEQ}) \).
Locate the two ends of the DC load line and state how far the Q-point sits from saturation.
The transistor is replaced by one with \(\beta = 200\). Recompute \(I_C\) and \(V_{CE}\) and comment.
\(V_{CC} = 12~\text{V}\), \(R_B = 470~\text{k}\Omega\), \(R_C = 2.2~\text{k}\Omega\)
\(\beta = 100\), \(V_{BE} = 0.7~\text{V}\) (silicon, active region assumed)
Part (a) — base loop, then collector loop
The base loop contains only \(V_{CC}\), \(R_B\) and the base–emitter junction, so \(I_B\) is fixed by the supply and is independent of \(\beta\):
\(I_{BQ} = 24.0~\mu\text{A}\), \(I_{CQ} = 2.40~\text{mA}\), \(V_{CEQ} = 6.71~\text{V}\)
Part (b) — load-line end points
Saturation is \(V_{CE} = 0\); cutoff is \(I_C = 0\):
The Q-point sits at \(I_{CQ}/I_{C(\text{sat})} = 44.1\%\) of the saturation current — close to mid-line. The undistorted output swing is limited by the smaller of \(V_{CEQ}\) and \(V_{CC} - V_{CEQ}\):
Load line runs from \((12~\text{V},\,0)\) to \((0,\,5.45~\text{mA})\); maximum symmetrical swing \(\approx 5.29~\text{V}\) peak.
Part (c) — the same circuit with \(\beta = 200\)
\(I_B\) does not change, so \(I_C\) scales directly with \(\beta\):
\(I_C\) changes by 100\% and \(V_{CE}\) falls to \(1.42~\text{V}\) — the stage is driven to the edge of saturation.
Doubling \(\beta\) doubles \(I_C\) exactly, because nothing in the base loop feeds back from the collector. That 1:1 sensitivity is why fixed bias is never used where \(\beta\) spread or temperature matters.
Emitter-Bias Q-Point and Beta Sensitivity
An emitter-biased stage runs from \(V_{CC} = 20~\text{V}\). A 430 k\(\Omega\) resistor connects the +20 V rail to the base, a 2 k\(\Omega\) resistor connects the rail to the collector, and a 1 k\(\Omega\) resistor connects the emitter to ground. \(\beta = 50\), \(V_{BE} = 0.7~\text{V}\).
Find \(I_B\), \(I_C\), \(I_E\) and \(V_{CE}\).
Find the node voltages \(V_B\), \(V_E\) and \(V_C\).
Repeat (a) for \(\beta = 100\) and compare the \(I_C\) sensitivity with fixed bias.
\(V_{CC} = 20~\text{V}\), \(R_B = 430~\text{k}\Omega\), \(R_C = 2~\text{k}\Omega\), \(R_E = 1~\text{k}\Omega\), \(\beta = 50\)
Active region, constant \(\beta\), \(I_E = (\beta+1)I_B\).
Part (a) — base loop with the emitter resistor reflected
Walking the base loop, \(R_E\) is crossed by \(I_E = (\beta+1)I_B\), so it appears in the base circuit as \((\beta+1)R_E\):
\(I_B = 40.1~\mu\text{A}\), \(I_C = 2.01~\text{mA}\), \(I_E = 2.05~\text{mA}\), \(V_{CE} = 13.9~\text{V}\)
Part (b) — node voltages
\(V_B = 2.75~\text{V}\), \(V_E = 2.05~\text{V}\), \(V_C = 16.0~\text{V}\) (check: \(V_C - V_E = 13.9~\text{V} = V_{CE}\)).
Part (c) — \(\beta = 100\)
| Quantity | \(\beta = 50\) | \(\beta = 100\) | Change |
|---|---|---|---|
| \(I_C\) (mA) | 2.01 | 3.63 | \(+81.2\%\) |
| \(V_{CE}\) (V) | 13.9 | 9.06 | \(-4.88~\text{V}\) |
Doubling \(\beta\) raises \(I_C\) by only 81.2\%, against 100\% for fixed bias.
The emitter resistor provides series current feedback: a rise in \(I_C\) raises \(V_E\), which cuts \(V_{BE}\) and pushes \(I_B\) back down. The larger \((\beta+1)R_E\) is compared with \(R_B\), the stiffer that feedback.
Voltage-Divider Bias: Exact versus Approximate
A universal-bias stage has \(V_{CC} = 22~\text{V}\), divider resistors \(R_1 = 39~\text{k}\Omega\) (rail to base) and \(R_2 = 3.9~\text{k}\Omega\) (base to ground), \(R_C = 10~\text{k}\Omega\) and \(R_E = 1.5~\text{k}\Omega\). The transistor is silicon with \(\beta = 140\).
Solve the Q-point exactly using a Thevenin equivalent of the divider.
Solve it again by the approximate (stiff-divider) method, after checking that the method is legal.
Tabulate the two results and quote the percentage error.
\(V_{CC} = 22~\text{V}\), \(R_1 = 39~\text{k}\Omega\), \(R_2 = 3.9~\text{k}\Omega\)
\(R_C = 10~\text{k}\Omega\), \(R_E = 1.5~\text{k}\Omega\), \(\beta = 140\), \(V_{BE} = 0.7~\text{V}\)
Part (a) — exact solution via Thevenin
Look back from the base with \(V_{CC}\) shorted to ground for the resistance, and open-circuit for the voltage:
The base loop is now identical in form to emitter bias:
Exact: \(I_{CQ} = 0.846~\text{mA}\), \(V_{CEQ} = 12.26~\text{V}\)
Part (b) — approximate method
The approximation treats the divider as unloaded, which is safe when the reflected input resistance swamps \(R_2\), i.e. \(\beta R_E \ge 10R_2\):
Approximate: \(I_{CQ} \approx 0.867~\text{mA}\), \(V_{CEQ} \approx 12.03~\text{V}\)
Part (c) — comparison
| Quantity | Exact (Thevenin) | Approximate | Error |
|---|---|---|---|
| \(I_{CQ}\) (mA) | 0.8463 | 0.8667 | \(+2.40\%\) |
| \(V_{CEQ}\) (V) | 12.26 | 12.03 | \(-1.83\%\) |
The approximation is within 2.40\% on \(I_C\) and 1.83\% on \(V_{CE}\) — entirely adequate for design.
Note that the exact \(I_C\) is the smaller one: real base current loads the divider and pulls \(V_B\) down. The error grows quickly once \(\beta R_E\) drops towards \(R_2\).
Collector-Feedback Bias and Its Self-Correction
In a collector-feedback stage the base resistor returns to the collector rather than to the supply. Here \(V_{CC} = 10~\text{V}\), \(R_F = 250~\text{k}\Omega\) from collector to base, \(R_C = 4.7~\text{k}\Omega\) from the rail to the collector and \(R_E = 1.2~\text{k}\Omega\) from emitter to ground. \(\beta = 90\), \(V_{BE} = 0.7~\text{V}\).
Derive the base-loop equation and find \(I_B\), \(I_C\) and \(V_{CE}\).
Recompute for \(\beta = 180\) and quote the percentage change in \(I_C\).
Explain in one sentence the physical mechanism that limits that change.
\(V_{CC} = 10~\text{V}\), \(R_F = 250~\text{k}\Omega\), \(R_C = 4.7~\text{k}\Omega\), \(R_E = 1.2~\text{k}\Omega\)
\(I_B \ll I_C\), so the current in \(R_C\) is taken as \(I_C\) and \(I_E \approx I_C\).
Part (a) — base loop
Start at ground, up through \(R_E\), across the junction, back through \(R_F\), through \(R_C\) to the rail. The current in \(R_C\) is \(I_C + I_B \approx I_C\):
\(I_B = 11.9~\mu\text{A}\), \(I_C = 1.07~\text{mA}\), \(V_{CE} = 3.68~\text{V}\)
Part (b) — \(\beta = 180\)
\(I_C\) rises by only 19.1\% when \(\beta\) doubles.
Part (c) — why
The base resistor is fed from the collector, not the supply. If \(I_C\) tries to rise, \(V_C\) falls, which reduces the voltage across \(R_F\) and therefore reduces \(I_B\) — negative voltage feedback around the device.
Sanity check on the denominator: \(\beta(R_C+R_E) = 531.0~\text{k}\Omega\) is already comparable with \(R_F = 250~\text{k}\Omega\), so \(\beta\) largely cancels between numerator and denominator. Make \(R_F\) small relative to \(\beta(R_C+R_E)\) and the bias becomes almost \(\beta\)-independent.
Stability Factor and Leakage-Driven Q-Point Drift
The stability factor \(S(I_{CO}) = \partial I_C / \partial I_{CO}\) measures how strongly the reverse saturation current pushes the Q-point around. Compare two silicon stages, both with \(\beta = 100\):
Circuit A — fixed bias, base resistor returned to \(V_{CC}\), emitter grounded.
Circuit B — voltage-divider bias with \(R_{Th} = 3.545~\text{k}\Omega\) and \(R_E = 1.5~\text{k}\Omega\).
Evaluate \(S(I_{CO})\) for each circuit.
\(I_{CO} = 0.5~\mu\text{A}\) at 25\(^\circ\)C and doubles for every 10\(^\circ\)C rise. Find \(\Delta I_C\) in each circuit when the junction reaches 65\(^\circ\)C.
State which circuit you would put into production and why.
\(\beta = 100\); Circuit B: \(R_{Th} = 3.545~\text{k}\Omega\), \(R_E = 1.5~\text{k}\Omega\)
\(I_{CO}(25^\circ\text{C}) = 0.5~\mu\text{A}\), doubling every 10\(^\circ\)C
Constant \(\beta\) and constant \(V_{BE}\); only \(I_{CO}\) is allowed to vary.
Part (a) — the two stability factors
The general result for the emitter-biased/divider topology is
Fixed bias is the limit \(R_E \to 0\), i.e. \(R_{Th}/R_E \to \infty\), which gives \(S = \beta+1\):
\(S_A = 101\) (fixed bias), \(S_B = 3.29\) (voltage divider).
Part (b) — leakage rise and the resulting collector-current drift
\(\Delta I_C = 0.757~\text{mA}\) for fixed bias against only \(24.7~\mu\text{A}\) for the divider — a factor of 30.7 better.
Part (c) — verdict
Circuit B. A drift of 0.757 mA is the same order as a typical quiescent current and would move the Q-point by volts; 24.7 \(\mu\)A is negligible. Note that \(S_B\) is set almost entirely by the ratio \(R_{Th}/R_E\), not by \(\beta\): keeping \(R_{Th}\) small (a stiff divider) and \(R_E\) large is what buys the stability, and it is exactly the same design choice that made the approximate analysis valid.
Design of a Voltage-Divider Bias Network
Design. From a \(V_{CC} = 12~\text{V}\) supply, bias a silicon transistor of \(\beta = 100\) at \(I_{CQ} = 2~\text{mA}\), \(V_{CEQ} = 6~\text{V}\) using a four-resistor voltage-divider network. Use the standard rules of thumb \(V_E \approx 0.1V_{CC}\) and \(R_2 \le \beta R_E/10\), and round every resistor to the nearest E24 value. Then verify the design exactly and quote the stability factor you have bought.
Target: \(I_{CQ} = 2~\text{mA}\), \(V_{CEQ} = 6~\text{V}\), \(V_{CC} = 12~\text{V}\), \(\beta = 100\), \(V_{BE} = 0.7~\text{V}\)
Rules: \(V_E = 0.1V_{CC}\); divider bleeder current \(\ge 10 I_B\), enforced as \(R_2 \le \beta R_E/10\).
Step 1 — emitter resistor from the 10\% rule
Step 2 — collector resistor from the collector loop
Step 3 — the divider
The base must sit at \(V_B = V_E + V_{BE} = 1.90~\text{V}\). The 1/10 rule caps \(R_2\):
\(R_1 = 30~\text{k}\Omega\), \(R_2 = 6.2~\text{k}\Omega\), \(R_C = 2.4~\text{k}\Omega\), \(R_E = 620~\Omega\)
Step 4 — exact verification with the chosen E24 values
| Quantity | Specified | Achieved | Error |
|---|---|---|---|
| \(I_{CQ}\) (mA) | 2.000 | 2.000 | \(0.0064\%\) |
| \(V_{CEQ}\) (V) | 6.000 | 5.947 | \(-0.880\%\) |
Design meets \(I_C\) to 0.0064\% and \(V_{CE}\) to 0.880\%, with \(S(I_{CO}) = 8.58\).
The E24 rounding of \(R_E\) from 594.1 \(\Omega\) to 620 \(\Omega\) is absorbed almost perfectly because \(R_1\) was then computed from the actual \(V_B\) — always propagate the rounded value forward rather than restarting from the ideal one.