Switched-Mode Power Supplies and Closed-Loop Control

Because the loop was relying on the electrolytic's ESR zero for its phase margin, and the "improvement" removed it.

The plant's zero. The buck's control-to-output response contains a zero at \( f_{ESR} = 1/(2\pi R_{ESR}C) \), contributed by the capacitor's resistance. A zero adds up to +90° of phase — genuinely useful help against the \( LC \) double pole's −180°.

Put numbers on the change. With \( C = 220\ \mu\text{F} \):

• Electrolytic, \( R_{ESR} = 80\ \text{m}\Omega \): \( f_{ESR} = 9 \) kHz — right at a typical crossover, contributing 40–50° of phase.
• Ceramic, \( R_{ESR} = 3\ \text{m}\Omega \): \( f_{ESR} = 241 \) kHz — far above crossover, contributing essentially nothing.

So the loop lost about 45° of phase margin overnight. If it had 50° before, it now has 5°, which is oscillation.

And a second effect compounds it. The ESR also damped the \( LC \) resonance. Removing it raises the \( Q \) sharply, producing a tall gain peak at \( f_0 \) that can push the loop above unity gain where the phase is already through −180°.

Two more traps in the same substitution:

1. DC bias. A Class-II ceramic marked 220 μF may deliver 80 μF at its working voltage. So \( f_0 \) moves too, and not in a helpful direction.
2. Undamped input filter. Ceramics on the input can resonate with the supply-lead inductance with almost no damping, producing a peak that violates the Middlebrook criterion and destabilises the loop from the input side.

The correct procedure: re-derive the plant with the new capacitor, redesign the compensator (usually adding phase boost to replace what the ESR provided), and add explicit damping — either a small series resistor or a parallel electrolytic acting purely as a damper. Capacitors are not interchangeable on capacitance alone.

Because the primary current is a proxy for the flux, and current-mode control regulates it directly.

The flux-walking mechanism (Chapter 14): in a push–pull or bridge converter, if one half-cycle applies more volt-seconds than the other, the core does not return to its starting flux. The offset accumulates until it saturates.

Voltage mode is blind to it. The pulse ends when the sawtooth crosses the error voltage — a timing decision that carries no information about the core's state. A systematic asymmetry stays systematic.

Current mode measures the thing that matters. In a transformer, \( i_{primary} = i_{magnetising} + i_{load,reflected} \), and \( i_{magnetising} \propto \) flux. So the sensed current contains the flux information. The pulse ends when that current reaches a threshold, which means:

• A half-cycle that starts from an elevated flux reaches the threshold sooner.
• Its pulse is therefore shorter, applying fewer volt-seconds.
• The flux is pushed back toward centre — automatically, every cycle, with no extra components.

This is negative feedback on the flux itself, and it is the main reason current-mode control dominates isolated converter design. The loop-shaping advantages usually cited first are real but secondary.

Two limits worth knowing:

1. It corrects volt-second asymmetry, not asymmetry in the sensing. A current transformer that behaves differently on the two half-cycles introduces its own walk.
2. Above \( D = 0.5 \) it needs slope compensation, and heavy compensation dilutes the flux information — so a heavily compensated current-mode controller balances flux less effectively.

Production practice is to use both defences: current-mode control and a DC blocking capacitor in series with the primary. Neither is expensive, and the failure they prevent destroys the converter.

The energy argument. During the dropout the converter draws its power entirely from the bulk capacitor, whose voltage falls from the nominal rectified value \( V_1 \) to the lowest input the converter can still regulate from, \( V_2 \):

\[ \tfrac12 C(V_1^2 - V_2^2) = P_o\,t_{hold} \;\Longrightarrow\; C = \frac{2P_o t_{hold}}{V_1^2 - V_2^2} \]

A worked instance. A 200 W supply on 230 V AC has \( V_1 \approx 325 \) V. If the converter regulates down to 200 V:

\[ C = \frac{2(200)(0.02)}{325^2 - 200^2} = \frac{8}{65625} = 122\ \mu\text{F} \]

Add 20% for tolerance and end-of-life capacitance loss, and specify 150 μF, 450 V.

What else the requirement affects — and this is the part usually missed:

1. The converter's input range must be wide. Regulating down to 200 V from a 325 V nominal is a 1.6:1 range that exists solely for hold-up. Design the duty ratio and turns ratio accordingly.
2. Inrush current. A 150 μF capacitor charging from a cold mains connection draws hundreds of amps unless limited. An NTC thermistor or a relay-bypassed resistor becomes mandatory.
3. Physical size. A 150 μF, 450 V electrolytic is one of the largest components in the supply and often dictates the enclosure height.
4. Lifetime. Electrolytics age, losing capacitance and gaining ESR. A supply that just meets 20 ms when new may fail at 15 ms after five years — so the design must allow margin, and lifetime calculation at the operating temperature is part of the work.

The design lever. Note that \( C \propto 1/(V_1^2 - V_2^2) \), so widening the converter's input range is far more effective than adding capacitance. Dropping \( V_2 \) from 250 V to 150 V nearly halves the capacitor. This is why hold-up requirements and converter input range are decided together, not separately.

Because phase margin buys damping, and past a certain point extra damping is simply slowness.

The mapping between phase margin and transient response:

• 30°: \( \zeta \approx 0.3 \). Several cycles of ringing, 30–40% overshoot. Marginal.
• 45°: \( \zeta \approx 0.45 \). One small overshoot, quick settling. Acceptable.
• 60°: \( \zeta \approx 0.6 \). Almost no overshoot, fastest overall settling. Optimal.
• 90°: \( \zeta \approx 1 \). No overshoot at all, but a slow exponential approach.

Why 90° hurts in a converter specifically. Achieving it requires rolling the loop gain off much earlier, which lowers the crossover frequency — often by a factor of two or three. And crossover frequency is what determines how fast the loop can correct a load transient.

Follow a 5 A load step through both designs. The output capacitor supplies the step alone until the loop responds. With a 50 kHz crossover the loop reacts in roughly 20 μs; at 15 kHz it takes 70 μs. The voltage dip is more than three times deeper — and the dip is what the specification limits, not the phase margin.

So the objective is not maximum phase margin. It is the highest crossover frequency consistent with adequate margin across the whole operating envelope. Excess margin at nominal is wasted bandwidth.

The one legitimate reason to take more margin is uncertainty. If the plant moves substantially — a wide input range, high-tolerance capacitors, a converter that enters DCM — designing for 60° at nominal may leave only 35° at the corners. Then the extra margin is not conservatism; it is a correct allowance for a plant you cannot pin down. The distinction is whether you have measured the envelope or are guessing at it.

Fixed losses that do not scale with load are now a large fraction of a small output.

Split the losses. At 10% load the current is a tenth, so every \( I^2R \) term is a hundredth of what it was. What remains is everything that runs regardless:

• Gate drive: \( Q_gV_gf \) — the same charge every cycle, whatever the switch carries.
• Switching loss: reduced but not proportionally, since the voltage transitions still happen \( f \) times a second.
• Core loss: set by flux swing, which follows the input voltage and duty ratio, not the load.
• Controller bias, feedback divider, snubbers, bleed resistors: all constant.
• Circulating current if the synchronous rectifier is in forced-CCM mode — actively wasteful at light load.

Every one of those is proportional to \( f \) or is a fixed drain, so the answer is to switch less often. In order of what to try first:

1. Enable diode emulation. Usually a single pin or register change, and it stops the reverse circulating current immediately. Try this first because it costs nothing.
2. Enable burst mode or pulse skipping. Deliver a group of pulses, then idle. The effective frequency falls by orders of magnitude, and 10%-load efficiency typically rises 10–20 points.
3. Frequency foldback if burst mode produces audible or ripple problems — a smooth reduction of \( f \) with load.
4. Reduce the fixed drains: raise the feedback divider's resistance, remove unnecessary bleed resistors, use a controller with a low-power sleep state.
5. Shed phases in a multiphase design — run one instead of four.

The trade to watch. Burst mode increases output ripple, since the output droops between bursts. If the load cannot tolerate that, frequency foldback is the compromise. And burst repetition rates in the audible band can make ceramic capacitors sing — so the burst frequency is chosen deliberately, usually above 20 kHz or below 20 Hz.

Five questions, in this order. Each one eliminates a class of answers, so the order matters.

1. Is isolation required?

• Yes — mains-connected, or a safety standard demands it: Chapter 14. Everything non-isolated is eliminated immediately.
• No — a low-voltage rail from a low-voltage source: Chapters 12 and 13.

2. Up, down, or both?

• Down only: buck — the simplest, most efficient, and the only one with no RHP zero.
• Up only: boost.
• Both: buck–boost, Ćuk, SEPIC, Zeta, or a four-switch buck–boost.

3. What power level? This is where isolated designs separate:

• Below 150 W: flyback.
• 150–500 W: forward, preferably two-switch.
• 500 W–2 kW: half-bridge or full-bridge.
• Above 2 kW: full-bridge, phase-shifted for soft switching.

4. Which port must be quiet?

• Input (battery, PV panel, strict conducted-emissions limit): boost or SEPIC — continuous input current.
• Output (sensitive analogue load, LED string): buck, forward or Zeta — continuous output current.
• Both: Ćuk, or accept two stages.

5. How fast must it respond?

• Fast (a processor rail, a servo): it must be a direct converter — buck or forward. Indirect topologies are capped by their RHP zero.
• Slow is fine (a battery charger, an LED driver): anything.

Why this order. Question 1 is a legal constraint, so it is absolute. Question 2 is arithmetic. Questions 3 and 4 are engineering economics. Question 5 is a control-theory limit that no amount of design effort will circumvent — so it belongs last, where it eliminates what remains rather than everything.

And when the answers conflict — a fast response from a wide-ranging isolated input, say — the resolution is almost always two stages: an indirect stage to make an intermediate bus, then a direct stage to regulate it quickly. Recognising when a single stage cannot satisfy the specification is the most useful judgement in this chapter.