Datasheet parameters turned into circuit numbers: common-mode rejection and the error it leaves at the output, slew-rate limits on sines and square-wave edges, offset voltage and bias-current errors with the compensating resistor, gain-bandwidth product, the desensitivity factor of negative feedback, a full worst-case error budget and an op-amp selection exercise.
Each problem below is solved in full — the given data is listed first, the governing relation is stated, and the arithmetic is carried through to a boxed answer. Work through the statement yourself before opening the solution. The underlying theory is covered in the Electronic Devices lecture series.
Common-Mode Rejection Ratio and Its Output Error
A datasheet quotes an op-amp's open-loop differential gain as \(A_d = 2\times10^{5}\) and its open-loop common-mode gain as \(A_{cm} = 6.5\).
Find the common-mode rejection ratio as a pure ratio and in decibels.
The device is used in a difference amplifier whose closed-loop differential gain is \(A_d' = 50\). CMRR is a property of the device, so the closed-loop common-mode gain is \(A_{cm}' = A_d'/\text{CMRR}\). Find \(A_{cm}'\) and the output error caused by a \(3.0~\text{V}\) common-mode input, and refer that error back to the input.
A \(20~\text{mV}\) differential signal rides on that same \(3.0~\text{V}\) common mode. Find the actual output and the percentage error.
What CMRR, in dB, would the op-amp need for the common-mode error to fall below 0.1% of the wanted output?
\(A_d = 2\times10^{5}\), \(A_{cm} = 6.5\) (open loop)
Closed-loop differential gain \(A_d' = 50\); \(V_{cm} = 3.0~\text{V}\), \(V_d = 20~\text{mV}\)
CMRR is treated as a device parameter, unchanged by the feedback network.
Part (a) — the ratio and its decibel value
CMRR is simply how much harder the amplifier works on the difference than on the average:
\(\text{CMRR} = 30769\), i.e. \(89.8~\text{dB}\)
Part (b) — common-mode gain and error in the closed-loop stage
\(A_{cm}' = 0.00162\); output error \(4.88~\text{mV}\), equivalent to \(97.5~\mu\text{V}\) of spurious differential input.
Part (c) — total output and the error it represents
The two contributions superpose:
\(V_o = 1.0049~\text{V}\) instead of \(1.000~\text{V}\) — an error of \(0.487\%\).
Part (d) — CMRR needed for 0.1% accuracy
Work backwards from the allowed output error:
\(\text{CMRR} \ge 103.5~\text{dB}\)
The general-purpose part is 14 dB short. Notice that the requirement is set by the ratio \(V_{cm}/V_d = 150\) here: the larger the common-mode pedestal a small differential signal has to sit on, the more rejection you must buy.
Open-Loop Gain, Closed-Loop Gain and Gain-Bandwidth Product
An internally compensated op-amp has a DC open-loop gain \(A_{OL} = 2\times10^{5}\) and a unity-gain frequency \(f_T = 1~\text{MHz}\). It is used as a non-inverting amplifier with \(R_f = 99~\text{k}\Omega\) from the output to the inverting input and \(R_1 = 1~\text{k}\Omega\) from that input to ground.
Express the open-loop gain in dB and find the open-loop 3 dB break frequency.
Find the ideal closed-loop gain, the feedback factor, the loop gain and the exact closed-loop gain.
Find the closed-loop 3 dB bandwidth two ways and check that they agree.
Find the closed-loop gain at \(50~\text{kHz}\) and compare it with the open-loop gain there.
What is the largest closed-loop gain that still gives a \(100~\text{kHz}\) bandwidth?
\(A_{OL} = 2\times10^{5}\), \(f_T = 1~\text{MHz}\) (single-pole roll-off, \(-20~\text{dB/decade}\))
\(R_f = 99~\text{k}\Omega\), \(R_1 = 1~\text{k}\Omega\), non-inverting connection
Ideal op-amp apart from the stated gain and bandwidth.
Part (a) — open-loop gain and break frequency
The gain-bandwidth product of a single-pole amplifier is constant and equal to \(f_T\), so the open-loop pole sits at \(f_T/A_{OL}\):
\(A_{OL} = 106.0~\text{dB}\), open-loop bandwidth \(5~\text{Hz}\)
Part (b) — closed-loop gain and loop gain
\(A_{CL} = 99.95\) against the ideal \(100\) — low by \(0.050\%\).
Part (c) — closed-loop bandwidth, two ways
Feedback trades gain for bandwidth by exactly the same factor \(1 + A_{OL}\beta\); the product stays at \(f_T\):
\(f_{3\text{dB}} = 10.01~\text{kHz}\) by either route.
Part (d) — gain at 50 kHz
\(|A_{CL}| = 19.6\) at \(50~\text{kHz}\), essentially riding on the open-loop curve (\(20.0\)).
Part (e) — gain available for a 100 kHz bandwidth
\(A_{CL} \le 10\) — beyond that the bandwidth falls short.
Part (d) is the useful picture: once the loop gain has been spent, the closed-loop response merges into the open-loop roll-off. Above that merge point feedback no longer controls the gain, so distortion and output impedance degrade as well as the gain.
Slew-Rate Limiting of Sine and Square Waveforms
A 741-class op-amp has a slew rate \(SR = 0.5~\text{V}/\mu\text{s}\) and a unity-gain frequency \(f_T = 1~\text{MHz}\). Its output is required to swing \(\pm 10~\text{V}\).
Find the highest frequency at which a 10 V peak sine wave leaves the output undistorted.
At \(50~\text{kHz}\), what is the largest undistorted output amplitude?
The amplifier now drives a \(10~\text{kHz}\) square wave whose output swings from \(-5~\text{V}\) to \(+5~\text{V}\). Find the edge transition time and express it as a fraction of a half period.
Compare that edge with the small-signal rise time the bandwidth alone would allow, and say which mechanism dominates.
What slew rate would be needed to bring the edge down to \(1~\mu\text{s}\)?
\(SR = 0.5~\text{V}/\mu\text{s} = 0.5\times10^{6}~\text{V/s}\), \(f_T = 1~\text{MHz}\)
Sine test: \(V_{pk} = 10~\text{V}\). Square test: \(10~\text{V}\) step at \(10~\text{kHz}\).
Slew limiting is a large-signal effect set by the compensation capacitor charging current; it is independent of the small-signal bandwidth.
Part (a) — full-power bandwidth
For \(v_o = V_{pk}\sin\omega t\) the steepest slope is at the zero crossing, \(\left. dv_o/dt \right|_{\max} = \omega V_{pk}\). Undistorted operation needs that to stay within \(SR\):
\(f_{\max} = 7.96~\text{kHz}\) at \(10~\text{V}\) peak.
Part (b) — amplitude available at 50 kHz
\(V_{pk} = 1.59~\text{V}\) — a factor \(6.28\) below the rail-to-rail capability.
Part (c) — the square-wave edge
The output cannot step; it ramps at the slew rate, so the edge becomes a straight line:
\(t_{\text{edge}} = 20.0~\mu\text{s}\), which is \(40\%\) of the half period — the square wave has become a trapezoid.
Part (d) — bandwidth limit versus slew limit
The bandwidth would allow a \(350~\text{ns}\) edge; slew rate forces \(20.0~\mu\text{s}\), a factor \(57\) worse. Slew rate dominates.
Part (e) — slew rate required for a 1 µs edge
\(SR \ge 10~\text{V}/\mu\text{s}\), i.e. \(20\times\) the present device.
Bandwidth and slew rate are separate specifications and must both be checked. A part can have ample small-signal bandwidth and still turn a large square wave into a triangle, because slew limiting depends on the amplitude as well as the frequency.
Input Offset Voltage, Bias Current and the Compensating Resistor
A non-inverting amplifier uses \(R_f = 100~\text{k}\Omega\) from output to inverting input and \(R_1 = 1~\text{k}\Omega\) from that input to ground. The op-amp has an input offset voltage \(V_{io} = 2~\text{mV}\), an input bias current \(I_B = 80~\text{nA}\) and an input offset current \(I_{io} = 20~\text{nA}\), all worst case.
Find the output error produced by \(V_{io}\) alone.
With the non-inverting input returned directly to ground, find the output error produced by \(I_B\).
Choose the compensating resistor \(R_{comp}\) and find the residual current-driven error once it is fitted.
Add the terms and state the total worst-case output offset, with and without compensation.
The same gain is built with \(R_f = 10~\text{k}\Omega\), \(R_1 = 100~\Omega\). Recompute the total error and comment.
\(R_f = 100~\text{k}\Omega\), \(R_1 = 1~\text{k}\Omega\) \(\Rightarrow\) noise gain \(1 + R_f/R_1 = 101\)
\(V_{io} = 2~\text{mV}\), \(I_B = 80~\text{nA}\), \(I_{io} = 20~\text{nA}\)
Each error source is evaluated on its own with the signal set to zero, then summed worst case (the polarities are not specified, so they are taken as adding).
Part (a) — offset voltage
\(V_{io}\) sits in series with the input, so it is amplified by the noise gain — the gain the amplifier presents to anything appearing at its own input terminals:
\(V_{o(io)} = 202~\text{mV}\)
Part (b) — bias current with no compensation
With the \(+\) input grounded, the bias current of the \(-\) input has nowhere to go but \(R_f\) (the inverting node is held at \(0~\text{V}\), so no current flows in \(R_1\)):
\(V_{o(I_B)} = 8.0~\text{mV}\)
Part (c) — the compensating resistor
Put an equal DC resistance in each input path. The \(-\) input sees \(R_1 \parallel R_f\) looking outward, so the same value goes in series with the \(+\) input; the two bias currents then develop equal voltages that cancel as a common mode, and only the mismatch \(I_{io}\) survives:
\(R_{comp} = 990~\Omega\) (nearest standard value \(1~\text{k}\Omega\)); residual error \(2.0~\text{mV}\), a factor \(4\) smaller.
Part (d) — worst-case totals
| Source | Without \(R_{comp}\) | With \(R_{comp}\) |
|---|---|---|
| \(V_{io}\times\) noise gain | 202 mV | 202 mV |
| Current term \(\times R_f\) | 8.0 mV | 2.0 mV |
| Worst-case total | 210.0 mV | 204.0 mV |
\(210~\text{mV}\) uncompensated, \(204~\text{mV}\) compensated — equivalent to \(2.02~\text{mV}\) at the input.
Part (e) — same gain, smaller resistors
Total falls to \(202.2~\text{mV}\) — the current-driven part scales directly with \(R_f\).
The \(V_{io}\) term is untouched by resistor scaling and dominates here: a \(20~\text{mV}\) input gives \(2.02~\text{V}\) of signal, so \(204~\text{mV}\) of offset is \(10.1\%\) of full scale. Low-resistance networks fix the current errors; only a low-offset part (or a null trim) fixes the voltage error.
Desensitivity Factor and the Effects of Negative Feedback
An op-amp with open-loop gain \(A = 2\times10^{5}\), input resistance \(Z_i = 2~\text{M}\Omega\), output resistance \(Z_o = 75~\Omega\) and an open-loop break frequency of \(5~\text{Hz}\) is connected as a non-inverting amplifier with feedback factor \(\beta = 0.01\).
Find the loop gain, the desensitivity factor \(1 + A\beta\) and the closed-loop gain. Compare with the ideal value \(1/\beta\).
Temperature and device spread drop \(A\) to \(5\times10^{4}\). Find the new closed-loop gain and compare the two percentage changes.
Find the closed-loop input and output resistances.
Find the closed-loop bandwidth and verify that the gain-bandwidth product is unchanged.
\(A = 2\times10^{5}\), \(\beta = 0.01\), \(Z_i = 2~\text{M}\Omega\), \(Z_o = 75~\Omega\)
Open-loop break frequency \(f_{OL} = 5~\text{Hz}\); series-shunt (voltage-series) feedback.
Part (a) — desensitivity and closed-loop gain
\(1 + A\beta = 2001\), \(A_f = 99.95\), within \(0.050\%\) of \(1/\beta\).
Part (b) — gain stability
The general result behind those two numbers is
A \(75\%\) collapse of the open-loop gain moves the closed-loop gain by only \(0.150\%\) — a desensitivity of about \(501\times\).
Part (c) — impedances
Series input sampling raises the input resistance and shunt output sampling lowers the output resistance, both by the same factor:
\(Z_{if} = 4.00~\text{G}\Omega\), \(Z_{of} = 37.5~\text{m}\Omega\)
Part (d) — bandwidth
\(f_{CL} = 10.01~\text{kHz}\); the gain-bandwidth product is unchanged at \(1.00~\text{MHz}\).
One factor, \(1 + A\beta\), does all four jobs: it divides the gain and its sensitivity, multiplies the input resistance and the bandwidth, and divides the output resistance. Everything feedback gives you is bought with surplus open-loop gain.
Which Limit Binds — Bandwidth or Slew Rate
An op-amp has \(GBW = 3~\text{MHz}\) and \(SR = 13~\text{V}/\mu\text{s}\). It must deliver a \(10~\text{V}\) peak sine wave.
For a non-inverting gain of \(20\), find the small-signal bandwidth and the slew rate the output would demand at that frequency. Which limit binds?
Repeat for a gain of \(5\).
Find the full-power bandwidth of the device at \(10~\text{V}\) peak.
For the gain of \(5\), state the largest input amplitude that stays undistorted right up to the small-signal bandwidth.
\(GBW = 3~\text{MHz}\), \(SR = 13~\text{V}/\mu\text{s} = 13\times10^{6}~\text{V/s}\)
Required output \(V_{pk} = 10~\text{V}\); single-pole roll-off assumed.
Two independent ceilings: \(f_{3\text{dB}} = GBW/A_{CL}\) (small signal) and \(f_{\max} = SR/2\pi V_{pk}\) (large signal). The lower one governs.
Part (a) — gain of 20
\(f_{3\text{dB}} = 150~\text{kHz}\); the demand of \(9.42~\text{V}/\mu\text{s}\) is inside the \(13~\text{V}/\mu\text{s}\) capability, so bandwidth is the binding limit.
Part (b) — gain of 5
The demand \(37.7~\text{V}/\mu\text{s}\) exceeds \(13~\text{V}/\mu\text{s}\), so slew rate binds long before the bandwidth does.
Part (c) — full-power bandwidth
\(f_{\max} = 207~\text{kHz}\) at full \(10~\text{V}\) output, regardless of the closed-loop gain.
Part (d) — usable input at the gain of 5
\(v_{in} \le 0.690~\text{V}\) peak (\(3.45~\text{V}\) at the output).
The two ceilings cross at the full-power bandwidth. Below a closed-loop gain of \(GBW/f_{\max} = 14.5\) the part is slew limited at full output; above it, bandwidth limited. Reducing the required output swing is often the cheapest way to buy back frequency response.
Worst-Case Error Budget of a Precision DC Amplifier
Error budget. A thermocouple delivering a steady \(5.00~\text{mV}\) drives a non-inverting DC amplifier with \(R_1 = 100~\Omega\) and \(R_f = 99.9~\text{k}\Omega\). The op-amp has \(A_{OL} = 10^{5}\), \(V_{io} = 150~\mu\text{V}\), \(I_{io} = 5~\text{nA}\) (a compensating resistor is fitted, so \(I_B\) cancels) and \(\text{CMRR} = 100~\text{dB}\).
Find the ideal output.
Find the error caused by finite open-loop gain.
Find the errors caused by \(V_{io}\), by \(I_{io}\), and by finite CMRR.
Assemble the worst-case error budget and identify the dominant term.
State what the op-amp would need for a total error below 0.1%.
\(V_{in} = 5.00~\text{mV}\) DC, \(R_1 = 100~\Omega\), \(R_f = 99.9~\text{k}\Omega\)
\(A_{OL} = 10^{5}\), \(V_{io} = 150~\mu\text{V}\), \(I_{io} = 5~\text{nA}\), \(\text{CMRR} = 100~\text{dB}\)
\(R_{comp} = R_1 \parallel R_f\) is fitted, so only the offset current contributes.
Step 1 — the ideal answer
Ideal \(V_o = 5.000~\text{V}\)
Step 2 — finite open-loop gain
Gain error \(-0.990\%\), i.e. \(-49.5~\text{mV}\) at the output. Note the loop gain is only \(100\) at this closed-loop gain.
Step 3 — the three input-referred error sources
In the non-inverting connection the common-mode input is the signal itself, \(V_{cm} = 5.00~\text{mV}\), which is why the CMRR term is negligible here.
\(150~\text{mV}\) from \(V_{io}\), \(500~\mu\text{V}\) from \(I_{io}\), \(50~\mu\text{V}\) from CMRR.
Step 4 — the budget
| Error source | Output error | Fraction of 5 V |
|---|---|---|
| Finite open-loop gain | -49.5 mV | 0.990% |
| Input offset voltage | ±150.0 mV | 3.000% |
| Input offset current | ±0.500 mV | 0.0100% |
| Finite CMRR | ±0.050 mV | 0.00100% |
| Worst-case total | 200.1 mV | 4.00% |
Worst-case output error \(200~\text{mV}\) on \(5.00~\text{V}\), i.e. \(4.00\%\); the offset voltage supplies \(75\%\) of it.
Step 5 — what 0.1% would take
\(V_{io} \le 5~\mu\text{V}\) and \(A_{OL} \ge 120~\text{dB}\) — a chopper-stabilised or auto-zero amplifier.
The lesson of the table is that at a gain of 1000 nothing matters except offset voltage and loop gain. Chasing resistor tolerances or bias current here would be wasted effort.
Design — Selecting an Op-Amp Against a Full Specification
Design. Select an op-amp for a non-inverting amplifier that must meet all of the following:
closed-loop gain \(A_{CL} = 25\);
output \(8~\text{V}\) peak sine at frequencies up to \(40~\text{kHz}\), undistorted;
gain flat to within 1% at \(40~\text{kHz}\);
untrimmed output offset no worse than \(20~\text{mV}\);
at least 20% slew-rate margin over the theoretical requirement.
The candidate parts are:
| Part | \(SR\) (V/\(\mu\)s) | \(GBW\) (MHz) | \(V_{io}\) (mV) |
|---|---|---|---|
| A | 0.5 | 1.0 | 2.00 |
| B | 13.0 | 3.0 | 3.00 |
| C | 12.0 | 5.0 | 3.00 |
| D | 2.8 | 8.0 | 0.03 |
| E | 20.0 | 4.0 | 0.30 |
| F | 70.0 | 15.0 | 4.00 |
Derive the three numerical requirements, screen the table, choose a part, justify the choice and complete the resistor design.
\(A_{CL} = 25\), \(V_{pk} = 8~\text{V}\), \(f_{\max} = 40~\text{kHz}\)
Amplitude droop \(\le 1\%\) at \(40~\text{kHz}\); output offset \(\le 20~\text{mV}\)
Slew-rate margin \(\ge 20\%\); single-pole roll-off assumed for every candidate.
Step 1 — the slew-rate requirement
Step 2 — the gain-bandwidth requirement
A 1% droop is a much tighter demand than a 3 dB corner. Set the single-pole magnitude equal to 0.99 and solve for the corner:
Step 3 — the offset requirement
Screen on \(SR \ge 2.41~\text{V}/\mu\text{s}\), \(GBW \ge 7.02~\text{MHz}\), \(V_{io} \le 0.8~\text{mV}\).
Step 4 — screening the candidates
| Part | \(SR\) | \(GBW\) | \(V_{io}\) | \(SR\) test | \(GBW\) test | \(V_{io}\) test | Verdict |
|---|---|---|---|---|---|---|---|
| A | 0.5 | 1.0 | 2.00 | FAIL | FAIL | FAIL | reject |
| B | 13.0 | 3.0 | 3.00 | pass | FAIL | FAIL | reject |
| C | 12.0 | 5.0 | 3.00 | pass | FAIL | FAIL | reject |
| D | 2.8 | 8.0 | 0.03 | pass | pass | pass | accept |
| E | 20.0 | 4.0 | 0.30 | pass | FAIL | pass | reject |
| F | 70.0 | 15.0 | 4.00 | pass | pass | FAIL | reject |
Parts B, C and E have plenty of slew rate but too little gain-bandwidth for a 1% flat response at a gain of 25; F has the bandwidth but a 4 mV offset gives \(4~\text{mV} \times 25 = 100~\text{mV}\) at the output; A fails on all three.
Part D is the only candidate that passes every test.
Step 5 — verifying part D
Step 6 — the resistor network
Choose part D; \(R_1 = 1~\text{k}\Omega\), \(R_f = 24~\text{k}\Omega\), \(R_{comp} = 1~\text{k}\Omega\). Achieved: droop \(0.77\%\), slew margin \(39\%\), full-power bandwidth \(56~\text{kHz}\), offset \(0.75~\text{mV}\).
Note which specification did the selecting: the 1% flatness demanded \(7.0~\text{MHz}\) of gain-bandwidth, seven times what a bare \(-3~\text{dB}\) corner at \(40~\text{kHz}\) would need. Flatness, not the corner frequency, is what usually sets the part.