Clipper and Clamper Circuits

About this problem set

Worked problems on diode wave shaping: series and shunt clippers, biased and double-ended limiters, positive and negative clampers with the RC time-constant condition, and the design of a biased clamper to a specified output swing. All waveforms are described in words with explicit numerical levels.

Each problem below is solved in full — the given data is listed first, the governing relation is stated, and the arithmetic is carried through to a boxed answer. Work through the statement yourself before opening the solution. The underlying theory is covered in the Electronic Devices lecture series.

PROBLEM 01

Series Clipper Output Levels

Problem Statement

A silicon diode is connected in series between a signal source and a \( 2.2~\text{k}\Omega \) load resistor to ground, with the diode's anode facing the source. The input is a sine wave of \( 10~\text{V} \) peak at \( 1~\text{kHz} \).

Describe the output waveform and give its positive and negative extremes.
Find the peak load current and the fraction of each cycle for which the diode conducts.
What is the average (DC) value of the output?

Solution

\( v_i = 10\sin\omega t~\text{V} \), \( f = 1~\text{kHz} \), \( R_L = 2.2~\text{k}\Omega \)
Silicon diode, constant-drop model \( V_D = 0.7~\text{V} \), anode towards the source

Step 1 — Which half survives

Positive half cycle: the anode is driven positive, so once \( v_i > 0.7~\text{V} \) the diode conducts and behaves as a \( 0.7~\text{V} \) battery in series with the load: \( v_o = v_i - 0.7 \).
Negative half cycle: the diode is reverse biased and open. No current flows in \( R_L \), so \( v_o = 0 \) — the whole negative loop is removed.

\[\begin{aligned} v_{o,\max} &= V_p - V_D = 10 - 0.7 = 9.3~\text{V} \\ v_{o,\min} &= 0~\text{V} \end{aligned}\]

The output is therefore the top half of the sine, flattened onto the zero line for the whole negative half cycle, with its peak pulled down from \( 10~\text{V} \) to \( 9.3~\text{V} \). The negative-going swing appears entirely across the diode, which must withstand a peak reverse voltage of \( 10~\text{V} \).

(a) Positive half-sine peaking at \( +9.3~\text{V} \); output is \( 0~\text{V} \) for the whole negative half cycle.

Step 2 — Current and conduction angle

\[\begin{aligned} I_{m} &= \frac{V_p - V_D}{R_L} = \frac{9.3}{2200} = 4.23~\text{mA} \\ \theta_1 &= \sin^{-1}\!\left(\frac{0.7}{10}\right) = 4.01^\circ \\ \text{conduction} &= 180^\circ - 2(4.01^\circ) = 172^\circ = 47.8\%\text{ of the cycle} \end{aligned}\]

(b) \( I_{m} = 4.23~\text{mA} \); the diode conducts for \( 172^\circ \), i.e. \( 47.8\% \) of each cycle.

Step 3 — DC value

\[\begin{aligned} V_{dc} &\approx \frac{V_p - V_D}{\pi} = \frac{9.3}{\pi} = 2.96~\text{V} \end{aligned}\]

A series clipper is electrically the same circuit as a half-wave rectifier — the name changes only with the intent, signal shaping rather than power conversion.

PROBLEM 02

Shunt Clipper with a Silicon Diode

Problem Statement

A \( 1~\text{k}\Omega \) resistor is in series between the source and the output node, and a silicon diode is connected from the output node to ground with its anode at the output node. The input is \( v_i = 12\sin\omega t~\text{V} \); the output is taken across the diode and is unloaded.

Sketch (in words) the output waveform, giving both levels.
Find the peak diode current and the peak power in the series resistor.
What changes if the diode is reversed?

Solution

\( v_i = 12\sin\omega t~\text{V} \), \( R = 1~\text{k}\Omega \), no load across the output
Si diode from output to ground, anode up; \( V_D = 0.7~\text{V} \), \( r_f \approx 0 \)

Step 1 — Behaviour in each half cycle

Positive half: as soon as \( v_o \) tries to exceed \( 0.7~\text{V} \) the diode turns on and holds the node at \( +0.7~\text{V} \). The remaining \( (v_i - 0.7) \) is dropped across \( R \). The positive peaks are therefore clipped flat at \( +0.7~\text{V} \).
Negative half: the diode is reverse biased and open. With no load, no current flows in \( R \), so there is no drop across it and \( v_o = v_i \) — the negative loop is reproduced in full down to \( -12~\text{V} \).

\[\begin{aligned} v_{o} &= +0.7~\text{V} \quad\text{(flat top, whenever } v_i > 0.7~\text{V)} \\ v_{o} &= v_i \quad\text{(down to } -12~\text{V)} \end{aligned}\]

Clipping begins at \( \theta = \sin^{-1}(0.7/12) = 3.34^\circ \) and ends at \( 176.7^\circ \), so the flat top occupies \( 48.1\% \) of the cycle.

(a) Output swings between \( +0.7~\text{V} \) (clipped flat) and \( -12~\text{V} \) (unclipped negative half-sine).

Step 2 — Diode current and resistor power

\[\begin{aligned} I_{D(\max)} &= \frac{v_{i(\max)} - 0.7}{R} = \frac{12 - 0.7}{1000} = 11.3~\text{mA} \\ p_{R(\max)} &= \frac{(12 - 0.7)^2}{1000} = 128~\text{mW} \end{aligned}\]

(b) \( I_{D(\max)} = 11.3~\text{mA} \), peak resistor power \( = 128~\text{mW} \) — a \( \tfrac14~\text{W} \) resistor is adequate since the average is far lower.

Step 3 — Reversed diode

(c) With the diode reversed (cathode at the output node) the negative peaks are clipped flat at \( -0.7~\text{V} \) and the positive half-sine passes intact to \( +12~\text{V} \).

The series resistor is essential: it absorbs the difference \( v_i - v_o \) during clipping. Make it too small and the diode is destroyed; too large and the source impedance of the clipper becomes unusable.

PROBLEM 03

Biased Shunt Clipper at a Chosen Level

Problem Statement

A shunt clipper has a \( 2.2~\text{k}\Omega \) series resistor. From the output node to ground there is a silicon diode (anode at the output node) in series with a \( 5~\text{V} \) battery whose positive terminal faces the diode's cathode. The input is \( v_i = 15\sin\omega t~\text{V} \).

At what level is the output clipped?
Over what portion of the cycle does clipping occur?
Find the peak diode current and the peak reverse voltage across the diode.

Solution

\( v_i = 15\sin\omega t~\text{V} \), \( R = 2.2~\text{k}\Omega \), \( V_B = 5~\text{V} \)
Si diode, \( V_D = 0.7~\text{V} \); output unloaded

Step 1 — Clipping level

The diode conducts only when the output node exceeds the battery voltage plus the diode's cut-in voltage. Once it does, the node is held at that sum.

\[\begin{aligned} V_{clip} &= V_B + V_D = 5 + 0.7 = 5.7~\text{V} \end{aligned}\]

So the output follows \( v_i \) everywhere below \( 5.7~\text{V} \) — including the entire negative half cycle down to \( -15~\text{V} \) — and is flat-topped at \( +5.7~\text{V} \) whenever \( v_i \) would have gone higher.

(a) The positive peaks are clipped flat at \( +5.7~\text{V} \); the negative peak is unaffected at \( -15~\text{V} \).

Step 2 — Clipping interval

\[\begin{aligned} \theta_1 &= \sin^{-1}\!\left(\frac{V_{clip}}{V_p}\right) = \sin^{-1}\!\left(\frac{5.7}{15}\right) = 22.3^\circ \\ \theta_2 &= 180^\circ - \theta_1 = 157.7^\circ \\ \Delta\theta &= 135.3^\circ = 37.6\%\text{ of the period} \end{aligned}\]

(b) Clipping runs from \( 22.3^\circ \) to \( 157.7^\circ \), i.e. for \( 135.3^\circ \) of every cycle.

Step 3 — Diode stresses

At the positive input peak all the excess appears across \( R \); at the negative input peak the diode is reverse biased by the input and the battery.

\[\begin{aligned} v_{R(\max)} &= V_p - V_{clip} = 15 - 5.7 = 9.3~\text{V} \\ I_{D(\max)} &= \frac{9.3}{2200} = 4.23~\text{mA} \\ \text{PIV} &= V_p + V_B = 15 + 5 = 20~\text{V} \end{aligned}\]

Reversing both the diode and the battery clips the negative peaks at \( -5.7~\text{V} \) instead; reversing the battery alone moves the clipping level down to \( -5 + 0.7 = -4.3~\text{V} \), which clips most of the waveform away.

PROBLEM 04

Double-Ended Limiter Between Two Levels

Problem Statement

A two-level limiter has a \( 1~\text{k}\Omega \) series resistor and two shunt branches from the output node to ground:

\( D_1 \) with its anode at the output node, in series with a \( 6~\text{V} \) battery (positive terminal towards \( D_1 \)'s cathode).
\( D_2 \) with its cathode at the output node, in series with a \( 3~\text{V} \) battery (negative terminal towards \( D_2 \)'s anode).

Both are silicon. The input is \( v_i = 12\sin\omega t~\text{V} \) at \( 2~\text{kHz} \).

Find the upper and lower output limits and describe the waveform.
Find the fraction of the cycle over which the output is not clipped.
Find the peak current in each diode.

Solution

\( V_p = 12~\text{V} \), \( R = 1~\text{k}\Omega \), \( V_{B1} = 6~\text{V} \), \( V_{B2} = 3~\text{V} \)
Si diodes, \( V_D = 0.7~\text{V} \); only one diode can conduct at a time

Step 1 — The two limits

\( D_1 \) conducts when \( v_o > V_{B1} + V_D \) and then holds the node there.
\( D_2 \) conducts when \( v_o < -(V_{B2} + V_D) \) and then holds the node there.
Between the two thresholds both diodes are off; with no load there is no drop across \( R \), so \( v_o = v_i \).

\[\begin{aligned} V_{o(\text{upper})} &= +\left(V_{B1} + V_D\right) = 6 + 0.7 = +6.7~\text{V} \\ V_{o(\text{lower})} &= -\left(V_{B2} + V_D\right) = -(3 + 0.7) = -3.7~\text{V} \\ V_{o(p\text{-}p)} &= 6.7 - (-3.7) = 10.4~\text{V} \end{aligned}\]

The output is the \( 12~\text{V} \) sine with its top sliced off flat at \( +6.7~\text{V} \) and its bottom sliced off flat at \( -3.7~\text{V} \) — a sine-cornered trapezoid, asymmetric because the two bias levels differ.

(a) Output limited between \( -3.7~\text{V} \) and \( +6.7~\text{V} \), total swing \( 10.4~\text{V} \) peak-to-peak.

Step 2 — Unclipped fraction

\[\begin{aligned} \theta_{1} &= \sin^{-1}\!\left(\frac{6.7}{12}\right) = 33.9^\circ \;\Rightarrow\; \text{top clipped for } 180^\circ - 2\theta_1 = 112.1^\circ \\ \theta_{2} &= \sin^{-1}\!\left(\frac{3.7}{12}\right) = 18^\circ \;\Rightarrow\; \text{bottom clipped for } 144.1^\circ \\ \text{unclipped} &= 360^\circ - 112.1^\circ - 144.1^\circ = 103.8^\circ \end{aligned}\]

(b) The output tracks the input for \( 103.8^\circ \), i.e. \( 28.8\% \) of each cycle.

Step 3 — Peak diode currents

\[\begin{aligned} I_{D1(\max)} &= \frac{V_p - (V_{B1} + V_D)}{R} = \frac{12 - 6.7}{1000} = 5.3~\text{mA} \\ I_{D2(\max)} &= \frac{V_p - (V_{B2} + V_D)}{R} = \frac{12 - 3.7}{1000} = 8.3~\text{mA} \end{aligned}\]

Drive the input hard enough and the output tends to a square wave switching between \( -3.7~\text{V} \) and \( +6.7~\text{V} \); this is exactly how a diode limiter is used to protect an input stage or to square up a sine.

PROBLEM 05

Positive and Negative Clamper Circuits

Problem Statement

A square wave of \( \pm 10~\text{V} \) at \( 1~\text{kHz} \) drives a clamper made of a \( 1~\mu\text{F} \) series capacitor, a silicon diode from the output node to ground, and a \( 100~\text{k}\Omega \) load.

Check the time-constant condition \( \tau = RC \gg T \).
With the diode's cathode at the output node, find the capacitor voltage, the output levels and the DC shift (negative clamper).
Repeat with the diode reversed (positive clamper), and estimate the tilt on the flat tops.

Solution

\( v_i = \pm10~\text{V} \) square, \( f = 1~\text{kHz} \Rightarrow T = 1~\text{ms} \)
\( C = 1~\mu\text{F} \), \( R = 100~\text{k}\Omega \), Si diode \( V_D = 0.7~\text{V} \)
A clamper shifts the waveform bodily; it never changes the peak-to-peak swing (\( 20~\text{V} \) here)

Step 1 — Time-constant check

The capacitor must hold its charge almost unchanged between the brief conduction pulses, so the discharge time constant has to swamp the period.

\[\begin{aligned} \tau &= RC = (100\times10^{3})(1\times10^{-6}) = 100~\text{ms} \\ \frac{\tau}{T} &= \frac{100~\text{ms}}{1~\text{ms}} = 100 \end{aligned}\]

(a) \( \tau = 100~\text{ms} = 100T \), far above the usual requirement \( \tau \ge 10T \) ✓

Step 2 — Negative clamper (cathode at the output)

On the first positive excursion the diode conducts and charges \( C \) to \( V_C = V_p - V_D = 10 - 0.7 = 9.3~\text{V} \), positive on the source side.
Thereafter the diode is off and \( C \) acts as a battery in series with the input: \( v_o = v_i - 9.3~\text{V} \).

\[\begin{aligned} v_{o}(\text{during } v_i = +10) &= 10 - 9.3 = +0.7~\text{V} \\ v_{o}(\text{during } v_i = -10) &= -10 - 9.3 = -19.3~\text{V} \\ \text{swing} &= 0.7 - (-19.3) = 20~\text{V (unchanged)} \end{aligned}\]

(b) \( V_C = 9.3~\text{V} \); output square wave sits between \( +0.7~\text{V} \) and \( -19.3~\text{V} \), a DC shift of \( -9.3~\text{V} \).

Step 3 — Positive clamper and tilt

Reversing the diode makes it conduct on the negative excursion instead; the capacitor charges to the same \( 9.3~\text{V} \) but with the opposite polarity, so \( v_o = v_i + 9.3~\text{V} \).

\[\begin{aligned} v_{o}(\text{during } v_i = -10) &= -10 + 9.3 = -0.7~\text{V} \\ v_{o}(\text{during } v_i = +10) &= 10 + 9.3 = +19.3~\text{V} \end{aligned}\]

During the non-conducting half the capacitor bleeds into \( R \), so each flat top sags:

\[\begin{aligned} \Delta V &\approx v_{o,\text{peak}}\,\frac{T/2}{\tau} = 19.3\times\frac{0.5}{100} = 0.0965~\text{V} \\ \text{tilt} &= \frac{T/2}{\tau}\times100 = 0.5\% \end{aligned}\]

(c) Positive clamper: output between \( -0.7~\text{V} \) and \( +19.3~\text{V} \); tilt \( \approx 96.5~\text{mV} \), i.e. \( 0.5\% \).

The \( 0.7~\text{V} \) is why a real clamper never reaches exactly \( 0~\text{V} \): the clamped level always overshoots by one diode drop in the direction the diode conducts.

PROBLEM 06

Design of a Biased Clamper

Problem Statement

Design. A \( 500~\text{Hz} \) sine wave of \( 8~\text{V} \) peak (\( 16~\text{V} \) peak-to-peak) must be shifted so that the output swings between \( +2~\text{V} \) and \( +18~\text{V} \). The following stage presents a load of \( 47~\text{k}\Omega \).

Show that a clamper (not an amplifier) can do this, and find the required capacitor voltage.
Choose the diode orientation and the bias voltage.
Choose \( C \), verify \( \tau \gg T \), and state the diode's PIV.

Solution

\( v_i = 8\sin\omega t~\text{V} \), \( f = 500~\text{Hz} \Rightarrow T = 2~\text{ms} \)
Target output: minimum \( +2~\text{V} \), maximum \( +18~\text{V} \)
\( R = 47~\text{k}\Omega \), Si diode \( V_D = 0.7~\text{V} \)

Step 1 — Feasibility and capacitor voltage

A clamper only translates a waveform; the swing must already be right.

\[\begin{aligned} \text{required swing} &= 18 - 2 = 16~\text{V} \\ \text{available swing} &= 2V_p = 2(8) = 16~\text{V} \;\checkmark \end{aligned}\]

The output is \( v_o = v_i + V_C \). Setting the input's negative peak \( (-8~\text{V}) \) to land on \( +2~\text{V} \):

\[\begin{aligned} V_C &= v_{o,\min} - v_{i,\min} = 2 - (-8) = +10~\text{V} \\ \text{check: } v_{o,\max} &= +8 + 10 = +18~\text{V} \;\checkmark \end{aligned}\]

(a) Feasible — the swing already matches; the capacitor must charge to \( V_C = 10~\text{V} \), positive on the output side.

Step 2 — Diode orientation and bias

Clamping the minimum means the diode must conduct on negative excursions, so it is a positive clamper: connect the diode with its cathode at the output node and its anode to the \( + \) terminal of a bias battery \( V_B \) whose \( - \) terminal is grounded. It then conducts whenever \( v_o < V_B - V_D \) and holds the node at that value.

\[\begin{aligned} v_{o,\min} &= V_B - V_D \\ 2 &= V_B - 0.7 \;\Longrightarrow\; V_B = 2.7~\text{V} \end{aligned}\]

(b) Positive clamper, cathode to the output node, with \( V_B = 2.7~\text{V} \) (a \( 2.7~\text{V} \) reference, e.g. a 2.7 V Zener or a divider).

Step 3 — Capacitor and diode rating

Apply the usual clamper rule \( \tau = RC \ge 10T \) so the stored \( 10~\text{V} \) barely decays between conduction pulses.

\[\begin{aligned} \tau_{\min} &= 10T = 10(2~\text{ms}) = 20~\text{ms} \\ C_{\min} &= \frac{\tau_{\min}}{R} = \frac{20\times10^{-3}}{47\times10^{3}} = 0.426~\mu\text{F} \end{aligned}\]

\[\begin{aligned} \text{choose } C &= 1~\mu\text{F}: \quad \tau = (47\times10^3)(1\times10^{-6}) = 47~\text{ms} = 23.5T \\ \text{tilt} &\approx v_{o,\max}\frac{T/2}{\tau} = 18\times\frac{1}{47} = 0.383~\text{V} \;(2.13\%) \\ \text{PIV} &= v_{o,\max} - (V_B - V_D) = 18 - 2 = 16~\text{V} \end{aligned}\]

(c) \( C = 1~\mu\text{F} \) (\( \ge 0.426~\mu\text{F} \) required), \( \tau = 47~\text{ms} = 23.5T \), tilt \( 2.13\% \), diode PIV \( = 16~\text{V} \) (use a 1N4148).

Design summary: the swing is fixed by the source, the DC position by \( V_B \), and the flatness of the tops by \( RC \). Increasing \( C \) reduces tilt but lengthens the settling time after the signal is applied — about \( 5\tau = 235~\text{ms} \) here.