SCR Ratings, di/dt and dv/dt Protection

The conduction window. With a resistive load the SCR conducts from \(\alpha\) to \(\pi\), so \(V_m = \sqrt2(230) = 325.3\) V and:

The RMS needs the square of the sine, which is where the \(\sin2\alpha\) term comes from:

With \(\alpha = \pi/3\) and \(\sin120^\circ = 0.866\):

Form factor — the ratio that says how far this is from DC:

Compare 1.57 for uncontrolled half-wave and 1.00 for pure DC. Retarding the firing angle makes the waveform peakier, so the RMS falls more slowly than the average and the form factor worsens.

Check both ratings. This is the step that is skipped and should not be:

Both pass, but the RMS is the tighter constraint — and it is the one usually forgotten. A device chosen only on the 3.88 A average, say a 5 A part, would very likely have an RMS rating below 7.29 A and would fail from heating while apparently well within its “current” rating.

On-state dissipation, using the average for the offset and the RMS for the slope:

Convert the surge rating into an energy figure. The \(I_{TSM}\) rating is a half sine over \(T/2 = 10\) ms, and the mean square of a half sine is half its peak squared:

Roughly 1500 A²s, which is how such a device would be catalogued. The point of the \(I^2t\) form is that it is duration-independent for short events: the silicon does not care whether the energy arrives as a big current briefly or a smaller one for longer.

The fault energy, same integral with a much larger peak:

The SCR would be destroyed thirty times over if the fault ran for a full half cycle. And it would — a thyristor cannot turn itself off, so without a fuse the fault persists until the supply zero crossing.

How quickly must the fuse act? Integrate the fault current only up to the clearing time \(t_c\) and set the result to the device rating:

For \(t_c \ll T/2\) the sine may be expanded, giving the simpler form:

Solving the exact integral numerically gives 1.75 ms, so the cubic approximation is good to 2% here. Either way the fuse has less than a fifth of a half cycle.

Why the cube root? Early in the half cycle the fault current is still rising almost linearly, so \(i \propto t\) and \(\int i^2dt \propto t^3\). A consequence worth noticing: to halve the delivered energy you need only cut the clearing time by 21%, so fuse speed pays off very quickly.

The coordination rule. A semiconductor fuse is specified by its own total \(I^2t\) — the melting energy plus the arcing energy — and selection is a single inequality:

So a fuse rated well under 1500 A²s at the prospective fault current. Note what this is not: an ordinary distribution fuse chosen on its RMS current rating will melt in tens of milliseconds and will protect the wiring while the thyristor fails first. Semiconductor fuses are a separate class of device, and their catalogue entry is an \(I^2t\) figure rather than an ampere figure for exactly this reason.

Why the limit exists. A thyristor turns on from a small region near the gate and the conducting area spreads outward at a finite velocity. If the external current rises faster than the plasma spreads, the whole current crowds into a fraction of the die, and the local power density destroys it — a failure that leaves no trace of an over-current in the measured waveform.

The natural rate, set only by the stray inductance:

Eight times the rating. Stray inductance alone will not save the device — and note that a better layout, with less stray inductance, would make this worse.

The required inductance follows directly from the same relation:

So add roughly 3.5 µH in series, giving 4 µH total. In practice this is a small air-cored coil or a saturable reactor — the latter presenting high inductance at low current, when the limit matters, and saturating out of the way once the device has fully turned on.

The energy that inductor now stores at full current:

And that is the sting. Every time the current is interrupted, 5 mJ has to go somewhere. Without a path it appears as \(L\,di/dt\) across whatever opened the circuit — a voltage spike on the device you were trying to protect.

So the \(di/dt\) inductor is never fitted alone. It needs a freewheeling path, or the snubber of Problem 4 to catch its energy, or a saturable core that stores far less at full current. Adding protection to a converter always creates the next problem; the skill is knowing which one.

Why the limit exists. The blocking junction has capacitance. A rapidly rising anode voltage drives a displacement current \(i = C_j\,dv/dt\) into the gate region, and if it is large enough the device latches on with no gate signal at all — a spurious turn-on that in a bridge means a shoot-through.

Size the time constant. With the capacitor initially uncharged, the device voltage recovers exponentially; using the standard design rule based on the rise over one time constant:

The resistor is set by the other constraint. When the SCR fires, the snubber capacitor dumps its charge through \(R\) and the device:

The snubber resistor has two jobs that pull in opposite directions: large enough to limit the discharge current, small enough to let the capacitor charge quickly. Five ohms with a little margin is the compromise.

The capacitance follows:

Now check the loop you have just built. The \(di/dt\) inductor, the snubber capacitor and the snubber resistor form a series RLC circuit, and nothing so far has guaranteed it is well behaved:

Underdamped but comfortably so — the usual target band is 0.5 to 1.0. Below about 0.3 the circuit rings for many cycles; above 1.0 the capacitor charges too slowly and the \(dv/dt\) protection is lost.

The peak voltage, from the standard second-order overshoot:

An 8% overshoot, which the device's voltage rating must cover on top of the 400 V supply. Had \(\zeta\) come out at 0.2 the overshoot would have been 53% — which is how a snubber intended to protect a thyristor ends up over-volting it.

The running cost. The capacitor is charged and discharged once per operation:

Modest, because a line-commutated thyristor switches only 100 times a second. The same snubber at 20 kHz would burn 400 W — which is the reason RC snubbers are standard practice on thyristors and rare on hard-switched MOSFETs.

What latching means. The gate starts the regenerative action, but until the anode current is high enough for the internal feedback to be self-sustaining, removing the gate signal turns the device back off. That threshold is the latching current, and it is typically two to three times the holding current.

The load decides how quickly it is reached. The inductance prevents the current from appearing instantly:

With \(L = 0.5\) H, \(\tau = 25\) ms and the same fractional rise takes proportionally longer:

Because the latching current is a small fraction of the final current, the exponential is still in its linear region, so the required time is simply proportional to \(\tau\) — and therefore to \(L\).

The resistive case, for contrast. With no inductance the current reaches 5 A essentially instantly, so latching is achieved within the device's own turn-on time — a few microseconds. A short gate pulse suffices.

This is why the same SCR that fires reliably on a lamp dimmer fails to fire on a motor or a transformer: the load, not the device, sets the pulse requirement.

Why a pulse train. A single 500 µs DC gate pulse is possible but undesirable, for three reasons:

A typical arrangement is a 10 kHz carrier gated on for the required window — here at least 202 µs, so three or more pulses. Each pulse re-triggers the device, and once the anode current passes \(I_L\) the train can stop.

The holding current is the other end of the same story. Conduction ceases when the anode current falls below \(I_H = 60\) mA:

Getting the device latched is harder than keeping it latched — which is exactly what you would expect of a regenerative process that has to start itself.

Output voltage. For a full converter with continuous inductive load current, the average output is the uncontrolled value scaled by the cosine of the firing angle:

Thyristor currents. Each device conducts the constant 40 A for half of every cycle, exactly as the bridge diodes did in Set 3:

Note that neither depends on \(\alpha\) — the firing angle shifts when each device conducts, not how long. That is a feature of the inductive load; with a resistive load, as in Problem 1, both currents fall as \(\alpha\) increases.

Conduction loss and efficiency:

Voltage rating. Each device blocks the full supply peak, and line transients demand the usual doubling:

The \(di/dt\) check — and this is where the firing angle matters. At the instant of firing, the instantaneous supply voltage is applied across the loop inductance:

Worth noting how this scales: at \(\alpha = 90^\circ\) the applied voltage would be the full 325 V and the requirement would double to 3.25 µH. The inductor must be sized for the largest firing angle the converter will ever use, not the operating point in the specification.

Fault survivability. A fault at fifteen times rated current gives a peak of 600 A:

The device survives one half cycle of this fault with 27% margin — but only one, and only if the fault is cleared before the next. A semiconductor fuse rated below 2450 A²s is still mandatory, exactly as Problem 2 argued.

The selection, assembled:

Four of five constraints were satisfied by the obvious device choice; the fifth needed a component added to the circuit. That is the normal outcome, and it is why the check is done as a table rather than as a single “40 A, 800 V” conclusion.