Gate Triggering, Series and Parallel Operation

Peak power from average power. The gate is driven in pulses, so the average limit is spread over the duty ratio:

Pulsing is what makes a hard gate drive possible at all: 5 W peak from a device that can only average half a watt.

Minimum \(R_s\) — the load line must not cross the power hyperbola. Substituting the load line into \(V_gI_g = P_{gm}\):

The line just touches the hyperbola when the discriminant vanishes:

At tangency \(I_g = E_s/2R_s = 0.667\) A and \(V_g = 7.5\) V — exactly 5 W. Any smaller resistance and the load line cuts through the forbidden region.

Maximum \(R_s\) — the drive must still reach the trigger point:

A wide window, which is fortunate, because \(V_{GT}\) and \(I_{GT}\) are worst-case cold values and the real device fires well inside them.

The operating point at \(R_s = 50\ \Omega\). Solve the load line against the gate characteristic simultaneously:

Check all four constraints:

Comfortably inside on every count. Note that overdriving the gate — here by 2.3 times — is deliberate and desirable: a hard gate drive turns the device on faster, spreads the conducting plasma more quickly, and therefore improves the \(di/dt\) capability of Set 4.

The firing threshold. The UJT conducts when its emitter exceeds the fraction \(\eta\) of the interbase voltage, plus the diode drop:

Charging time to that threshold. The capacitor charges exponentially towards \(V_{BB}\):

Notice that \(V_{BB}\) cancels: the period depends on \(\eta\) but not on the supply voltage, which is exactly the property that makes the UJT a usable timing element.

Solve for \(R\) with \(T = 1\) ms:

Convenient coincidence worth remembering: for \(\eta \approx 0.63\) the logarithm is almost exactly 1, so \(T \approx RC\).

The resistor is bounded on both sides, and this is the part that gets missed. Too large and the capacitor never reaches the peak point:

Too small and, after firing, \(R\) keeps supplying more than the valley current, so the UJT never turns off and the oscillator latches:

Check the design against those bounds:

It passes, but only by 9% at the lower end. Component tolerance or a warm UJT could push it below \(R_{min}\), at which point the circuit stops oscillating altogether. The fix is to raise \(R\) and lower \(C\) proportionally — say 20 kΩ and 0.05 µF for the same 1 ms, giving an order of magnitude of margin.

The base resistors follow the standard design relations, with \(R_2\) providing temperature compensation and \(R_1\) developing the output pulse:

The pulse appears across \(R_1\) as the capacitor dumps into base 1, giving a short, sharp trigger of the kind Problem 1 assumed.

Number of devices. Ideal sharing would need \(15000/2000 = 7.5\), so eight, and the fractional device is exactly the margin that unequal sharing consumes:

Why they do not share. In series every device carries the same current. A device with lower leakage needs more reverse voltage to pass that current, so it takes the larger share — and being closest to breakdown, it is the one that fails first. Worst case, one device sits at its full \(V_{Dm}\) while the other seven divide the remainder.

Static equalizing resistors. Putting \(R\) across each device gives the leakage mismatch somewhere to go. In the worst case the standard result is:

The numerator is the total spare blocking voltage the string has — 1 kV — and the denominator is the mismatch current it must absorb. More devices, or better matched ones, allow a larger and therefore cooler resistor.

What the resistors cost:

A startling figure until it is put in context: a 15 kV string carrying, say, 500 A handles 7.5 MW, so the sharing network costs 0.03% of throughput. In HVDC valve design these resistors are real, large and water-cooled, and they are simply part of the price of stacking devices.

Dynamic sharing. The resistors handle steady leakage, but during turn-off the devices recover at different rates, and the one that recovers first is suddenly asked to block everything. A capacitor across each device holds the voltage down while that happens:

Same spare-voltage denominator, with recovery charge in place of leakage current — because the transient mismatch is a charge, not a current.

The two networks together. In practice the capacitor is fitted in series with a small resistor, so that it also damps the turn-on discharge:

Neither substitutes for the other. A capacitor passes no steady current so it cannot correct leakage; a resistor of 14 kΩ is far too slow to act during a recovery lasting microseconds.

Parallel means equal voltage. Setting the three characteristics equal pairwise turns the offset differences into current differences:

Add the constraint that they carry 300 A between them:

A 200 mV spread in forward voltage produces a 40 A spread in current, and \(T_1\) is 10 A over its 110 A rating while \(T_3\) loafs at 80.

What the group can really carry. The limit is reached when the hardest-worked device hits its rating, i.e. \(I_1 = 110\) A:

Nearly a fifth of the installed silicon is unusable. And the situation is worse than static: \(T_1\) runs hottest, a thyristor's forward drop falls with temperature, so it takes an even larger share — a positive feedback that has no equivalent in paralleled MOSFETs, whose \(R_{DS(on)}\) rises with temperature and therefore self-balances.

Force the sharing. Adding \(R_s = 10\ \text{m}\Omega\) to each branch simply steepens every characteristic, so the same voltage offset produces less current imbalance:

Now the full 300 A fits:

301 W buys back 30 A of capacity. Whether that is a good trade depends on what a fourth thyristor costs — and in practice the sharing element is usually a small inductor or a few centimetres of deliberately routed busbar rather than a resistor, which achieves the same slope during transients without the steady dissipation.

A pulse transformer saturates on volt-seconds, not volts. From Faraday's law integrated over the pulse:

Compare with what is applied:

Exactly at the limit — which means saturating. Once the core saturates its inductance collapses, the magnetizing current runs away, and the primary looks like a short circuit to the driver. The gate pulse simply disappears part-way through, and the thyristor may or may not have latched by then.

Add margin by adding turns. The ratio stays 1:1 — only the absolute turns count matters for saturation:

A factor of two is the usual target, because the core must also cope with a hot ambient (lower \(B_{sat}\)) and with incomplete reset between pulses.

Magnetizing current at the end of the pulse, from the magnetizing inductance:

Against a 200 mA gate current — 15%, which the driver must supply on top of the useful load and which contributes nothing to firing the thyristor.

Droop. Because the magnetizing current grows through the pulse, the output amplitude sags. With the effective loop resistance \(R = 15/0.2 = 75\ \Omega\):

So a pulse that starts at 3 V ends at about 2.55 V. That still clears the 2.5 V \(V_{GT}\) of Problem 1, but barely — and it is the trailing edge that matters, because that is when the load current is closest to the latching threshold. Under 20% droop is the usual rule.

Energy accounting:

Negligible in power terms — the pulse transformer exists for isolation, not efficiency. The magnetizing energy is not lost as such, but it must be reset out of the core between pulses through a reset winding or a clamp, or the flux walks up cycle by cycle until it saturates anyway.

Size the matrix. Ideal sharing would need exactly three in each direction, which leaves no margin at all for the mismatch that Problems 3 and 4 quantified:

A bare 3×3 would give 100% string efficiency, which sounds ideal and is in fact a statement that every device operates at exactly its rating with zero tolerance for spread — unbuildable.

The three efficiencies:

And note the structure: \(0.75\times0.75 = 0.5625\). The two derating factors multiply, so a matrix wastes silicon far faster than either dimension alone. Sixteen devices are installed to do the work of nine.

Conduction loss. Each device carries a quarter of the arm current:

The arm's total forward drop is four devices in series, and the whole 600 A passes through it:

Arm efficiency:

4.68 kW is a great deal of heat in absolute terms — it needs serious cooling — and simultaneously a rounding error against the throughput. Both statements matter, and confusing which one is relevant to a given question is a common trap.

Static sharing for the series dimension:

Compare with the 14.3 kΩ and 246 W of Problem 3. The extra device of margin here left 2 kV of spare blocking voltage instead of 1 kV, which permitted a resistor four times larger and cut the dissipation by a factor of seven. Margin is not only insurance — it pays for itself in auxiliary loss.

The complete picture:

The sharing network adds 12% to the arm's losses — a real cost, and the reason matched device batches are worth paying for, but not one that threatens the 99.85% efficiency that makes line-commutated converters attractive at these power levels in the first place.