Boost Converter Design and Ripple

Duty ratio and inductor current:

Eight amps in the inductor to deliver two to the load — four times the output current. Every conduction loss in the converter is computed from 8 A, not 2, and that ratio is \(1/(1-D)\), so it worsens rapidly as the gain rises.

The inductance. During the on-time the full input voltage is across the inductor:

Now the capacitor, and here the boost differs completely. While the switch is on, the diode is reverse biased and the capacitor alone supplies the load — at the full \(I_o\), for the whole on-time:

Compare the buck of Set 18, which needed 22.5 µF for a 50 mV ripple at 5 A. Scaled to the same specification, a boost needs roughly fifteen times the capacitance — because its capacitor carries the load current rather than the inductor's ripple.

The ESR contribution is worse still. The capacitor current jumps between \(-I_o\) and \(I_{L,pk}-I_o\) at every switching edge:

Hence with a modest 20 mΩ of ESR:

Which alone exceeds the entire 200 mV budget, before the capacitance contributes anything. In a boost converter the ESR requirement essentially always dominates, and it is set by the peak inductor current — a quantity four times the load current here.

What that forces. To meet 200 mV the ESR must come down:

So the design ends up with 300 µF at 14 mΩ — several ceramics in parallel, or a low-ESR polymer part. The naive 75 µF answer was out by a factor of four.

Compare the two topologies at a glance:

The third and fourth rows are duals. A buck has a smooth output and a pulsed input; a boost has a smooth input and a pulsed output. That is why a boost makes an excellent power-factor corrector — its input current can be shaped — and a poor supply for a sensitive load without extra filtering.

The voltage stresses are both the output voltage. When the switch is off it stands off \(V_o\); when it is on, the diode does:

Note that raising the output raises the device blocking requirement with it — unlike the buck, where both devices see only the input. A high-gain boost needs high-voltage devices, whose \(R_{DS(on)}\) is worse, which is a second penalty on top of the current ratio.

The currents follow the conduction intervals:

The capacitor's RMS current is 1.7 times the load current — against 0.26 times for the buck of Set 18. That is what sets its physical size and its lifetime.

The loss budget:

Total and efficiency:

Read the difference. The boost delivers 60% more power and dissipates twice as much, and the shift is concentrated in the two current-squared terms:

The inductor carries 8 A instead of 5, and the loss goes as the square. Every \(I^2R\) term in a boost is inflated by \(1/(1-D)^2\) relative to the load current — a factor of 16 here.

Where a synchronous rectifier would help. Replacing the diode with a MOSFET of the same 15 mΩ:

A gain of 0.8 percentage points — useful, but only half what the same change bought in a buck, because the diode was a smaller share to begin with. In a boost the inductor is the thing to improve.

Derive the real conversion ratio. Applying volt-second balance with the resistance included, and charge balance at the output, gives:

The correction factor is the ratio of the load resistance reflected through the converter, \(R(1-D)^2\), to the series resistance. As \(D\to1\) the reflected load collapses and the series resistance takes everything.

Evaluate across the range:

The gain rises, peaks and then falls. Past \(D = 0.935\) increasing the duty ratio reduces the output — a feedback loop that does not know this will chase the duty ratio to 1 and collapse the output entirely.

Find the peak analytically. Writing \(x = 1-D\) and \(k = r/R\):

The efficiency at that point is remarkable:

Exactly one half, independent of \(r\), \(R\) and everything else. At the duty ratio of maximum gain, precisely half the input power is dissipated in the series resistance — the classic maximum-power-transfer condition, because the reflected load resistance \(R(1-D)^2\) has fallen to equal \(r\).

What this means in practice. The maximum useful gain is well below the peak:

So a single boost stage is practically limited to a gain of about four or five. Beyond that the answer is a transformer — the flyback and forward converters of Set 22 — whose turns ratio provides gain at no efficiency cost at all.

Why the buck has no such limit. Its equivalent expression is:

A buck's series resistance costs a fixed percentage whatever the duty ratio, because the inductor current is always \(I_o\). A boost's inductor current diverges as \(D\to1\), and the loss goes as its square. That asymmetry is the whole result.

What a PFC boost actually does. Its input is the rectified sine, not a DC source, so the duty ratio must vary continuously through every half cycle to make the input current follow the input voltage:

And \(D \to 1\) at each zero crossing, where the input is momentarily zero. The boost topology is the natural choice precisely because the output must always exceed the input, and 400 V clears the 325 V peak with margin.

The input current, for unity power factor:

Compare Set 10's capacitor-input rectifier at the same power: it drew 9.77 A RMS with a 71.6 A peak. The PFC stage draws less than half the RMS and a ninth of the peak.

The inductor, sized at the line peak where the ripple is worst:

A substantial choke carrying 6 A peak — but note that its ripple current is at 65 kHz, so it is a small ferrite component rather than the 110 mH iron-cored monster the choke-input filter of Set 10 required.

The bulk capacitor is sized by hold-up, not by ripple. The requirement is to keep the downstream converter running for 20 ms after the mains fails, allowing the bus to sag from 400 V to a minimum of 300 V:

This is why PFC bus capacitors are large electrolytics rather than ceramics: the requirement is energy storage, and only electrolytics offer it economically at 400 V.

Check the second-harmonic ripple. A single-phase input delivers power at \(P(1-\cos2\omega t)\) while the load draws a constant \(P\), so the capacitor absorbs the difference at 100 Hz:

Unavoidable in any single-phase PFC — it is a consequence of instantaneous power pulsating at twice line frequency, not of any design choice. The downstream converter must reject it, and the PFC's own control loop must be slow enough (under about 20 Hz) not to try to correct it, or it would distort the input current in the attempt.

What the stage achieves:

One switching stage converts the worst input current in this book into very nearly the best. And because the boost's input current is continuous by topology, no additional input filter is needed beyond a small high-frequency one.

Test the mode. The boost has its own critical value:

Only 11% below the boundary — which is exactly the situation in which using the CCM formula feels safe and is not.

The DCM conversion ratio for a boost:

With \(M = 4\) fixed by the regulator, solve for \(D\):

Against 0.75 in CCM — a reduction of 6%. Note the direction: as with the buck of Set 18, DCM requires less duty ratio for the same output, because the missing third interval removes part of the volt-second demand.

Verify by reconstructing the waveform:

Matching \(P/V_{in} = 24/12 = 2\) A exactly. The idle interval is \(1-0.707-0.236 = 0.057\) — under 6% of the period, consistent with being only just discontinuous.

Contrast the two mode criteria:

The boost's critical value is five to ten times smaller, so a boost stays in continuous conduction with far less inductance than a buck at the same load. Its worst case is at \(D = 1/3\), where \(K_{crit} = 4/27 = 0.148\) — and at high duty ratios it is very hard to make a boost discontinuous at all.

Why DCM is sometimes chosen deliberately. Two of its properties are advantages:

And (ii) the right-half-plane zero of Problem 6 disappears entirely, so the control loop can be fast. Low-power boost converters and small PFC stages often run permanently in DCM or at the boundary for exactly these reasons — paying for it in peak current and higher RMS losses.

Where the right-half-plane zero comes from. Suppose the loop demands more output and increases the duty ratio. The immediate effect is to keep the diode off for longer, so less charge reaches the output:

Only later, once the inductor current has had time to build, does the output rise as intended. So the converter's initial response to a correction is in the wrong direction — which is precisely what a right-half-plane zero describes.

Compute it:

What a right-half-plane zero does to a loop. It adds gain like a zero but subtracts phase like a pole:

The worst of both. It raises the gain, making it harder to bring the loop down through unity, while simultaneously removing the phase margin needed to do so. There is no compensator that cancels it — cancelling a right-half-plane zero would require a right-half-plane pole, which is unstable.

The bandwidth limit. The only remedy is to cross over well below it:

Against a buck, which has no right-half-plane zero and can be compensated to cross over at \(f_s/10 = 10\) kHz. The boost's loop is seven times slower for the same switching frequency.

And it gets worse with gain:

The \((1-D)^2\) dependence means a high-gain boost is almost uncontrollable dynamically. This is the same \((1-D)^2\) that appeared in the gain ceiling of Problem 3 — the reflected load resistance — and it limits the loop for the same underlying reason.

Practical consequences and remedies:

Current-mode control is the standard answer. It closes a fast inner loop on the inductor current, which has no right-half-plane zero, and a slow outer loop on the voltage — so the converter responds quickly to load changes even though the voltage loop is slow. Set 24 works that through.