Buck Converter Design and Ripple

The duty ratio range. The output is regulated, so the duty ratio must move to track the input:

A 1.67:1 input range maps onto a 1.67:1 duty range. Worth checking against the controller's limits — and note that a converter needing \(D > 0.9\) or \(D < 0.05\) is usually asking for trouble with minimum on-times.

The ripple specification at nominal input:

Thirty per cent is the usual starting point, and the reason is a compromise: less ripple means a bigger inductor, more ripple means larger RMS currents and a worse critical current. Anything from 20% to 40% is defensible.

The inductance, from the volt-seconds applied during the on-time:

Now check the extremes. The ripple is \(\left(V_{in}-V_o\right)D/Lf_s\), and substituting \(D = V_o/V_{in}\) gives:

The worst case is at high input, which is the opposite of the intuition that a lower input is harder. A higher input means a shorter on-time but a larger voltage across the inductor, and the voltage wins.

Why the ripple rises with input voltage. Written as \(V_o(1-D)/Lf_s\), the output voltage is fixed and only \((1-D)\) varies:

The ripple is set entirely by the off-interval, during which the inductor sees a fixed \(-V_o\). A longer off-interval means more volt-seconds and more ripple. This is also why the buck's ripple approaches a maximum of \(V_o/Lf_s\) as \(V_{in}\to\infty\).

What the choice costs and buys:

The inductor must not saturate at 5.9 A — and preferably not at the current limit either, which will be set well above that. The peak, not the average, sizes the core; the RMS (essentially 5 A) sizes the winding.

The capacitive ripple. The capacitor receives the inductor's ripple current — the DC component all goes to the load — and integrating that triangle over the half period when it is positive gives:

The factor of eight is worth deriving once: half the ripple amplitude, over half the period, times the half for the triangle's area. It is specific to the buck, whose capacitor current is triangular.

Size an ideal capacitor at the worst-case ripple of 1.8 A:

Which looks easy — a 22 µF ceramic would do. But the ideal capacitor does not exist.

The ESR ripple is entirely separate. The ripple current flowing through the equivalent series resistance produces a voltage directly:

For the whole 50 mV budget to be ESR alone:

Note what this does not depend on: the capacitance, or the frequency. A large electrolytic with 200 mΩ of ESR would give 360 mV of ripple no matter how many microfarads it had.

With a real 20 mΩ capacitor, the two contributions share the budget:

Nearly four times the ideal figure, and the capacitance is doing the easy part. Adding the two contributions arithmetically is conservative — they peak at slightly different instants, so the true total is a little lower — but the margin is worth having.

Which mechanism dominates? Compare the two as the frequency changes:

The capacitive term falls as \(1/f_s\) while the ESR term does not fall at all. So in any modern converter switching above a few hundred kilohertz, ESR is the whole problem — which is why ceramic capacitors, with milliohms of ESR, displaced electrolytics in that role.

The capacitor's own current rating. It carries the inductor's ripple, which is triangular with zero mean:

Modest — and a striking contrast with the capacitor-input rectifier of Set 10, whose reservoir capacitor carried 9.6 A for a 2 A load. A buck's output capacitor sees only the ripple, never the load current, because the inductor supplies the DC.

The stresses, from the conduction intervals:

Note the last row. The input capacitor carries far more RMS current than the output one — 2.5 A against 0.52 A — because the input current is a square pulse while the output current is smooth. This is the reverse of most people's expectation and it is why input capacitors on a buck are often the larger part.

The loss budget, term by term:

Total and efficiency:

The diode alone is more than half the loss, and it is the one component that was chosen for being cheap. A 0.4 V Schottky carrying 2.5 A average simply cannot do better than one watt.

Replace it with a synchronous rectifier — a second MOSFET of the same \(10\ \text{m}\Omega\), turned on during the off-interval:

The loss nearly halves and 0.875 W of heat disappears, for the cost of one MOSFET and the dead-time logic of Set 7. Compare Set 2, Problem 2: with 0.4 V and 10 mΩ the crossover current is 40 A, so at 5 A the MOSFET wins comfortably.

Where the loss now sits:

With the diode gone, the inductor's DCR becomes the largest single term. Improving the converter further means a better core and thicker wire — or a lower frequency, which trades against the inductor's size. This is the point at which further optimisation stops being about semiconductors.

Each phase carries half the load:

The per-phase ripple is unchanged, because the inductor and the voltages are unchanged — but it is now a larger fraction of the phase current, 60% instead of 30%.

Conduction loss halves. Two MOSFETs each carry half the current:

Against 0.125 W for the single phase — exactly half. The reason is \(2\times(I/2)^2R = I^2R/2\): splitting a current between two devices halves the total \(I^2R\) loss even though the total silicon area is only doubled.

Now the striking part — the output ripple. The two phase currents are triangles 180° apart. At \(D = 0.5\), one is rising at exactly the rate the other is falling:

Complete cancellation. The output capacitor sees no ripple current at all at \(D = 0.5\) — not reduced, eliminated. This happens whenever \(D = k/N\) for integer \(k\), so a two-phase converter cancels perfectly at 0.5 and an \(N\)-phase one at every \(k/N\).

Away from the sweet spot the cancellation is partial but still substantial:

And the ripple that remains is at \(2f_s = 400\) kHz, so the capacitor filters it twice as easily. Both effects compound.

The input capacitor benefits too, and this is often the bigger prize:

The input current becomes continuous rather than a square pulse, because the two phases draw alternately. Since Problem 3 found the input capacitor carrying five times the output capacitor's current, removing that is worth more than the output ripple cancellation.

What interleaving costs:

The last benefit matters more than it sounds. Two devices each dissipating half as much have a far easier thermal path than one dissipating everything — and Set 8 showed that the heatsink is three-quarters of the temperature rise.

Test the mode first. With the output still regulated at 12 V, the equivalent load resistance is:

Consistent with the critical current found in Problem 1: at 30 V the ripple is 1.8 A, so \(I_{crit} = 0.9\) A and a 0.5 A load is well below it.

In DCM the output ratio is load-dependent, so the duty ratio is no longer \(V_o/V_{in}\):

Here \(M = 12/30 = 0.4\) is fixed by the regulator, and \(D\) is the unknown. Rearranging:

Compare with what CCM would demand:

The controller must reduce the duty ratio by 25% to hold the same output. If it did not — if it were an open-loop converter set to 0.400 — the output would rise well above 12 V, exactly as the DCM buck of Set 1 rose from 6 to 14.3 V.

Verify by reconstructing the waveform. The peak inductor current:

Exact agreement with the 0.5 A demanded. Note also that the third interval is \(1-0.298-0.447 = 0.255\) — a quarter of every cycle with no current at all.

What this does to the control loop. The two modes have completely different transfer functions:

A compensator designed for the CCM double pole is over-damped and slow in DCM; one designed for DCM is unstable in CCM. A converter that crosses the boundary in normal service must be compensated for the worst of both — which is why many controllers force a minimum load or use synchronous rectification to stay in CCM at all times.

How synchronous rectification changes this. A MOSFET conducts in both directions, so the inductor current can go negative:

The converter simply circulates current backwards during part of each cycle. That keeps the transfer function fixed at all loads — at the cost of conducting current that does no work, which is why efficient designs switch to a diode-emulation mode at light load and accept the DCM behaviour.

Sort the terms by how they scale, which is the whole method — the Set 2 discipline applied to a complete design:

Three different scalings, so three different regimes. The diode is linear rather than quadratic because it holds a roughly fixed voltage — Set 2's distinction between junction and channel devices.

Full load, 5 A:

Half load, 2.5 A. Quadratic terms fall by four, linear terms by two, the constant does not move:

Efficiency has risen. The quadratic terms collapsed faster than the output did, so the loss fraction improved. That is the mechanism behind the peak that every efficiency curve has.

Ten per cent load, 0.5 A:

Falling again — because at 0.5 A the fixed 0.1 W is 42% of the total loss, and it does not shrink at all. Below this the curve collapses steeply toward zero.

The curve, and where each regime lies:

The peak sits near half load, which is typical and is why supplies are often specified for best efficiency at 50% rather than 100%. It is also why a converter oversized for its actual load runs worse, not better — it operates permanently in the fixed-loss regime.

Where the peak sits, in general. The efficiency is maximised when the load-dependent quadratic losses equal the fixed losses:

Here \(k_2 = 0.020\) W/A² from the two quadratic terms, giving \(I_{o,opt} = \sqrt{0.1/0.02} = 2.24\) A — close to the 2.5 A observed. The same condition appeared in Set 2, Problem 6 for the optimum frequency: an optimum occurs where a rising cost meets a falling one.

How to improve each regime:

The light-load remedy is the same as Set 2, Problem 4: fixed losses are proportional to switching frequency, so the way to reduce them is to switch less often. A burst-mode controller delivers a few full-current cycles and then sleeps, cutting the average \(f_s\) by orders of magnitude.