As shown in the circuit, the initial voltage across the capacitor is 10 V with the switch open. The switch is then closed at \( t = 0 \). The total energy dissipated in the ideal Zener diode (\( V_Z = 5\,V \)) after the switch is closed in mJ, rounded to three decimal places, is ___.
GATE 2024 Analog Electronics Q1 Zener circuit diagram
Solution
[Image of RC circuit discharge graph]
Once the switch closes the capacitor discharges through the 10 k\(\Omega\) resistor and the Zener, which holds a constant 5 V while current flows. The capacitor voltage therefore relaxes towards 5 V, not towards zero, with \( RC = 0.1\,s \):
Conduction continues until the current dies away, by which time the capacitor has fallen from 10 V to 5 V. The charge delivered through the Zener is therefore
In the circuit shown, the \( n:1 \) step-down transformer and diodes are ideal (no forward drop). If the input voltage is \( V_s(t) = 10\sin t \) and the average load voltage \( V_L(t) \) is \( \frac{5}{\pi}\,V \), the value of \( n \) is ___.
4
8
12
16
GATE 2024 Analog Electronics Q2 diode circuit diagram
Solution
The centre-tapped secondary with \(D_1\) and \(D_2\) gives a full-wave rectified load voltage, so with \(V_M\) the peak of each half-secondary:
In the circuit shown below, transistors M1 and M2 are in saturation. Their small-signal transconductances are \( g_{m1} \) and \( g_{m2} \) respectively. Neglect body effect, channel-length modulation, and capacitances. Assume C1 is AC short. The exact magnitude of small-signal voltage gain \( \frac{v_{out}}{v_{in}} \) is ___.
\( g_{m2} R_D \)
\( \frac{g_{m2} R_D R_B}{1+g_{m1} R_S + R_B} \)
\( \frac{g_{m2} R_D R_B}{1+g_{m1} R_S + R_B} \)
\( g_{m2} R_D \frac{1}{1+g_{m1} R_S + R_B} \)
GATE 2024 Analog Electronics Q3 transistor circuit diagram
Solution
From small-signal model:
Equation
\[v_o = g_{m2} v_{gs2} R_D\]
Gate node gives:
Equation
\[v_{gs2} = v \frac{R_B}{1+g_{m1} R_S + R_B}\]
where \( v = v_{in} \) (since \( C_1 \) is AC short).
For the circuit shown, long-channel NMOS is biased in saturation with small signal transconductance \( g_m \). Neglect body effect, channel-length modulation, and intrinsic capacitances. The small-signal input impedance \( Z_{in} \) is ___.
\( g_m C_1 C_L \frac{2}{1/jC_1 + 1/jC_L} \)
\( g_m C_1 C_L \frac{2}{1/jC_1 + 1/jC_L} \)
\( \frac{1}{jC_1 + 1/jC_L} \)
\( g_m C_1 C_L \frac{2}{1/jC_1 jC_L} \)
GATE 2024 Analog Electronics Q4 NMOS circuit diagram
Solution
The drain sits at \( V_{DD} \), a small-signal ground, so the device is a source follower. Let \( v_i \) be the gate voltage and \( v_s \) the source voltage; the only path for input current is \( C_1 \), which bridges gate and source.
KCL at the source node, with \( v_{gs} = v_i - v_s \):
For the closed-loop amplifier circuit, open-loop small-signal gain \( A_{OL} = 40 \). All transistors in saturation and current source is ideal. Neglect body effect, channel-length modulation, and capacitances. The closed-loop small-signal gain \( \frac{v_{out}}{v_{in}} \), rounded to three decimal places, is ___.
0.976
1
1.025
0.488
GATE 2024 Analog Electronics Q5 transistor circuit diagram
In the op-amp circuit below, if the circuit is to show sustained oscillations, the respective values of \( R_1 \) and the frequency of oscillation are ___ and ___.
\( 29R \) and \( \frac{1}{2\pi\sqrt{6}RC} \)
\( 2R \) and \( \frac{1}{2\pi RC} \)
\( 29R \) and \( \frac{1}{2\pi RC} \)
\( 2R \) and \( \frac{1}{2\pi\sqrt{6}RC} \)
GATE 2024 Analog Electronics Q6 op-amp circuit diagram
Solution
The feedback network is a series \(C\) with shunt \(R\) followed by a series \(R\) with shunt \(C\). Writing \(x = \omega RC\), nodal analysis gives
The magnitude condition \(|A\beta| = 1\) then requires a non-inverting gain of 3:
Equation
\[1 + \frac{R_1}{R} = 3 \implies R_1 = 2R\]
So the correct values are \( R_1 = 2R \) and \( f_0 = \frac{1}{2\pi RC} \).
B
Final Answer
Correct option: B.
Question 07
Question 7
Two ideal op-amps saturate at 10 V. Initial inductor current 0 A. Input \( V_i(t) \) is a triangle wave (2V peak, period 8s). Which statement is true?
\( V_{01} \) delayed by 2s relative to Vi, \( V_{02} \) is triangular waveform.
\( V_{01} \) not delayed relative to Vi, \( V_{02} \) is trapezoidal waveform.
\( V_{01} \) not delayed relative to Vi, \( V_{02} \) is triangular waveform.
\( V_{01} \) delayed by 1s relative to Vi, \( V_{02} \) is trapezoidal waveform.
GATE 2024 Analog Electronics Q7 op-amp circuit diagram
Solution
Op-amp A1 is a non-inverting Schmitt trigger: the inverting input is grounded, while the non-inverting input is fed by \( V_i \) through 10 k\(\Omega\) and by \( V_{01} \) through the 100 k\(\Omega\) feedback resistor. Switching occurs when that node reaches 0 V:
With \( V_{01} = \mp 10\,\text{V} \) the trip points are \( V_{UT} = +1\,\text{V} \) and \( V_{LT} = -1\,\text{V} \).
The triangle swings \( \pm 2 \) V over half a period, so its slope is \( 4\,\text{V} / 4 = 1 \) V per second. Starting from a zero crossing, \( V_i \) therefore takes 1s to reach either trip point.
So \( V_{01} \) (a square wave) switches 1s after the corresponding zero crossing of \( V_i \): it is delayed by 1s.
Op-amp A2 (integrator): saturates quickly, resulting in combination of ramp and flat sections; \( V_{02} \) is a trapezoidal waveform.