Solved GATE Paper

GATE 2024 Analog Electronics Questions and Solutions

Instructor: Prof. Mithun Mondal Institution: BITS Pilani Subject: Analog Electronics
Question 01

Question 1

As shown in the circuit, the initial voltage across the capacitor is 10 V with the switch open. The switch is then closed at \( t = 0 \). The total energy dissipated in the ideal Zener diode (\( V_Z = 5\,V \)) after the switch is closed in mJ, rounded to three decimal places, is ___.

GATE 2024 Analog Electronics Q1 Zener circuit diagram
GATE 2024 Analog Electronics Q1 Zener circuit diagram

Solution

[Image of RC circuit discharge graph]

Once the switch closes the capacitor discharges through the 10 k\(\Omega\) resistor and the Zener, which holds a constant 5 V while current flows. The capacitor voltage therefore relaxes towards 5 V, not towards zero, with \( RC = 0.1\,s \):

Equation
\[V_C(t) = 5 + 5\,e^{-t/RC}, \qquad i(t) = \frac{V_C(t)-5}{10\,k} = 0.5\,e^{-t/RC}\,mA\]

Conduction continues until the current dies away, by which time the capacitor has fallen from 10 V to 5 V. The charge delivered through the Zener is therefore

Equation
\[Q = \int_0^{\infty} i(t)\,dt = C\,\Delta V_C = 10\,\mu F \times 5\,V = 50\,\mu C\]

The Zener holds 5 V throughout, so

Equation
\[W = V_Z\,Q = 5 \times 50\,\mu C = 250\,\mu J = 0.250\,mJ\]
Question 02

Question 2

In the circuit shown, the \( n:1 \) step-down transformer and diodes are ideal (no forward drop). If the input voltage is \( V_s(t) = 10\sin t \) and the average load voltage \( V_L(t) \) is \( \frac{5}{\pi}\,V \), the value of \( n \) is ___.

  1. 4
  2. 8
  3. 12
  4. 16
GATE 2024 Analog Electronics Q2 diode circuit diagram
GATE 2024 Analog Electronics Q2 diode circuit diagram

Solution

The centre-tapped secondary with \(D_1\) and \(D_2\) gives a full-wave rectified load voltage, so with \(V_M\) the peak of each half-secondary:

Equation
\[V_{DC} = \frac{2V_M}{\pi} = \frac{5}{\pi} \implies V_M = 2.5\,V\]

The primary peak is 10 V, so the turns ratio follows directly:

Equation
\[n = \frac{V_{p,peak}}{V_M} = \frac{10}{2.5} = 4\]
A
Final Answer
Correct option: A.
Question 03

Question 3

In the circuit shown below, transistors M1 and M2 are in saturation. Their small-signal transconductances are \( g_{m1} \) and \( g_{m2} \) respectively. Neglect body effect, channel-length modulation, and capacitances. Assume C1 is AC short. The exact magnitude of small-signal voltage gain \( \frac{v_{out}}{v_{in}} \) is ___.

  1. \( g_{m2} R_D \)
  2. \( \frac{g_{m2} R_D R_B}{1+g_{m1} R_S + R_B} \)
  3. \( \frac{g_{m2} R_D R_B}{1+g_{m1} R_S + R_B} \)
  4. \( g_{m2} R_D \frac{1}{1+g_{m1} R_S + R_B} \)
GATE 2024 Analog Electronics Q3 transistor circuit diagram
GATE 2024 Analog Electronics Q3 transistor circuit diagram

Solution

From small-signal model:

Equation
\[v_o = g_{m2} v_{gs2} R_D\]

Gate node gives:

Equation
\[v_{gs2} = v \frac{R_B}{1+g_{m1} R_S + R_B}\]

where \( v = v_{in} \) (since \( C_1 \) is AC short).

Therefore,

Equation
\[\frac{v_o}{v_{in}} = g_{m2} R_D \frac{R_B}{1+g_{m1} R_S + R_B}\]
Question 04

Question 4

For the circuit shown, long-channel NMOS is biased in saturation with small signal transconductance \( g_m \). Neglect body effect, channel-length modulation, and intrinsic capacitances. The small-signal input impedance \( Z_{in} \) is ___.

  1. \( g_m C_1 C_L \frac{2}{1/jC_1 + 1/jC_L} \)
  2. \( g_m C_1 C_L \frac{2}{1/jC_1 + 1/jC_L} \)
  3. \( \frac{1}{jC_1 + 1/jC_L} \)
  4. \( g_m C_1 C_L \frac{2}{1/jC_1 jC_L} \)
GATE 2024 Analog Electronics Q4 NMOS circuit diagram
GATE 2024 Analog Electronics Q4 NMOS circuit diagram

Solution

The drain sits at \( V_{DD} \), a small-signal ground, so the device is a source follower. Let \( v_i \) be the gate voltage and \( v_s \) the source voltage; the only path for input current is \( C_1 \), which bridges gate and source.

KCL at the source node, with \( v_{gs} = v_i - v_s \):

Equation
\[(v_i - v_s)\left(j\omega C_1 + g_m\right) = v_s\,j\omega C_L\]

so \( v_s = v_i \dfrac{g_m + j\omega C_1}{g_m + j\omega C_1 + j\omega C_L} \), and the input current is

Equation
\[I_{in} = (v_i - v_s)\,j\omega C_1 = v_i\,\frac{(j\omega)^2 C_1 C_L}{g_m + j\omega C_1 + j\omega C_L}\]
Equation
\[Z_{in}(j\omega) = \frac{1}{j\omega C_1} + \frac{1}{j\omega C_L} + \frac{g_m}{(j\omega)^2 C_1 C_L}\]
A
Final Answer
Correct option: A.
Question 05

Question 5

For the closed-loop amplifier circuit, open-loop small-signal gain \( A_{OL} = 40 \). All transistors in saturation and current source is ideal. Neglect body effect, channel-length modulation, and capacitances. The closed-loop small-signal gain \( \frac{v_{out}}{v_{in}} \), rounded to three decimal places, is ___.

  1. 0.976
  2. 1
  3. 1.025
  4. 0.488
GATE 2024 Analog Electronics Q5 transistor circuit diagram
GATE 2024 Analog Electronics Q5 transistor circuit diagram

Solution

Differential amplifier active load, unity feedback: \( V_f = V_{out} \).

Closed-loop gain:

Equation
\[A_{CL} = \frac{A_{OL}}{1+A_{OL}} = \frac{40}{41} = 0.976\]
Question 06

Question 6

In the op-amp circuit below, if the circuit is to show sustained oscillations, the respective values of \( R_1 \) and the frequency of oscillation are ___ and ___.

  1. \( 29R \) and \( \frac{1}{2\pi\sqrt{6}RC} \)
  2. \( 2R \) and \( \frac{1}{2\pi RC} \)
  3. \( 29R \) and \( \frac{1}{2\pi RC} \)
  4. \( 2R \) and \( \frac{1}{2\pi\sqrt{6}RC} \)
GATE 2024 Analog Electronics Q6 op-amp circuit diagram
GATE 2024 Analog Electronics Q6 op-amp circuit diagram

Solution

The feedback network is a series \(C\) with shunt \(R\) followed by a series \(R\) with shunt \(C\). Writing \(x = \omega RC\), nodal analysis gives

Equation
\[\beta(j\omega) = \frac{V_f}{V_o} = \frac{jx}{1 - x^2 + 3jx}\]

The Barkhausen phase condition needs \(\beta\) real, so \(1 - x^2 = 0\), that is \(x = 1\):

Equation
\[\omega_0 = \frac{1}{RC} \implies f_0 = \frac{1}{2\pi RC}, \qquad \beta = \frac{1}{3}\]

The magnitude condition \(|A\beta| = 1\) then requires a non-inverting gain of 3:

Equation
\[1 + \frac{R_1}{R} = 3 \implies R_1 = 2R\]

So the correct values are \( R_1 = 2R \) and \( f_0 = \frac{1}{2\pi RC} \).

B
Final Answer
Correct option: B.
Question 07

Question 7

Two ideal op-amps saturate at 10 V. Initial inductor current 0 A. Input \( V_i(t) \) is a triangle wave (2V peak, period 8s). Which statement is true?

  1. \( V_{01} \) delayed by 2s relative to Vi, \( V_{02} \) is triangular waveform.
  2. \( V_{01} \) not delayed relative to Vi, \( V_{02} \) is trapezoidal waveform.
  3. \( V_{01} \) not delayed relative to Vi, \( V_{02} \) is triangular waveform.
  4. \( V_{01} \) delayed by 1s relative to Vi, \( V_{02} \) is trapezoidal waveform.
GATE 2024 Analog Electronics Q7 op-amp circuit diagram
GATE 2024 Analog Electronics Q7 op-amp circuit diagram

Solution

Op-amp A1 is a non-inverting Schmitt trigger: the inverting input is grounded, while the non-inverting input is fed by \( V_i \) through 10 k\(\Omega\) and by \( V_{01} \) through the 100 k\(\Omega\) feedback resistor. Switching occurs when that node reaches 0 V:

Equation
\[\frac{10 V_i + V_{01}}{11} = 0 \implies V_i = -\frac{V_{01}}{10}\]

With \( V_{01} = \mp 10\,\text{V} \) the trip points are \( V_{UT} = +1\,\text{V} \) and \( V_{LT} = -1\,\text{V} \).

The triangle swings \( \pm 2 \) V over half a period, so its slope is \( 4\,\text{V} / 4 = 1 \) V per second. Starting from a zero crossing, \( V_i \) therefore takes 1s to reach either trip point.

So \( V_{01} \) (a square wave) switches 1s after the corresponding zero crossing of \( V_i \): it is delayed by 1s.

Op-amp A2 (integrator): saturates quickly, resulting in combination of ramp and flat sections; \( V_{02} \) is a trapezoidal waveform.

D
Final Answer
Correct option: D.
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GATE Analog Electronics