Solved GATE Paper

GATE 2020 Analog Electronics Questions and Solutions

Instructor: Prof. Mithun Mondal Institution: BITS Pilani Subject: Analog Electronics
Question 01

Question 1

In the voltage regulator shown below, \( V_i \) is the unregulated voltage at 15 V. Assume \( V_{BE} = 0.7\,V \) and the base current is negligible for both BJTs. If the regulated output \( V_O = 9\,V \), find the value of \( R_2 \).

GATE 2020 Analog Electronics Q1 BJT circuit diagram
GATE 2020 Analog Electronics Q1 BJT circuit diagram

Solution

[Image of voltage regulator circuit analysis]

The emitter of the error-amplifier BJT is clamped by the Zener at \(V_Z = 3.3\,V\) and its base is driven from the \(R_1\)-\(R_2\) divider across \(V_O\). In regulation the base sits one \(V_{BE}\) above the emitter:

Equation
\[V_{tap} = V_Z + V_{BE} = 3.3 + 0.7 = 4\,V\]

With \(V_O = 9\,V\) applied across \(R_1 = 1\,\text{k}\Omega\) in series with \(R_2\):

Equation
\[9 \times \frac{R_2}{R_2 + 1\,\text{k}\Omega} = 4\]
Equation
\[9R_2 = 4R_2 + 4\,\text{k}\Omega\]
Equation
\[5R_2 = 4\,\text{k}\Omega\]
Equation
\[R_2 = \frac{4000}{5} = 800\,\Omega\]
Question 02

Question 2

For the BJT in the amplifier shown below, \( V_{BE} = 0.7\,V \), \( \frac{kT}{q} = 26\,mV \). Assume the BJT output resistance \( r_o \) is very high and the base current is negligible. The capacitors are short-circuited at signal frequencies. The input \( v_i \) is direct coupled. Find the low-frequency gain \( \frac{v_o}{v_i} \) of the amplifier.

GATE 2020 Analog Electronics Q2 BJT circuit diagram
GATE 2020 Analog Electronics Q2 BJT circuit diagram

Solution

[Image of common emitter amplifier small signal model]

First, find the DC emitter current \(I_{EQ}\):

Equation
\[I_{EQ} = \frac{10 - 0.7}{20} = 0.465\,mA\]

Calculate transconductance \(g_m\):

Equation
\[g_m = \frac{I_{EQ}}{V_T} = \frac{0.465}{26} = 0.0179\,S\]

Voltage gain \(A_V\):

Equation
\[A_V = \frac{v_{out}}{v_{in}} = -g_m R_{L}'\]

\(C_E\) bypasses \(R_E\) at signal frequencies, so the stage is a common emitter with signal load \(R_C \parallel R_L = 10\,k \parallel 10\,k = 5\,k\Omega\), and the gain is inverting:

Equation
\[|A_v| = \frac{0.465}{26} \times 5000 = 89.42\]
Equation
\[A_v = -89.42\]
Question 03

Question 3

In the circuit shown below, all the components are ideal and the input voltage is sinusoidal. The magnitude of the steady-state output \( V_0 \) rounded off to two decimal places is ___ V.

GATE 2020 Analog Electronics Q3 circuit diagram
GATE 2020 Analog Electronics Q3 circuit diagram

Solution

[Image of voltage doubler circuit diagram]

This is a voltage doubler circuit. Input peak voltage \(V_m = 230 \sqrt{2}\).

Equation
\[V_0 = 2V_m = 2 \times 230 \sqrt{2} = 650.54\,V\]
Equation
\[V_0 = 650.54\,V\]
Question 04

Question 4

Using the incremental low-frequency small-signal model of the MOS device, find the Norton equivalent resistance of the circuit.

GATE 2020 Analog Electronics Q4 circuit diagram
GATE 2020 Analog Electronics Q4 circuit diagram

Solution

The two terminals are the source and ground; the gate is grounded and \(V_{DD}\) is a small-signal ground, so \(R\) stands between drain and ground. Drive the source with a test voltage \(V_x\) that draws a test current \(I_x\), giving \(V_{gs} = -V_x\).

All of \(I_x\) flows through \(R\), so the drain sits at \(V_d = I_x R\). The channel current from drain to source is \(-I_x\):

Equation
\[-I_x = g_m V_{gs} + \frac{V_d - V_x}{r_{ds}} = -g_m V_x + \frac{I_x R - V_x}{r_{ds}}\]

Multiplying through by \(r_{ds}\) and collecting terms:

Equation
\[I_x (r_{ds} + R) = V_x (1 + g_m r_{ds})\]

Resulting equivalent resistance:

Equation
\[R_N = \frac{V_x}{I_x} = \frac{r_{ds} + R}{1 + g_m r_{ds}}\]
Question 05

Question 5

An enhancement MOSFET of threshold voltage 3 V is used in a sample and hold circuit. The substrate is connected to -10 V. If the input voltage \( V_I \) lies between \( -10\,V \) and \( +10\,V \), find the minimum \( V_G \) for proper sampling and the maximum \( V_G \) for proper holding.

Solution

For sampling the switch must conduct for every input in the range, so \(V_{GS} > V_T\) has to hold at the worst case \(V_I = +10\,V\):

Equation
\[V_G - 10 > 3 \implies V_{G,\min} = 13\,V\]

For holding the switch must stay off for every input, so \(V_{GS} < V_T\) has to hold at the worst case \(V_I = -10\,V\):

Equation
\[V_G - (-10) < 3 \implies V_{G,\max} = -7\,V\]

Proper sampling needs \( V_G \geq 13\,V \) and proper holding needs \( V_G \leq -7\,V \).

Question 06

Question 6

The components in the circuit below are ideal. If \( R = 2\,k\Omega \) and \( C = 1\,\mu F \), find the -3 dB cut-off frequency of the circuit in Hz.

GATE 2020 Analog Electronics Q6 op-amp circuit diagram
GATE 2020 Analog Electronics Q6 op-amp circuit diagram

Solution

[Image of active low pass filter frequency response]

This is an op-amp active low-pass filter.

Equation
\[f_c = \frac{1}{2\pi RC} = \frac{1}{2 \times \pi \times 2 \times 10^3 \times 10^{-6}} \approx 79.58\,Hz\]

The \(2C\) and \(2R\) branches are tied to the virtual ground at the inverting terminal, so they carry no signal current and drop out of the transfer function, leaving \(\frac{V_o}{V_i} = -\frac{1}{1+j\omega RC}\).

Equation
\[f_c = 79.58\,Hz\]
Question 07

Question 7

In the circuit shown below, all components are ideal. If \( V_i = 2\,V \), find the current \( I_o \) sourced by the op-amp in mA.

GATE 2020 Analog Electronics Q7 op-amp circuit diagram
GATE 2020 Analog Electronics Q7 op-amp circuit diagram

Solution

[Image of non-inverting amplifier circuit analysis]

The stage is non-inverting with \( R_f = R_1 = 1\,k\Omega \), so the gain is 2:

Equation
\[V_o = \left(1 + \frac{R_f}{R_1}\right) V_i = \frac{1 + 1}{1} \cdot 2\,V = 4\,V\]

The output node feeds two branches: the 1 k\(\Omega\) load to ground, and the 1 k\(\Omega\) feedback resistor into the inverting terminal, which the virtual short holds at \(V_i = 2\,V\).

Equation
\[I_{load} = \frac{V_o}{1k} = \frac{4}{1k} = 4\,mA\]
Equation
\[I_{fb} = \frac{V_o - 2}{1k} = \frac{4-2}{1k} = 2\,mA\]
Equation
\[I_o = I_{load} + I_{fb} = 4 + 2 = 6\,mA\]
Question 08

Question 8

The components in the circuit below are ideal. If the op-amp is in positive feedback and the input voltage \( V_i \) is a sine wave of amplitude 1 V, find the output voltage \( V_o \).

GATE 2020 Analog Electronics Q8 op-amp circuit diagram
GATE 2020 Analog Electronics Q8 op-amp circuit diagram
  1. A non-inverted sine wave of 2 V amplitude
  2. An inverted sine wave of 1 V amplitude
  3. A square wave of 5 V amplitude
  4. A constant of either 5 V or -5 V

Solution

[Image of Schmitt trigger hysteresis curve]

Given circuit is a non-inverting Schmitt Trigger (Positive Feedback). Output saturates to rail voltages:

Equation
\[V_o = \pm 5V\]

The two equal 1 k\(\Omega\) resistors place the non-inverting terminal at \(V_+ = \frac{V_i + V_o}{2}\), and the state changes when \(V_+ = 0\), that is when \(V_i = -V_o\). With \(V_o = \pm 5\,V\) the trip points are \(V_i = \mp 5\,V\).

The input is a 1 V sine, so \(|V_i|\) never reaches 5 V and no transition ever occurs. The output stays latched at whichever rail it started in, a constant \( +5\,V \) or \( -5\,V \).

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GATE Analog Electronics