In the circuit shown, transistors \(Q_1\) and \(Q_2\) are biased at a collector current of \(2.6\,mA\). Assuming \(I_C \approx I_E\) and thermal voltage \(V_T=26\,mV\), the magnitude of voltage gain \(V_o/V_i\) in mid-band is:
GATE 2017 Analog Electronics Q1 diode circuit diagram
Solution
[Image of differential amplifier small signal analysis]
The base of \(Q_2\) is bypassed to ground by the capacitor, so at mid-band \(Q_2\) is a common-base stage and \(Q_1\) sees only its emitter resistance:
In the voltage reference circuit with 32 identical transistors, \(V_P=0.7\,V\), \(V_T=26\,mV\), the output voltage \(V_{out}\) is approximately:
GATE 2017 Analog Electronics Q2 transistor circuit diagram
Solution
- Use KCL and log expression for junction voltages. - \(V = V_T \ln 31 + V_P = 0.789\,V\). - \(V_{out} = 5 - 2.8 = 1.145\,V\).
A
Final Answer
Correct answer: A.
Question 03
Question 3
For identical MOSFETs \(M_1\) and \(M_2\) with threshold voltage \(1\,V\), and given operating voltages, the states of \(M_1, M_2\) are:
GATE 2017 Analog Electronics Q3 MOSFET circuit diagram
Saturation, Saturation
Linear, Linear
Linear, Saturation
Saturation, Linear
Solution
- Calculate \(V_{GS1}, V_{GS2}\) and compare with \(V_{DS1}, V_{DS2}\). - Solve current equality for \(V\) and verify operation regions. - Result: \(M_1\) in linear, \(M_2\) in saturation.
C
Final Answer
Correct answer: C.
Question 04
Question 4
Real diode \(D_1\) drop \(0.7\,V\), Zener diode \(D_2\) breakdown \(-6.8\,V\), input periodic square wave \(\pm14\,V\) with \(T \gg \tau\). Maximum and minimum output voltages are:
GATE 2017 Analog Electronics Q4 Zener circuit diagram
\(7.5\,V\) and \(-20.5\,V\)
\(6.1\,V\) and \(-21.9\,V\)
\(7.5\,V\) and \(-21.9\,V\)
\(6.1\,V\) and \(-22.6\,V\)
Solution
\(D_1\) and \(D_2\) face each other cathode to cathode, so the branch conducts only for a positive output, with \(D_1\) forward biased and \(D_2\) in breakdown:
Equation
\[V_{out(\max)} = 0.7 + 6.8 = 7.5\,V\]
During the \(+14\,V\) half cycle the output is clamped at \(7.5\,V\), so the capacitor charges to \(14 - 7.5 = 6.5\,V\) with its input-side plate positive. For a negative output the branch blocks, the capacitor holds that charge, and the input swing appears directly at the output:
Equation
\[V_{out(\min)} = -14 - 6.5 = -20.5\,V\]
A
Final Answer
Correct answer: A.
Question 05
Question 5
[2] In the transistor circuit with \(V_{BE} = 0.8\,V\), \(\alpha=1\), and resistors shown, collector-to-emitter voltage \(V_{CE}\) is:
GATE 2017 Analog Electronics Q5 transistor circuit diagram
Average reading of DC voltmeter connected to diode circuit for input \(v(t) = 10 \sin \omega t\), \(f=50\) Hz is:
GATE 2017 Analog Electronics Q6 diode circuit diagram
Solution
The single series diode gives a half-wave rectified voltage across the \(1\,k\Omega\) load, so the meter reads the average of one half sine per period:
NMOS transistor with threshold voltage \(1\,V\), transconductance parameter \(1\,mA/V^2\), connected as shown. Drain current \(I_D\) is (mA):
GATE 2017 Analog Electronics Q9 NMOS circuit diagram
Solution
The gate divider gives \(V_G = 8 \times \frac{5}{3+5} = 5\,V\), and the \(1\,k\Omega\) source resistor makes \(V_{GS} = 5 - I_D R_S\). With \(I_D\) in mA:
The roots are \(8\,mA\) and \(2\,mA\). The first gives \(V_{GS} = -3\,V < V_{TH}\) and is discarded, so \(I_D = 2\,mA\). Then \(V_{GS} = 3\,V\) and \(V_{DS} = 8 - 2(1+1) = 4\,V > V_{GS}-V_{TH} = 2\,V\), confirming saturation.
Question 10
Question 10
For common emitter amplifier with given resistor values, midband voltage gain magnitude is (approximately):
GATE 2017 Analog Electronics Q10 amplifier circuit diagram
Solution
[Image of Common Emitter amplifier small signal model]