GATE 2016 Analog Electronics Questions and Solutions

In the circuit shown below, transistor M1 is in saturation and has transconductance \(g_m = 0.01\) S. Ignoring internal parasitic capacitances and assuming channel length modulation \(\lambda = 0\), the small signal input pole frequency (in kHz) is:

Solution

The gain from input to output is calculated using Miller's equivalent circuit. Small-signal AC analysis yields the total resistance and capacitance at the input node.

[Image of Miller effect capacitance]

With \(\lambda = 0\) the gain from gate to drain is \[ A_V = -g_m R_D = -0.01 \times 1\times 10^{3} = -10 \] so Miller's theorem reflects the \(50\) pF gate-drain capacitance to the input as \[ C_{in} = C(1 - A_V) = 50\,\text{pF} \times 11 = 550\,\text{pF} \]

The input node sees the source resistance \(R_S = 5~\text{k}\Omega\), so the input pole is at \[ f_p = \frac{1}{2\pi R_S C_{in}} = \frac{1}{2\pi \times 5\times 10^{3} \times 550\times 10^{-12}} = 57.9~\text{kHz} \]

In the circuit shown below, channel length modulation of all transistors is non-zero, and all transistors operate in saturation with negligible body effect. The AC small signal voltage gain \(\frac{V_o}{V_{in}}\) of the circuit is:

1. \(g_{m1}r_{o1}r_{o3}\)
2. \(g_{m2}r_{o1}r_{o2}r_{o3}\)
3. \(g_{m1}r_{o1}r_{o3}r_{o2}\)
4. \(g_{m1}r_{o1}r_{o3}r_{o2}\)

Solution

[Image of Cascode amplifier small signal model]

With channel length modulation, output resistance per MOSFET is \(r_{o}\). For a cascode, the total gain is the product of \(g_m\) and all output resistances in the signal path. Therefore, \(A_v = g_{m1} r_{o1} r_{o3} r_{o2}\).

[2] For the circuit shown below, \(R_1 = R_2 = R_3 = 10~\Omega\), \(L = 1\) H and \(C = 1\) F. If the input \(V_{in} = \cos(10^6 t)\), then the overall voltage gain \(\frac{V_{out}}{V_{in}}\) is:

Solution

[Image of RLC circuit resonance analysis]

The first stage is non-inverting with a series \(RC\) branch in its feedback path, so \[ V_1 = \left(1 + \frac{1}{sRC}\right)V_{in} \]

The second stage is inverting, driven through an identical series \(RC\) branch and fed back through \(R\): \[ V_{out} = -\frac{R}{R + 1/(sC)}V_1 = -\frac{V_1}{1 + 1/(sRC)} \]

The two identical factors cancel, so \[ \frac{V_{out}}{V_{in}} = -1 \] independently of frequency.

In the astable multivibrator circuit shown, the frequency of oscillation (in kHz) at output pin 3 is:

Solution

[Image of 555 timer astable mode schematic]

For a 555 in astable mode the free-running frequency is \[ f = \frac{1}{0.69\,(R_A + 2R_B)C} \] With \(R_A = 2.2\;\text{k}\Omega\), \(R_B = 4.7\;\text{k}\Omega\) and \(C = 0.022\,\mu\text{F}\), \[ R_A + 2R_B = 2.2 + 9.4 = 11.6~\text{k}\Omega \]

so \[ f = \frac{1}{0.69 \times 11.6\times 10^{3} \times 0.022\times 10^{-6}} = 5.68~\text{kHz} \]

Consider the circuit shown below. Assuming \(V_{BE1} = V_{EB2} = 0.7\) V, the value of the DC voltage \(V_{C2}\) (in volts) is:

Solution

Both junctions are forward biased, so KVL around the base loop - which contains \(V_{BE1}\), \(V_{EB2}\) and the \(10~\text{k}\Omega\) base resistor of \(Q_2\) - leaves \(0.1\) V across that resistor: \[ I_{B2} = \frac{0.1}{10\times 10^{3}} = 10~\mu\text{A} \]

With \(\beta = 50\), \[ I_{C2} = \beta I_{B2} = 50 \times 10~\mu\text{A} = 0.5~\text{mA} \] and this current flows in the \(1~\text{k}\Omega\) collector resistor, so \[ V_{C2} = I_{C2}R_{C2} = 0.5\times 10^{-3} \times 1\times 10^{3} = 0.5~\text{V} \]

The diodes D1 and D2 in the figure are ideal and the capacitors are identical. The product RC is very large compared to the time period of the AC voltage. Assuming that the diodes do not breakdown in reverse bias, the output voltage \(V_o\) (in volt) at steady state is:

Solution

Because \(RC\) is much larger than the period, each capacitor charges to the peak of the ac source and then holds that voltage while its diode is reverse biased. \(D_1\) charges its capacitor to \(+V_m\) and \(D_2\) charges the other to \(-V_m\), so in steady state KVL around the output loop gives \[ V_o = V_{C1} + V_{C2} = V_m + (-V_m) = 0~\text{V} \]

An opamp has a finite open loop voltage gain of 100. Its input offset voltage \(V_{ios}\) \(= 5\) mV is modeled as shown in the circuit below. The amplifier is ideal in all other respects. \(V_\text{input} = 25\) mV. The output voltage (in mV) is:

Solution

[Image of op amp input offset voltage model]

The offset source sits in series with the signal, so the amplifier sees \[ V_\text{input} + V_{ios} = 25 + 5 = 30~\text{mV} \] The feedback network sets an ideal closed-loop gain of \[ 1 + \frac{R_f}{R_1} = 1 + \frac{15}{1} = 16 \]

With a finite open-loop gain \(A = 100\) the realised closed-loop gain is \[ A_{CL} = \frac{16}{1 + 16/100} = \frac{16}{1.16} = 13.79 \] so \[ V_{out} = 13.79 \times 30 = 413.8~\text{mV} \]

In the opamp circuit shown, the Zener diodes Z1 and Z2 clamp the output voltage V to 5 V or -5 V. The switch S is initially closed and is opened at time \(t_0\). The time \(t_T\) (in seconds) at which \(V_o\) changes state is:

Solution

With S closed the inverting input is tied to \(+10\) V, so the output sits at the negative clamp level \(V_o=-5\) V and the non-inverting input is held at

When S opens the capacitor charges through the \(10~\mathrm{k}\Omega\) resistor with \(\tau = RC = 10~\mathrm{k}\Omega \times 100~\mu\mathrm{F} = 1\) s, starting from \(+10\) V and heading for \(-10\) V:

The output changes state when \(V_-\) falls to \(V_+ = -1\) V:

The figure shows a half-wave rectifier with a \(475\,\mu\)F filter capacitor. The load draws a constant current \(I=1\)A from the rectifier. The input voltage \(V_i\) is a triangle wave with an amplitude of \(10\) V, period of \(1\) ms. The value of the ripple \(u\) (in volts) is:

Solution

Ripple voltage \(u = I/(fC)\) for half-wave; \(u = 1\times10^{-3}/(1 \times 475\times10^{-6}) = 2.15\) V.

Which one of the following statements is correct about an ac-coupled common-emitter amplifier operating in the mid-band region?

1. The device parasitic capacitances behave like open circuits, whereas coupling and bypass capacitances behave like short circuits.
2. The device parasitic capacitances, coupling capacitances and bypass capacitances behave like open circuits.
3. The device parasitic capacitances, coupling capacitances and bypass capacitances behave like short circuits.
4. The device parasitic capacitances behave like short circuits, whereas coupling and bypass capacitances behave like open circuits.

Solution

Resistor R in the circuit has been adjusted so that \(I=1\) mA. The bipolar transistors Q1 and Q2 are perfectly matched and have very high current gain. The supply voltage \(V_{cc}=6\) V. The thermal voltage \(kT/q=26\) mV. The value of \(R_2\) in \(\Omega\) for which \(I_2=100uA\) is:

Solution

Assume the diode in the figure has \(V_{on} = 0.7\) V, but is otherwise ideal. The magnitude of current \(i_2\) (in mA) is:

Solution

Test the diode ON: the parallel branch would sit at \(0.7\) V, so \(i_2 = (2-0.7)/6~\mathrm{k}\Omega = 0.217\) mA while \(R_1\) alone carries \(0.7/2~\mathrm{k}\Omega = 0.35\) mA. The diode current would be \(0.217 - 0.35 = -0.133\) mA, which is impossible, so the diode is OFF.

With the diode open, \(R_1\) and \(R_2\) are simply in series across the source:

The drop across \(R_1\) is then \(0.5\) V, below \(V_{on}=0.7\) V, which confirms the diode stays off. Hence \(i_2 = 0.25\) mA.

The Ebers-Moll model of a BJT is valid:

1. Only in active mode.
2. Only in active and saturation modes.
3. Only in active and cut-off modes.
4. In active, saturation and cut-off modes.

Solution

Model describes all three regions of operation: active, saturation, and cut-off—matching full transistor functionality.

A p-i-n photodiode of responsivity \(0.8\) A/W is connected to the inverting input of an ideal opamp, \(V_{cc} = 15\) V, \(-V_{cc} = -15\) V, load resistor \(R = 10\) k\(\Omega\). \(10~\mu\)W power incident on photodiode. What is the photocurrent (in \(\mu\)A)?

Solution

The photo current through load \(R_L=10\,\mathrm{k}\Omega\) is given by

In the ideal opamp with voltages \(V_1, V_2, \ldots\), as \(N \rightarrow \infty\) and alternating+, what is the output voltage (in V)?

Solution

Large alternating sum forces opamp output to saturate to positive supply rail. Thus, output is \(15\) V.

What is the voltage \(V_{out}\) in the following CMOS inverter circuit?

1. \(A~V_{DD}\)
2. \(B~V_{TN}(\text{NMOS threshold})\)
3. \(C~\text{Switching threshold}\)
4. \(D~V_{TP}(\text{PMOS threshold})\)

Solution

[Image of CMOS inverter voltage transfer characteristics]

When input equals the switching threshold, NMOS and PMOS both conduct, \(V_{out}\) corresponds to inverter threshold.

Consider the oscillator circuit shown. What is the function of the network (dotted box)?

1. Amplitude stabilization by preventing saturation of opamp (fixed sinusoidal oscillations).
2. Amplitude stabilization by forcing square wave oscillations.
3. Frequency stabilization at a single frequency.
4. Loop gain enables square wave oscillations.

Solution

Resistor-diode network limits output swing to below opamp rails, sustains sinusoidal oscillation with fixed amplitude.

For the signal \(V_i\) (peak voltage \(8\) V) applied to non-inverting terminal of an opamp, transistor \(V_{BE}=0.7\)V, \(\beta =100\), \(V_{LED}=1.5\)V, \(V_{cc}=10\)V, \(-V_{cc}=-10\)V. How many times does the LED glow?

Solution

LED glows each time \(V_{i}>2\) V driving BJT/LED. Given waveform crosses above 2V threshold 3 times.