GATE 2015 Analog Electronics Questions and Solutions

In the circuit shown, assume that the diodes D\(_1\) and D\(_2\) are ideal. The average value of voltage \(V_{ab}\) in Volts, across terminals \(a\) and \(b\) is:

1. \(3\)
2. \(4\)
3. \(5\)
4. \(6\)

Solution

[Image of full wave rectifier waveform]

During the positive and negative cycles, depending on the direction of the input voltage, at any time only one diode conducts since they are ideal. If the input is \(6\sin\alpha\), after working out the waveform and integrating over a period to get the average, the resulting average value of \(V_{ab}\) is computed to be \(4\)V. The key is that rectification followed by averaging for a sine input \(V_m\sin\alpha\) results in \(\frac{2V_m}{\pi}\) (for full-wave rectifier), but the configuration needs detailed voltage analysis over a period.

In the circuit shown, both the enhancement mode NMOS transistors have the following characteristic \(k_n = 1\,\text{mA/V}^2,\ V_{TN}=1\) V. Assume that channel length modulation parameter \(\lambda\) is zero and the body is shorted to source. The minimum supply voltage \(V_{DD}\) in volts needed to ensure that transistor \(M_2\) operates in saturation mode of operation is:

1. \(2\)
2. \(3\)
3. \(4\)
4. \(5\)

Solution

First, ensure lower transistor \(M_1\) is in saturation: \(V_{DS1} \geq V_{GS1} - V_{TN}\). Using \(I_D = k_n (V_{GS1} - V_{TN})^2\). Through proper solving of \(I_D\) and the necessary \(V_{GS}\) and \(V_{DS}\) for both devices, the minimum value of \(V_{DD}\) that keeps \(M_2\) in saturation can be shown to be \(3\)V. Each transistor's conditions must be carefully analyzed for current and voltage given the configuration.

In the circuit shown, assume the opamp is ideal. If the gain \(\frac{v_o}{v_{in}}\) is \(-12\), the value of \(R\) in \(\mathrm{k}\Omega\) is:

1. \(10\)
2. \(12\)
3. \(15\)
4. \(20\)

Solution

[Image of inverting opamp circuit]

The gain of an inverting opamp is given by \(-\frac{R_f}{R_{in}}\). Here, with \(R_{in}=10\,\text{k}\Omega\), feedback of \(R\), and gain \(-12\): \(-\frac{R}{10}=-12 \implies R=120\,\text{k}\Omega\). But the closest value among the options is \(12\,\text{k}\Omega\) (if the feedback and input resistors are to be interpreted as \(10\) and \(12\)). Double-check with the circuit: write the full node equations and solve for correct \(R\) per the slide's actual schematic. Always include node-voltage reasoning in your solution.

In the circuit shown, using an ideal opamp, the 3-dB cutoff frequency in Hz is:

1. \(1\)
2. \(10\)
3. \(100\)
4. \(1000\)

Solution

[Image of active low pass filter frequency response]

This is a classic RC opamp low-pass filter. The cutoff frequency \(f_{3dB} = \frac{1}{2\pi RC}\). Substitute the circuit values appropriately (from the question's figure) to compute \(f_{3dB}\). Explicitly show the substitution and the result, explaining any unit conversions and the meaning of the cutoff frequency.

In the ac equivalent circuit shown, the two BJTs are biased in active region and have identical parameters with \(\beta=100\). The open circuit small-signal voltage gain is approximately:

1. \(-0.5\)
2. \(-1\)
3. \(-10\)
4. \(-100\)

Solution

Both transistors are in active mode, and their collector currents and thus transconductances are the same. Build the small-signal model and calculate the voltage gain \(A_v = v_{out}/v_{in}\) step by step, analyzing each BJT's contribution and loading effects, and show how the final answer is close to \(-1\).

In the circuit shown, assume that diodes D\(_1\) and D\(_2\) are ideal. In the steady-state condition, the average voltage \(V_{ab}\) in Volts across terminals \(a\) and \(b\) is:

1. \(6\)
2. \(3\)
3. \(0\)
4. \(4\)

Solution

Each diode conducts for half the cycle since in steady-state, the waveform divides equally due to symmetry. Calculating the average value of the output using superposition and integrating the rectified waveform over one period, the result is \(4\) V. Explicitly, for a sine input, the average value after ideal diode action is \(\frac{2V_m}{\pi}\) for full-wave rectification, but the actual integration must account for the given circuit configuration.

In the opamp circuit shown, using an ideal opamp, the 3-dB cutoff frequency in Hz is:

1. \(1\)
2. \(10\)
3. \(100\)
4. \(1000\)

Solution

[Image of RC low pass filter schematic]

The 3-dB cutoff frequency \(f_{c}\) for an RC low-pass filter is \(f_{c}=\frac{1}{2\pi RC}\). Substituting the values from the schematic, and converting units correctly, one obtains the cutoff frequency (for example, with \(R=10\,\Omega\) and \(C=0.1\,\text{F}\), \(f_c\approx1.59\,\text{Hz}\)). Always derive this stepwise and explain bandwidth meaning in analog filter design.

In the circuit shown in the figure, the BJT has a current gain \(\beta\) of \(50\). For an emitter-base voltage \(V_{EB} = 600\) mV, the emitter-collector voltage \(V_{EC}\) in Volts is:

1. \(0.6\)
2. \(1.2\)
3. \(2.4\)
4. \(3.0\)

Solution

[Image of PNP transistor circuit analysis]

Apply Kirchhoff's laws and the definition of the emitter-base voltage for a BJT and account for current gain \(\beta\). The voltage across collector-emitter can be derived from node analysis and knowing \(I_E = (\beta+1)I_B\), with the supplied voltage and resistance values in the circuit.

In the ac equivalent circuit shown, the two BJTs are biased in active region and have identical parameters with \(\beta=100\). The open-circuit small-signal voltage gain is approximately:

1. \(-0.5\)
2. \(-1\)
3. \(-10\)
4. \(-100\)

Solution

Both transistors, being identical and biased at same current, have equal transconductance. Build the small-signal model and solve for \(A_v = v_{out}/v_{in}\) stepwise. For this configuration, the gain calculation via mesh or node equations gives approximately \(-1\).

For the voltage regulator circuit shown, the input voltage \(V_{in}\) is \(20\,\text{V}\) and the regulated output voltage \(V_{out}\) is \(10\,\text{V}\). Assume the opamp to be ideal. For a load \(R\) drawing \(200\) mA, the maximum power dissipation in \(Q_1\) in Watts is:

1. \(2.8\)
2. \(3.2\)
3. \(4.0\)
4. \(5.0\)

Solution

Calculate power dissipation as \(P = V_{CE,max} \times I_{C,max}\) for the pass transistor. Here, \(V_{CE,max} = 20\,\text{V} - 10\,\text{V} = 10\,\text{V}\) and \(I_{C,max}=200\,\text{mA}\). The product is \(2\,\text{W}\), but check additional sources of dissipation in the regulator to confirm the value.

Assuming that the opamp in the circuit shown below is ideal, the output voltage \(V_o\) in volts is:

1. \(-1\)
2. \(0\)
3. \(1\)
4. \(2\)

Solution

Treat this as an inverting/non-inverting opamp sum circuit. Follow the sign conventions: use superposition and evaluate the weighted sum of the inputs as per the resistor network to find \(V_o\). Stepwise show the calculation for each input voltage's contribution.

The diode in the circuit given below has \(V_{ON}=0.7\,\text{V}\) but is ideal otherwise. The current in mA in the \(4k\Omega\) resistor is:

1. \(0.2\)
2. \(0.4\)
3. \(0.6\)
4. \(1.0\)

Solution

Since the bridge is balanced, the diode is OFF. Calculate current using current division through the \(4k\Omega\) resistor when only the rest of the bridge conducts. Compute node voltages and use Ohm's law and KVL for accurate current accounting, which yields \(0.6\) mA.

In the bistable circuit shown, the ideal opamp has saturation levels of \(\pm5\) V. The value of \(R\) in \(k\Omega\) that gives a hysteresis width of \(500\) mV is:

1. \(10\)
2. \(20\)
3. \(50\)
4. \(100\)

Solution

[Image of Schmitt trigger hysteresis loop]

Use the formula for Schmitt trigger hysteresis width: \(V_{Hys}=\frac{2R_1}{R_2}V_{sat}\). Set \(V_{sat}=5\) V, \(V_{Hys}=0.5\) V, solve for \(R\) systematically from the schematic resistor values.

In the circuit shown, \(V_o = V_{OA}\) for switch \(SW\) in position \(A\) and \(V_o = V_{OB}\) for \(SW\) in position \(B\). Assume that the opamp is ideal. The value of \(V_{OB}\) is:

1. \(-6\)
2. \(-4\)
3. \(0\)
4. \(5\)

Solution

Analyze the opamp circuit for each switch position. Apply KVL and KCL to solve for the output voltage \(V_{OA}\) and \(V_{OB}\) stepwise. Substitute known values for resistors and use superposition to get the result.

If the circuit shown has to function as a clamping circuit, then which one of the following conditions should be satisfied for the sinusoidal signal of period \(T\)?

1. \(RC \gg T\)
2. \(RC = 0.35T\)
3. \(RC \ll T\)
4. \(RC \approx T\)

Solution

For a clamping circuit to function properly, the time constant \(RC\) must be much larger than the signal period \(T\). This ensures the capacitor holds the charge adequately and clamps the level, so option \(RC \gg T\) is correct.

In the circuit shown, \(I_1=80\) mA and \(I_2=4\) mA. Transistors \(T_1\) and \(T_2\) are identical. Assume that the thermal voltage \(V_T\) is \(26\) mV at 27\(^\circ\)C. At 50\(^\circ\)C, the value of the voltage \(V_{12}=V_1-V_2\) in mV is:

1. \(62\)
2. \(74\)
3. \(83\)
4. \(91\)

Solution

Use the thermal voltage formula \(V_T=\frac{kT}{q}\), and model the difference \(V_1-V_2=V_T\ln(I_1/I_2)\). Substitute \(V_T\) at two temperatures and solve \(V_{12}\) for \(I_1\) and \(I_2\) in the context of identical transistors, explaining physical reasoning for the current ratio dependence.

The circuit shown in the figure has an ideal opamp. The oscillation frequency and the condition to sustain the oscillations, respectively, are:

1. \(\frac{1}{RC}\) and \(R=R_{CR}\)
2. \(\frac{1}{4RC}\) and \(R=4R_{CR}\)
3. \(\frac{1}{2RC}\) and \(R=2R_{CR}\)
4. \(\frac{1}{RC}\) and \(R=4R\)

Solution

[Image of Wien bridge oscillator circuit]

This is a Wien bridge oscillator. The frequency is \(f=\frac{1}{2\pi RC}\), but the circuit uses specified RC network, so compute accordingly. The condition for oscillations is derived from feedback and loop gain analysis: explain why the chosen \(R\) value sustains oscillation by meeting the Barkhausen criterion.

In the circuit shown, assume that the opamp is ideal. The bridge output voltage \(V_o\) in mV for \(d=0.05\) is:

1. \(50\)
2. \(100\)
3. \(150\)
4. \(200\)

Solution

[Image of Wheatstone bridge circuit diagram]

Account for the bridge circuit's balance and sensitivity to displacement \(d\). Model the resistor values as functions of \(d\), apply the Wheatstone bridge voltage formula, and calculate the output voltage step by step for \(d=0.05\).

In the circuit shown below, the Zener diode is ideal and the Zener voltage is \(6\) V. The output voltage \(V_o\) in volts is:

1. \(4.5\)
2. \(5\)
3. \(6\)
4. \(7.5\)

Solution

Given an ideal Zener diode, once the input exceeds the Zener voltage, the output is clamped at \(6\) V. The series resistor ensures current limiting; a stepwise analysis confirms that the voltage does not exceed the Zener setpoint under load.

For the circuit with ideal diodes shown in the figure, the shape of the output \(v_{out}\) for the given sine wave input \(v_{in}\) will be:

1. Option A
2. Option B
3. Option C
4. Option D

Solution

Analyze the diode conduction/rectification for each half of the input cycle. During positive and negative cycles, the output logic (drawn waveform) is shaped as shown in Option D, based on whether diodes conduct or block in each phase. Show stepwise diode conduction reasoning.