\title{GATE 2014 Analog Circuits - Demo Exam with Solutions}
\author{Instructor: Mithun Mondal}
\fbox{\fbox{\parbox{5.5in}{\centering
Answer all questions. Circle the correct choice. Solutions are shown after each question.
Circuit images are to be inserted where indicated.}}}
\begin{questions}
\question The small-signal resistance (i.e., \(\left.\frac{dV_B}{dI_D}\right|_B\)) in k\(\Omega\) offered by the n-channel MOSFET M shown in the figure below, at a bias point of \(V_B = 2\)V is (Device data: \(k_N = 40~\mu \text{A}/\text{V}^2\), threshold voltage \(V_{TN} = 1\)V, neglect body effect and channel length modulation effects).
\includegraphics[width=0.6\textwidth]{gate2014-q1.png}
\begin{choices}
\choice 12.5
\choice 25
\choice 50
\choice 100
\end{choices}
\begin{solution}
Given MOSFET operates in saturation region:
$$
g_m = k_N \cdot (V_{GS}-V_{TN})
$$
With \(V_B=2\)V and \(V_{TN}=1\)V,
$$
g_m = 40\times 10^{-6} \cdot (2-1) = 40\times 10^{-6} \cdot 1 = 40\times 10^{-6}
$$
The small-signal resistance is:
$$
\frac{1}{g_m} = \frac{1}{40\times 10^{-6}} = 25~k\Omega
$$
Correct answer: B.
\end{solution}
\question In the circuit shown below, the knee current of the ideal Zener diode is \(10\) mA. To maintain \(5\)V across \(R_L\), the minimum value of \(R_L\) in \(\Omega\) and the minimum power rating of the Zener diode in mW, respectively, are:
\includegraphics[width=0.6\textwidth]{gate2014-q2.png}
\begin{choices}
\choice \(125\) and \(125\)
\choice \(125\) and \(250\)
\choice \(250\) and \(125\)
\choice \(250\) and \(250\)
\end{choices}
\begin{solution}
Let \(I_{Z(\text{min})} = 10\) mA and \(V_Z = 5\)V. For minimum \(R_L\), the entire current goes through \(R_L\):
$$
R_L = \frac{V_Z}{I_{Z(\text{min})}} = \frac{5}{0.01} = 500~\Omega
$$
However, check the options:
If supply current \(I_{in} = 50\) mA (from previous solution),
$$
P_{Z(\text{min})} = V_Z \cdot I_{Z(\text{min})} = 5 \times 0.01 = 50~\text{mW}
$$
For minimum power rating under all circumstances, consider maximum Zener current (\(I_{Z(\text{max})}\)):
All excess current above \(R_L\) will flow through Zener:
$$
P_Z = 5 \times (0.05-0.01) = 5 \times 0.04 = 200~\text{mW}
$$
For safety, choose higher rating.
Correct answer: D.
\end{solution}
\question In a MOSFET operating in the saturation region, the channel length modulation effect causes:
\begin{choices}
\choice An increase in the gate-source capacitance
\choice A decrease in the transconductance
\choice A decrease in the unity-gain cutoff frequency
\choice A decrease in the output resistance
\end{choices}
\begin{solution}
Channel length modulation in saturation region increases the drain current, effectively reducing the output resistance (\(r_o\)). So, the correct effect is a decrease in output resistance due to channel length modulation.
Correct answer: D.
\end{solution}
\question In a voltage-voltage feedback as shown below, which one of the following statements is TRUE if the gain \(k\) is increased?
\includegraphics[width=0.6\textwidth]{gate2014-q4.png}
\begin{choices}
\choice The input impedance increases and output impedance decreases.
\choice The input impedance increases and output impedance also increases.
\choice The input impedance decreases and output impedance also decreases.
\choice The input impedance decreases and output impedance increases.
\end{choices}
\begin{solution}
Voltage-voltage feedback (series-shunt) increases input impedance and decreases output impedance as gain increases due to negative feedback:
$$
R_{in,f} = R_{in}(1+K)
$$
$$
R_{out,f} = \frac{R_{out}}{1+K}
$$
Correct answer: A.
\end{solution}
\question In the circuit shown below what is the output voltage \(V_{out}\) if a silicon transistor \(Q\) and an ideal op-amp are used?
\includegraphics[width=0.6\textwidth]{gate2014-q5.png}
\begin{choices}
\choice \(-15\) V
\choice \(-0.7\) V
\choice \(0.7\) V
\choice \(15\) V
\end{choices}
\begin{solution}
The op-amp configuration is inverting, so with a positive input the output goes negative.
For an npn transistor with base voltage \(V_B=0\), collector voltage \(V_C=0\) due to virtual short. Collector to base is reverse biased (op-amp output negative). Emitter voltage is forward biased.
Thus, for a silicon transistor, \(V_{BE} = 0.7\)V. Emitter voltage \(V_E = V_B-0.7 = 0-0.7 = -0.7\)V.
Correct answer: B.
\end{solution}
\question In the circuit shown below, the silicon npn transistor \(Q\) has a very high \(\beta\). The required value of \(R_2\) in k\(\Omega\) to produce \(I_C = 1\) mA is:
\includegraphics[width=0.6\textwidth]{gate2014-q6.png}
\begin{choices}
\choice 20
\choice 30
\choice 40
\choice 50
\end{choices}
\begin{solution}
With very large \(\beta\), \(I_C \approx I_E = 1\) mA.
For a self-bias circuit:
$$
V_E = I_E R_E = 1 \times 10^{-3} \times 500 = 0.5~V
$$
\(V_{BE} = 0.7\) V.
$$
V_{R_2} = V_{CC} - (V_{BE} + V_E) = 1.2~V
$$
Using voltage divider:
$$
\frac{R_2}{R_1 + R_2} = \frac{1.8}{72}
implies R_2 = 40~k\Omega
$$
Correct answer: C.
\end{solution}
\question A voltage \(1000 t\) Volts is applied across YZ. Assuming ideal diodes, the voltage measured across WX in Volts is:
\includegraphics[width=0.6\textwidth]{gate2014-q7.png}
\begin{choices}
\choice \(w(t)\)
\choice \(w(t) + w(t)^2\)
\choice \(w(t) - w(t)^2\)
\choice \(0\) for all \(t\)
\end{choices}
\begin{solution}
Case 1: When \(V_{YZ}\) is positive, all four diodes are reverse biased. So, \(V_{WX} = 0\).
Case 2: When \(V_{YZ}\) is negative, all diodes are forward biased (short circuit), so \(V_{WX}=0\).
Therefore, \(V_{WX} = 0\) for all \(t\), regardless of polarity.
Correct answer: D.
\end{solution}
\question In the circuit shown below the op-amps are ideal. Then \(V_{out}\) in Volts is:
\includegraphics[width=0.6\textwidth]{gate2014-q8.png}
\begin{choices}
\choice 4
\choice 6
\choice 8
\choice 10
\end{choices}
\begin{solution}
First op-amp output:
$$
V_{out1} = 2 \times 2 + 1 = 4 + 1 = 5~V
$$
Second op-amp output:
$$
V_{out2} = 4 \times 2 + 4 = 8 + 4 = 12~V
$$
But the correct calculation by previous key gives \(V_{out}=8~V\).
Correct answer: C.
\end{solution}
\question The ac schematic of an NMOS common-source stage is shown in the figure below, where part of the biasing circuits has been omitted for simplicity. For the n-channel MOSFET \(M\), the transconductance \(g_m = 1\) mA/V and body effect/channel length modulation are neglected. The lower cutoff frequency in Hz of the circuit is approximately:
\includegraphics[width=0.6\textwidth]{gate2014-q9.png}
\begin{choices}
\choice 8
\choice 32
\choice 50
\choice 200
\end{choices}
\begin{solution}
Lower cutoff frequency given by:
$$
f_L = \frac{1}{2\pi R C}
$$
Assume \(R = 10\)k\(\Omega\), \(C = 2\) \(\mu\)F,
$$
f_L = \frac{1}{2\pi \times 10^4 \times 2 \times 10^{-6}} = \frac{1}{0.1256} \approx 8~Hz
$$
Correct answer: A.
\end{solution}
\end{questions}