GATE 2014 Analog Electronics Questions and Solutions

The small-signal resistance (i.e., \( \left.\frac{dV_B}{dI_D}\right|_B \)) in k\(\Omega\) offered by the n-channel MOSFET M shown in the figure below, at a bias point of \(V_B = 2\)V is (Device data: \(k_N = 40~\mu \text{A}/\text{V}^2\), threshold voltage \(V_{TN} = 1\)V, neglect body effect and channel length modulation effects).

1. 12.5
2. 25
3. 50
4. 100

Solution

The MOSFET is diode-connected, so it works in saturation and

With \(V_B = V_{GS} = 2\,V\) and \(V_{TN} = 1\,V\):

The small-signal resistance at the bias point is the reciprocal:

In the circuit shown below, the knee current of the ideal Zener diode is \(10\) mA. To maintain \(5\)V across \(R_L\), the minimum value of \(R_L\) in \(\Omega\) and the minimum power rating of the Zener diode in mW, respectively, are:

1. \(125\) and \(125\)
2. \(125\) and \(250\)
3. \(250\) and \(125\)
4. \(250\) and \(250\)

Solution

Once the Zener clamps the output at \(V_Z = 5\,V\), the current delivered through the series resistance is fixed:

This current divides between the diode and the load, \(I_S = I_Z + I_L\).

Minimum \(R_L\). The load can take the most current when the Zener is left with just its knee current, \(I_{Z(\min)} = 10\,\text{mA}\):

Minimum power rating. The worst case for the diode is an open-circuited load, when it carries the whole supply current:

In a MOSFET operating in the saturation region, the channel length modulation effect causes:

1. An increase in the gate-source capacitance
2. A decrease in the transconductance
3. A decrease in the unity-gain cutoff frequency
4. A decrease in the output resistance

Solution

Channel length modulation in saturation region increases the drain current, effectively reducing the output resistance (\(r_o\)). So, the correct effect is a decrease in output resistance due to channel length modulation.

In a voltage-voltage feedback as shown below, which one of the following statements is TRUE if the gain \(k\) is increased?

1. The input impedance increases and output impedance decreases.
2. The input impedance increases and output impedance also increases.
3. The input impedance decreases and output impedance also decreases.
4. The input impedance decreases and output impedance increases.

Solution

Voltage-voltage feedback (series-shunt) increases input impedance and decreases output impedance as gain increases due to negative feedback: \($ R_{in,f} = R_{in}(1+K) \)\( \)\( R_{out,f} = \frac{R_{out}}{1+K} \)$

In the circuit shown below what is the output voltage \(V_{out}\) if a silicon transistor \(Q\) and an ideal op-amp are used?

1. \(-15\) V
2. \(-0.7\) V
3. \(0.7\) V
4. \(15\) V

Solution

The signal is applied to the inverting terminal, so the op-amp output swings negative. The base of \(Q\) is held at ground, \(V_B = 0\). With the collector returned to the positive supply and the op-amp pulling the emitter negative, the base-collector junction is reverse biased while the base-emitter junction is forward biased, so \(Q\) sits in the active region.

For a silicon transistor the forward-biased junction drops \(V_{BE} = 0.7\) V, so the emitter - and therefore the output - sits at \[ V_{out} = V_E = V_B - V_{BE} = 0 - 0.7 = -0.7~\text{V} \]

In the circuit shown below, the silicon npn transistor \(Q\) has a very high \(\beta\). The required value of \(R_2\) in k\(\Omega\) to produce \(I_C = 1\) mA is:

1. 20
2. 30
3. 40
4. 50

Solution

With \(\beta\) very large the base current is negligible, so \(I_C \approx I_E = 1\) mA. The emitter resistor \(R_E = 500~\Omega\) then fixes \[ V_E = I_E R_E = 1\times 10^{-3}\times 500 = 0.5~\text{V} \] and with \(V_{BE} = 0.7\) V for silicon the base must sit at \[ V_B = V_{BE} + V_E = 0.7 + 0.5 = 1.2~\text{V} \]

Because the base draws no current, \(R_1 = 60~\text{k}\Omega\) and \(R_2\) act as an unloaded divider across \(V_{CC} = 3\) V: \[ \frac{3R_2}{R_2 + 60} = 1.2 \quad\Longrightarrow\quad 1.8R_2 = 72 \quad\Longrightarrow\quad R_2 = 40~\text{k}\Omega \]

A voltage \(1000 t\) Volts is applied across YZ. Assuming ideal diodes, the voltage measured across WX in Volts is:

1. \(w(t)\)
2. \(w(t) + w(t)^2\)
3. \(w(t) - w(t)^2\)
4. \(0\) for all \(t\)

Solution

Case 1: When \(V_{YZ}\) is positive, all four diodes are reverse biased. So, \(V_{WX} = 0\). Case 2: When \(V_{YZ}\) is negative, all diodes are forward biased (short circuit), so \(V_{WX}=0\).

Therefore, \(V_{WX} = 0\) for all \(t\), regardless of polarity.

In the circuit shown below the op-amps are ideal. Then \(V_{out}\) in Volts is:

1. 4
2. 6
3. 8
4. 10

Solution

Both op-amps are ideal, so each inverting terminal sits at the potential of its non-inverting terminal and draws no input current. Writing KCL at the node \(V_1\) between the two 1 k\(\Omega\) resistors of the second stage gives \[ V_1 = 4~\text{V} \] The equal 1 k\(\Omega\) resistors in the feedback path put that node at half the output, \(V_1 = V_{out}/2\), so \[ V_{out} = 2V_1 = 8~\text{V} \]

The ac schematic of an NMOS common-source stage is shown in the figure below, where part of the biasing circuits has been omitted for simplicity. For the n-channel MOSFET \(M\), the transconductance \(g_m = 1\) mA/V and body effect/channel length modulation are neglected. The lower cutoff frequency in Hz of the circuit is approximately:

1. 8
2. 32
3. 50
4. 200

Solution

The low-frequency response is set by the coupling capacitor \(C_C = 1~\mu\text{F}\). With \(\lambda = 0\) the drain of \(M\) behaves as an ideal current source, so looking out from \(C_C\) the drain resistor and the load appear in series: \[ R = R_D + R_L = 10 + 10 = 20~\text{k}\Omega \]

Hence \[ f_L = \frac{1}{2\pi R C_C} = \frac{1}{2\pi \times 20\times 10^{3}\times 1\times 10^{-6}} = 7.96 \approx 8~\text{Hz} \]