GATE 2012 Analog Electronics Questions and Solutions

The voltage gain \(A\) of the circuit shown below is:

1. \(A \approx 200\)
2. \(A \approx 100\)
3. \(A \approx 20\)
4. \(A \approx 10\)

Solution

At signal frequencies the capacitors are shorts, and the stage is a shunt-shunt (voltage-shunt) feedback amplifier: the source drives the base through \(R_S = 10\,k\Omega\) and the \(R_F = 100\,k\Omega\) resistor returns the collector signal to the base.

The loop gain is large, so the signal swing at the base is negligible and the base acts as a virtual ground. The whole input current then flows on into the feedback resistor:

The magnitude of the gain is \(|A| \approx 10\).

The circuit shown is a:

1. Low pass filter with \(f_{3dB} = \frac{1}{(R_1 + R_2)C}\) rad/s
2. High pass filter with \(f_{3dB} = \frac{1}{(R_1 + R_2)C}\) rad/s
3. Low pass filter with \(f_{3dB} = \frac{1}{R_1 C}\) rad/s
4. High pass filter with \(f_{3dB} = \frac{1}{R_1 C}\) rad/s

Solution

The op-amp is in the inverting configuration: the input branch is \(R_1\) in series with \(C\), and the feedback element is \(R_2\). Hence

At \(\omega = 0\) the capacitor blocks the input and \(V_o = 0\); as \(\omega \to \infty\) it is a short and \(V_o = -(R_2/R_1)V_i\). Low frequencies are rejected and high frequencies are passed, so this is a high pass filter.

The corner is the pole of \(H(s)\), i.e. the frequency at which the reactance of \(C\) equals \(R_1\):

In the CMOS circuit shown, electron and hole mobilities are equal, and M1 and M2 are equally sized. The device M1 is in the linear region if:

1. \(V_{in} < 1.875\,V\)
2. \(1.875\,V < V_{in} < 3.125\,V\)
3. \(V_{in} > 3.125\,V\)
4. \(0 < V_{in} < 5\,V\)

Solution

M1 is a PMOS transistor. Source Voltage \(V_S = 5\,V\). Gate Voltage \(V_G = V_{in}\). Source-Gate Voltage \(V_{SG} = V_S - V_G = 5 - V_{in}\).

The PMOS is ON when \(V_{SG} > |V_{TP}|\). Assuming \(|V_{TP}| \approx 1\,V\):

For the PMOS to be in the **linear (triode) region**, the condition is:

Based on the detailed analysis of the CMOS inverter transfer characteristics, M1 (PMOS) stays in the linear region when the input voltage is low (logic 0) and transitions to saturation as \(V_{in}\) increases. The transition point calculated for these parameters is typically \(V_{in} < 1.875\,V\).

The diodes and capacitors in the circuit shown are ideal. The voltage \(v(t)\) across the diode \(D_1\) is:

1. \(\cos(\omega t) - 1\)
2. \(\sin(\omega t)\)
3. \(1 - \cos(\omega t)\)
4. \(1 - \sin(\omega t)\)

Solution

The series capacitor and \(D_1\) form a negative clamper. \(D_1\) conducts only while the voltage across it tries to go positive, which happens at the positive peak of the input; the capacitor charges to the peak value \(V_m = 1\,V\) with the polarity that opposes the source.

Everything is ideal, so there is no discharge path and the capacitor holds that \(1\,V\) for the rest of the cycle, keeping \(D_1\) reverse biased. The voltage across \(D_1\) is then the input shifted down by \(1\,V\):

The waveform swings between \(0\) and \(-2\,V\) and never goes positive, which is consistent with \(D_1\) staying off.

The current through the base of a silicon npn transistor is \(1 + 0.1\cos(10000\pi t)\) mA. At \(300\,K\), the \(r_\pi\) in the small signal model of the transistor is:

1. \(250\,\Omega\)
2. \(27.5\,\Omega\)
3. \(25\,\Omega\)
4. \(22.5\,\Omega\)

Solution

The base current is given as a DC component plus an AC component:

The small-signal input resistance \(r_\pi\) is calculated using the DC operating point and the thermal voltage \(V_T\):