GATE 2010 Analog Electronics Questions and Solutions

ANALOG ELECTRONICS GATE 2010 questions and solutions

\section*{1. GATE EE 2010} \subsection*{Analog Circuits}

Consider the common emitter amplifier shown below with the following circuit parameters: \(\beta = 100\), \(g_m = 0.3861\,\mathrm{A/V}\), \(r_0 = \infty\), \(r_a = \infty\), \(r_\pi = 259\,\mathrm{\Omega}\), \(R_s = 1\,\mathrm{k\Omega}\), \(R_B = 93\,\mathrm{k\Omega}\), \(R_C = 250\,\mathrm{k\Omega}\), \(R_L = 1\,\mathrm{k\Omega}\), \(C_1 = \infty\) and \(C_2 = 4.7\,\mathrm{\mu F}\).

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The lower cut-off frequency due to \(C_2\) is:

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Solution:
The lower cut-off frequency \(f_L\) due to the output coupling capacitor \(C_2\) is determined by \(C_2\) and the total resistance in its path. The resistance seen by \(C_2\) is the sum of \(R_C\) and \(R_L\).

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\textit{Note: The question text states \(R_C = 250\,\mathrm{k\Omega}\), but the standard solution calculation uses \(R_C = 250\,\mathrm{\Omega}\) to arrive at the correct answer options. This is likely a typo in the question text.} Using \(R_C = 250\,\mathrm{\Omega}\):

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Correct answer: B.

\section*{2. GATE EE 2010} \subsection*{Analog Circuits}

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The resistance seen by the source \(v_s\) is:

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Solution:
The resistance seen by the source \(v_s\) is \(R_{in}' = R_s + R_{in}\), where \(R_{in}\) is the input resistance of the amplifier stage. The input resistance \(R_{in}\) is the parallel combination of the biasing resistor \(R_B\) and the input resistance at the base of the transistor, \(h_{ie}\) (or \(r_\pi\)).

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The value of \(h_{ie}\) is given as \(r_\pi = 259\,\mathrm{\Omega}\). We can also verify this:

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Now, calculate the parallel combination:

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The total resistance \(R_{in}'\) seen by the source \(v_s\) is:

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Correct answer: B.

\section*{3. GATE EE 2010} \subsection*{Analog Circuits}

The transfer characteristic for the precision rectifier circuit shown below is (assume ideal OP-AMP and practical diodes):

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Solution:
This is a summing amplifier circuit. Since the Op-Amp is ideal, \(V_+ = 0\,\mathrm{V}\), so \(V_- = 0\,\mathrm{V}\) (virtual ground). We can apply KCL at the \(V_-\) node (sum of currents entering = 0). This circuit acts as a precision half-wave rectifier and summing amplifier.

Case 1: \(V_o\) (at op-amp output, before D1) tends to go positive. This happens if \(\frac{V_i}{R} + \frac{20}{4R} > 0 \implies V_i + 5 > 0 \implies V_i > -5\,\mathrm{V}\). If \(V_{op-amp} > 0\), D1 is ON, D2 is OFF. The feedback loop is closed via D1, so \(V_o = V_- = 0\,\mathrm{V}\).

Case 2: \(V_o\) (at op-amp output) tends to go negative. This happens if \(V_i < -5\,\mathrm{V}\). If \(V_{op-amp} < 0\), D1 is OFF, D2 is ON. The feedback loop is now closed via D2 and \(R\). KCL at \(V_-\):

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Checking the points:

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So, for \(V_i > -5\,\mathrm{V}\), \(V_o = 0\,\mathrm{V}\). For \(V_i \le -5\,\mathrm{V}\), \(V_o = -V_i - 5\). This matches graph (B).

Correct answer: B.

\section*{4. GATE EE 2010} \subsection*{Analog Circuits}

Assuming the OP-AMP to be ideal, the voltage gain of the amplifier shown below is:

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Solution:
1. The non-inverting terminal \(V_+\) is connected directly to ground, so \(V_+ = 0\,\mathrm{V}\). 2. For an ideal Op-Amp in negative feedback, the virtual ground principle applies, so the inverting terminal \(V_-\) is also at \(0\,\mathrm{V}\). 3. Now consider resistor \(R_3\). One end is connected to \(V_-\) (which is at \(0\,\mathrm{V}\)) and the other end is connected to ground (\(0\,\mathrm{V}\)). 4. Since both ends of \(R_3\) are at the same potential, no current flows through it. \(R_3\) is effectively shorted out and has no impact on the circuit's operation. 5. The circuit simplifies to a standard inverting amplifier with \(R_1\) as the input resistor and \(R_2\) as the feedback resistor. 6. The voltage gain \(A_v\) for this configuration is:

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Correct answer: A.

\section*{5. GATE EE 2010} \subsection*{Analog Circuits}

The amplifier circuit shown below uses a silicon transistor. The capacitors \(C_C\) and \(C_E\) can be assumed to be short at signal frequency and effect of output resistance \(r_0\) can be ignored. If \(C_E\) is disconnected from the circuit, which one of the following statements is true:

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Solution:
When the emitter bypass capacitor \(C_E\) is connected, it provides a short to ground for AC signals, bypassing the emitter resistor \(R_E\). When \(C_E\) is disconnected, \(R_E\) is part of the AC circuit. This is known as emitter degeneration.

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Therefore, \(R_i\) increases and \(|A_v|\) decreases.

Correct answer: A.

\section*{6. GATE EE 2010} \subsection*{Analog Circuits}

In the silicon BJT circuit shown below, assume that the emitter area of transistor \(Q_1\) is half that of transistor \(Q_2\). The value of current \(I_0\) is approximately:

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Solution:
This is a current mirror circuit. First, we find the reference current \(I_{REF}\) flowing through the \(R=9.3\,\mathrm{k\Omega}\) resistor. The base of \(Q_1\) is \(V_B\). Since it's a silicon BJT, \(V_{BE} \approx 0.7\,\mathrm{V}\). The emitter is at \(-10\,\mathrm{V}\). Therefore, \(V_B = V_{BE} + V_E = 0.7\,\mathrm{V} + (-10\,\mathrm{V}) = -9.3\,\mathrm{V}\). This reference current \(I_{REF}\) flows from ground (\(0\,\mathrm{V}\)) to \(V_B\) through \(R\):

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This current \(I_{REF}\) splits into \(I_{C1}\) and the base currents (\(I_{B1} + I_{B2}\)). Since \(\beta\) is very large (700+), we can neglect the base currents and assume \(I_{C1} \approx I_{REF} = 1\,\mathrm{mA}\). For a current mirror, the collector current is proportional to the saturation current \(I_S\), which is proportional to the emitter area.

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We are given that \(\text{Area}(Q_1) = \frac{1}{2} \text{Area}(Q_2)\), which means \(\text{Area}(Q_2) = 2 \times \text{Area}(Q_1)\).

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Correct answer: B.