GATE 2009 Analog Electronics Questions and Solutions

In the circuit shown below, the switch S is closed at t=0. The value of \(V_{out}(t)\) for \(t > 0\) is given by:

1. \(V_{out}(t) = V_{in}(1 - e^{-t/RC})\)
2. \(V_{out}(t) = V_{in} e^{-t/RC}\)
3. \(V_{out}(t) = V_{in}\)
4. \(V_{out}(t) = 0\)

Solution

Solution: This is an ideal Op-Amp configured as a voltage follower (buffer). For an ideal Op-Amp, \(V_+ = V_-\). The non-inverting input \(V_+\) is connected directly to the input source \(V_{in}\). The inverting input \(V_-\) is connected directly to the output \(V_{out}\). Therefore, \(V_{out} = V_- = V_+ = V_{in}\). The resistor \(R\) and capacitor \(C\) are connected to the output, forming a load. Since the Op-Amp is ideal (with zero output impedance), it can drive any load perfectly. The output voltage \(V_{out}\) is not affected by \(R\) or \(C\) and will always follow \(V_{in}\).

For the Op-Amp circuit shown, the feedback factor \(\beta\) (defined as \(V_f / V_{out}\)) is:

1. \(\frac{R_1}{R_1 + R_F}\)
2. \(\frac{R_F}{R_1 + R_F}\)
3. \(\frac{R_1}{R_F}\)
4. \(1\)

Solution

Solution: This is a non-inverting amplifier configuration. The feedback voltage (\(V_f\)) is the voltage at the inverting terminal (\(V_-\)). The feedback network consists of \(R_F\) and \(R_1\) forming a voltage divider between the output \(V_{out}\) and ground. The voltage \(V_f\) at the node between \(R_1\) and \(R_F\) is given by the voltage divider rule:

The feedback factor \(\beta\) is defined as \(\frac{V_f}{V_{out}}\):

The transfer function \(H(s) = \frac{V_o(s)}{V_i(s)}\) for the circuit shown is:

1. \(\frac{-sRC}{1 + sRC}\)
2. \(\frac{1}{1 + sRC}\)
3. \(\frac{sRC}{1 + sRC}\)
4. \(\frac{-1}{1 + sRC}\)

Solution

The op-amp is in the inverting configuration. The input branch is \(R\) in series with \(C\), and the feedback element is \(R\).

The gain vanishes at \(s = 0\) and tends to \(-1\) as \(s \to \infty\), so this is a first-order high-pass section with corner frequency \(\omega_c = 1/RC\).

In the circuit shown, the input impedance \(Z_{in}(s) = \frac{V_{in}(s)}{I_{in}(s)}\) is:

1. \(R\)
2. \(\frac{1}{sC}\)
3. \(sL\)
4. \(R + sL + \frac{1}{sC}\)

Solution

The op-amp together with \(R_1\), \(R_2\) and \(C\) forms a gyrator. The feedback loop inverts the capacitive branch, so the driving-point impedance seen by the source is proportional to \(s\) rather than to \(1/s\):

The input impedance is zero at dc and rises linearly with frequency, which is the behaviour of an inductance \(L_{eq}\). The circuit therefore looks like \(sL\) at its input terminals.

An 8-bit DAC has a full-scale voltage of \(V_{FS} = 5.12\,V\). The resolution of the DAC is:

1. \(20\,mV\)
2. \(10\,mV\)
3. \(5\,mV\)
4. \(40\,mV\)

Solution

An \(N\)-bit converter divides the full-scale range into \(2^N\) equal steps, so the resolution is the change in output produced by one LSB:

With \(N = 8\) and \(V_{FS} = 5.12\,V\):

The number of comparators required to build a 3-bit flash Analog-to-Digital Converter (ADC) is:

1. 7
2. 8
3. 9
4. 3

Solution

Solution: A flash ADC (or parallel ADC) works by comparing the input voltage to \(2^N - 1\) different reference voltages simultaneously. Each comparison requires one comparator. For an N-bit flash ADC, the number of comparators needed is \(2^N - 1\). Given \(N = 3\) bits:

This requires a resistor divider chain with \(2^N\) (or 8) resistors to create the 7 reference levels.