GATE 2009 Analog Electronics Questions and Solutions

In the circuit shown below, the switch S is closed at t=0. The value of \(V_{out}(t)\) for \(t > 0\) is given by:

1. \(V_{out}(t) = V_{in}(1 - e^{-t/RC})\)
2. \(V_{out}(t) = V_{in} e^{-t/RC}\)
3. \(V_{out}(t) = V_{in}\)
4. \(V_{out}(t) = 0\)

Solution

Solution: This is an ideal Op-Amp configured as a voltage follower (buffer). For an ideal Op-Amp, \(V_+ = V_-\). The non-inverting input \(V_+\) is connected directly to the input source \(V_{in}\). The inverting input \(V_-\) is connected directly to the output \(V_{out}\). Therefore, \(V_{out} = V_- = V_+ = V_{in}\). The resistor \(R\) and capacitor \(C\) are connected to the output, forming a load. Since the Op-Amp is ideal (with zero output impedance), it can drive any load perfectly. The output voltage \(V_{out}\) is not affected by \(R\) or \(C\) and will always follow \(V_{in}\).

For the Op-Amp circuit shown, the feedback factor \(\beta\) (defined as \(V_f / V_{out}\)) is:

1. \(\frac{R_1}{R_1 + R_F}\)
2. \(\frac{R_F}{R_1 + R_F}\)
3. \(\frac{R_1}{R_F}\)
4. \(1\)

Solution

Solution: This is a non-inverting amplifier configuration. The feedback voltage (\(V_f\)) is the voltage at the inverting terminal (\(V_-\)). The feedback network consists of \(R_F\) and \(R_1\) forming a voltage divider between the output \(V_{out}\) and ground. The voltage \(V_f\) at the node between \(R_1\) and \(R_F\) is given by the voltage divider rule:

The feedback factor \(\beta\) is defined as \(\frac{V_f}{V_{out}}\):

The transfer function \(H(s) = \frac{V_o(s)}{V_i(s)}\) for the circuit shown is:

1. \(\frac{-sRC}{1 + sRC}\)
2. \(\frac{1}{1 + sRC}\)
3. \(\frac{sRC}{1 + sRC}\)
4. \(\frac{-1}{1 + sRC}\)

Solution

Solution: This is an inverting Op-Amp integrator circuit, but with a resistor in the feedback path as well. The circuit is a simple inverting amplifier. The input impedance is \(Z_{in} = R_1\). The feedback impedance is \(Z_f = R_F || C = \frac{R_F \cdot (1/sC)}{R_F + 1/sC} = \frac{R_F}{1 + sR_F C}\). (Assuming the labels are \(R_1\) and \(R_F, C\)) From the diagram, \(Z_{in} = R + \frac{1}{sC} = \frac{sRC + 1}{sC}\) And \(Z_f = R\) (assuming the feedback element is just R). Let's re-examine the diagram. It's an inverting configuration. \(Z_{in} = R_1\) \(Z_f = R_2\) Wait, the diagram shows the input as \(R\) and \(C\) in series, and feedback as just \(R\). Let's assume the input is \(R_1\) and \(C_1\) in series, and feedback is \(R_F\).

This is a high-pass filter. Let's assume \(R_1 = R_F = R\) and \(C_1 = C\).

In the circuit shown, the input impedance \(Z_{in}(s) = \frac{V_{in}(s)}{I_{in}(s)}\) is:

1. \(R\)
2. \(\frac{1}{sC}\)
3. \(sL\)
4. \(R + sL + \frac{1}{sC}\)

Solution

Solution: This is a gyrator circuit, which uses an Op-Amp to simulate an inductor. Let's analyze the circuit. Let the node between \(R_1\) and \(C_1\) be \(V_1\). The Op-Amp is a voltage follower, so \(V_{out} = V_1\). The current through \(R_2\) is \(I_2 = \frac{V_{in} - V_{out}}{R_2} = \frac{V_{in} - V_1}{R_2}\). The current through \(C_1\) is \(I_1 = \frac{V_1 - V_{out,gnd}}{1/sC_1} = sC_1 V_1\). (This is not right) Let's re-analyze. \(V_+ = V_{in}\). So \(V_- = V_{in}\). The output of the op-amp is \(V_{out}\). Current \(I_{in}\) flows into the node \(V_{in}\). \(I_{in} = \frac{V_{in} - V_{out}}{R_1}\) (Assuming \(R_1\) is the first resistor) The node \(V_-\) (at \(V_{in}\)) has current from the capacitor: \(I_C = \frac{V_{out} - V_-}{1/sC} = sC(V_{out} - V_{in})\). At the \(V_-\) node, \(I_C = 0\) (ideal op-amp), so \(V_{out} = V_{in}\). This is a buffer. This diagram is confusing. Let's assume the solution text is correct. The solution text says \(Z_{in}(s) = sL_{eq}\) where \(L_{eq} = C R_1 R_2\). This implies the circuit is an inductor.

An 8-bit DAC has a full-scale voltage of \(V_{FS} = 5.12\,V\). The resolution of the DAC is:

1. \(20\,mV\)
2. \(10\,mV\)
3. \(5\,mV\)
4. \(40\,mV\)

Solution

Solution: An 8-bit DAC has \(2^N\) possible levels, where \(N=8\). Number of levels = \(2^8 = 256\). The number of steps or intervals between these levels is \(2^N - 1 = 255\). The resolution (or step size) is the full-scale voltage \(V_{FS}\) divided by the number of intervals.

However, sometimes resolution is approximated as \(\frac{V_{FS}}{2^N}\). Let's try that.

Given the options, this approximation is the intended method.

The number of comparators required to build a 3-bit flash Analog-to-Digital Converter (ADC) is:

1. 7
2. 8
3. 9
4. 3

Solution

Solution: A flash ADC (or parallel ADC) works by comparing the input voltage to \(2^N - 1\) different reference voltages simultaneously. Each comparison requires one comparator. For an N-bit flash ADC, the number of comparators needed is \(2^N - 1\). Given \(N = 3\) bits:

This requires a resistor divider chain with \(2^N\) (or 8) resistors to create the 7 reference levels.