GATE 2008 Analog Electronics Questions and Solutions

In the following transistor circuit \(V_{BE}=0.7\,\mathrm{V}\), \(r_e = 25\,mV/I_E\), and \(\beta\) and all the capacitances are very large. The mid-band voltage gain of the amplifier is approximately:

1. -180
2. -120
3. -90
4. -60

Solution

The mid-band voltage gain is given by:

To find \(r_e\), we first need \(I_E\). Assuming \(I_E \approx 1\,mA\) (calculated in the next question):

In the following transistor circuit \(V_{BE}=0.7\,\mathrm{V}\), \(r_e = 25\,mV/I_E\), and \(\beta\) and all the capacitances are very large. The value of DC current \(I_E\) is:

1. \(1\,mA\)
2. \(2\,mA\)
3. \(5\,mA\)
4. \(10\,mA\)

Solution

To find the DC current \(I_E\), we perform a DC analysis. The capacitors are open circuits. We find the Thevenin equivalent for the base-biasing network (\(20k\Omega\), \(10k\Omega\), and \(9V\)).

Thevenin Voltage (\(V_{Th}\)):

Thevenin Resistance (\(R_{Th}\)):

Apply KVL to the base-emitter loop. Since \(\beta\) is large, \(I_B\) is negligible (\(I_B \approx 0\)).

Consider the Schmidt trigger circuit shown below. A triangular wave which goes from \(-12\,\mathrm{V}\) to \(12\,\mathrm{V}\) is applied to the inverting input of OPAMP. Assume that the output of the OPAMP swings from \(+15\,\mathrm{V}\) to \(-15\,\mathrm{V}\). The voltage at the non-inverting input switches between:

1. \(-12\,\mathrm{V}\) to \(+12\,\mathrm{V}\)
2. \(-7.5\,\mathrm{V}\) to \(7.5\,\mathrm{V}\)
3. \(-5\,\mathrm{V}\) to \(+5\,\mathrm{V}\)
4. \(0\,\mathrm{V}\) and \(5\,\mathrm{V}\)

Solution

This is an inverting Schmitt trigger. The voltage at the non-inverting input (\(V_+\)) sets the trigger points. Based on the circuit configuration (assuming standard feedback resistors), the relationship is derived using KCL at the non-inverting node.

Since \(V_0\) swings from \(-15\,\mathrm{V}\) to \(+15\,\mathrm{V}\):

• Upper Trigger Point (\(V_{UTP}\)) occurs when \(V_0 = +15\,\mathrm{V}\):
  Equation

  \[V_1 = \frac{+15\,\mathrm{V}}{3} = +5\,\mathrm{V}\]
• Lower Trigger Point (\(V_{LTP}\)) occurs when \(V_0 = -15\,\mathrm{V}\):
  Equation

  \[V_1 = \frac{-15\,\mathrm{V}}{3} = -5\,\mathrm{V}\]

The voltage at the non-inverting input switches between \(-5\,\mathrm{V}\) and \(+5\,\mathrm{V}\).

An astable multivibrator circuit using IC 555 timer is shown below. Assume that the circuit is oscillating steadily. The voltage \(V_C\) across the capacitor varies between:

1. \(3\,\mathrm{V}\) to \(5\,\mathrm{V}\)
2. \(3\,\mathrm{V}\) to \(6\,\mathrm{V}\)
3. \(3.6\,\mathrm{V}\) to \(6\,\mathrm{V}\)
4. \(3.6\,\mathrm{V}\) to \(5\,\mathrm{V}\)

Solution

In a standard 555 timer astable configuration, the capacitor voltage \(V_C\) oscillates between the lower and upper threshold voltages. These internal thresholds are set by the 555's internal voltage divider:

• Lower Threshold (Trigger, Pin 2) = \(\frac{1}{3} V_{CC}\)
• Upper Threshold (Threshold, Pin 6) = \(\frac{2}{3} V_{CC}\)

Given \(V_{CC} = 9\,\mathrm{V}\):

The capacitor voltage \(V_C\) varies between \(3\,\mathrm{V}\) and \(6\,\mathrm{V}\).

Two identical NMOS transistors M1 and M2 are connected as shown below. \(V_{bias}\) is chosen so that both transistors are in saturation. The equivalent \(g_m\) of the pair is defined to be \(\frac{\partial I_{out}}{\partial V_i}\) at constant \(V_{out}\). The equivalent \(g_m\) of the pair is:

1. the sum of individual \(g_m\)'s of the transistors
2. the product of individual \(g_m\)'s of the transistors
3. nearly equal to the \(g_m\) of M1
4. nearly equal to \(g_m/g_0\) of M2

Solution

This configuration is a cascode stage (M1) on top of a common-source stage (M2). The input voltage \(V_i\) is the gate voltage of M2 (\(V_{GS2}\)).

Since M1 is in series with M2, \(I_{out} = I_{D1} = I_{D2}\). The definition of the equivalent \(g_m\) is:

By definition, the transconductance of M2 is \(g_{m2} = \frac{\partial I_{D2}}{\partial V_{GS2}}\). Therefore, \(g_m = g_{m2}\). Since M1 and M2 are identical, \(g_{m1} = g_{m2}\). Thus, the equivalent \(g_m\) is nearly equal to the \(g_m\) of M1 (and M2).

The OPAMP circuit shown above represents a:

1. high pass filter
2. low pass filter
3. band pass filter
4. band reject filter

Solution

This is an active inductor circuit. The transfer function \(H(s) = V_o/V_i\) is derived as:

Where \(Z_{in} = R_1 + Ls\) and \(Z_f = R_2 || \frac{1}{Cs}\).

This is a standard second-order low-pass filter transfer function, which has a constant numerator and a second-order polynomial in \(s\) in the denominator.

Consider the following circuit using an ideal OPAMP. The I-V characteristic of the diode is described by the relation \(I = I_0(e^{V/V_T} - 1)\) where \(V_T = 25\,mV\), \(I_0 = 1\,\mu A\) and V is the voltage across the diode (taken as positive for forward bias). For an input voltage \(V_i = -1\,\mathrm{V}\), the output voltage \(V_O\) is:

1. \(0\,\mathrm{V}\)
2. \(0.1\,\mathrm{V}\)
3. \(0.7\,\mathrm{V}\)
4. \(1.1\,\mathrm{V}\)

Solution

1. Since the op-amp is ideal, \(V_{-} = V_{+} = 0\,\mathrm{V}\). 2. The input current \(I_{in}\) is:

3. The feedback current \(I_f\) flows from \(V_o\) to \(V_{-}\). To balance the node, \(I_f = 10\,\mu A\). This current flows through the diode (forward biased). 4. Using the diode equation with \(I_D = I_f = 10\,\mu A\) and \(I_0 = 1\,\mu A\):

5. The output voltage \(V_o\) is the sum of the voltage drop across the \(4k\Omega\) resistor and the diode \(V_D\):

For the circuit shown in the following figure, transistor M1 and M2 are identical NMOS transistors. Assume the M2 is in saturation and the output is unloaded. The current \(I_x\) is related to \(I_{bias}\) as:

1. \(I_x = I_{bias} + I_s\)
2. \(I_x = I_{bias}\)
3. \(I_x = I_{bias} - (V_{DD} - V_{out}) / R_E\)
4. \(I_x = I_{bias} - I_s\)

Solution

This is a standard NMOS current mirror circuit. The current \(I_{bias}\) flows into the drain of M1. M1 is "diode-connected" (\(V_{DS} = V_{GS}\)), ensuring it is in saturation. Since the gate of M2 is connected to the gate of M1, and their sources are both connected to ground, \(V_{GS2} = V_{GS1}\). Because M1 and M2 are identical transistors and have the same \(V_{GS}\), their drain currents must be equal:

In the following limiter circuit, an input voltage \(V_i = 10\sin(100\pi t)\) is applied. Assume that the diode drop is \(0.7\,\mathrm{V}\) when it is forward biased. When it is forward biased, the zener breakdown voltage is \(6.8\,\mathrm{V}\). The maximum and minimum values of the output voltage respectively are:

1. \(6.1\,\mathrm{V}\), \(-0.7\,\mathrm{V}\)
2. \(0.7\,\mathrm{V}\), \(-7.5\,\mathrm{V}\)
3. \(7.5\,\mathrm{V}\), \(-0.7\,\mathrm{V}\)
4. \(7.5\,\mathrm{V}\), \(-7.5\,\mathrm{V}\)

Solution

This circuit clips (limits) the output voltage \(V_o\).

For the positive half of \(V_i\) (\(V_i > 0\)):

• Diode D1 is forward biased.
• Zener diode D2 is reverse biased.
• The output clamps when D1 is on (\(0.7\,\mathrm{V}\) drop) AND D2 is in breakdown (\(6.8\,\mathrm{V}\) drop).
• \(V_{o (max)} = V_{D1(fwd)} + V_{Zener} = 0.7\,\mathrm{V} + 6.8\,\mathrm{V} = 7.5\,\mathrm{V}\).

For the negative half of \(V_i\) (\(V_i < 0\)):

• Diode D1 is reverse biased (open circuit).
• Zener diode D2 is forward biased (acting like a regular diode).
• The output is clamped at the forward voltage drop of D2.
• \(V_{o (min)} = -V_{D2(fwd)} = -0.7\,\mathrm{V}\).

The maximum and minimum values are \(7.5\,\mathrm{V}\) and \(-0.7\,\mathrm{V}\).