Thyristor and SCR Circuits — Solved Problems

About this problem set

Phase control with thyristors: average and rms output of half-wave and single-phase full converters, the firing angle needed for a required DC output, inversion beyond 90 degrees, latching against holding current and the gate pulse width that follows from it, UJT relaxation oscillator design, and dv/dt and di/dt protection with a snubber and series inductor.

Each problem below is solved in full — the given data is listed first, the governing relation is stated, and the arithmetic is carried through to a boxed answer. Work through the statement yourself before opening the solution. The underlying theory is covered in the Electronic Devices lecture series.

PROBLEM 01

Half-Wave SCR Rectifier with Resistive Load

Problem Statement

A single SCR feeds a purely resistive load \(R = 50~\Omega\) from a 230 V rms, 50 Hz single-phase supply. The gate is fired at a delay angle \(\alpha = 60^\circ\) in every positive half cycle; the device blocks throughout the negative half cycle.

Find the average (DC) output voltage and current.
Find the rms output voltage and current.
Find the power delivered to the load, the form factor and the rectification efficiency.
State the peak inverse voltage the SCR must withstand, and compare the DC output with the uncontrolled case \(\alpha = 0\).

Solution

\(V_s = 230~\text{V}\) rms, so \(V_m = \sqrt{2}\,(230) = 325.27~\text{V}\)
\(R = 50~\Omega\), \(f = 50~\text{Hz}\), \(\alpha = 60^\circ = 1.0472~\text{rad}\)
Ideal SCR: zero on-state drop, zero leakage. With a resistive load the current follows the voltage, so conduction runs from \(\alpha\) to \(\pi\) and stops at the natural zero.

Part (a) — average output

Average the half sinusoid over one full period of \(2\pi\), integrating only over the conduction window:

\[\begin{aligned} V_{dc} &= \frac{1}{2\pi}\int_{\alpha}^{\pi} V_m \sin\omega t \; d(\omega t) = \frac{V_m}{2\pi}\bigl[-\cos\omega t\bigr]_{\alpha}^{\pi} = \frac{V_m}{2\pi}(1 + \cos\alpha) \\ &= \frac{325.27}{2\pi}(1 + 0.5000) = 77.65~\text{V} \\ I_{dc} &= \frac{V_{dc}}{R} = \frac{77.65}{50} = 1.553~\text{A} \end{aligned}\]

\(V_{dc} = 77.7~\text{V}\), \(I_{dc} = 1.55~\text{A}\)

Part (b) — rms output

\[\begin{aligned} V_{rms} &= \left[\frac{1}{2\pi}\int_{\alpha}^{\pi} V_m^2 \sin^2\omega t \; d(\omega t)\right]^{1/2} = \frac{V_m}{2}\left[\frac{1}{\pi}\left(\pi - \alpha + \frac{\sin 2\alpha}{2}\right)\right]^{1/2} \\ &= \frac{325.27}{2}\left[\frac{1}{\pi}\left(3.1416 - 1.0472 + \frac{0.8660}{2}\right)\right]^{1/2} \\ &= 162.63 \times 0.8969 = 145.87~\text{V} \\ I_{rms} &= \frac{V_{rms}}{R} = 2.917~\text{A} \end{aligned}\]

\(V_{rms} = 145.9~\text{V}\), \(I_{rms} = 2.92~\text{A}\)

Part (c) — power, form factor, efficiency

Real power in a resistor is set by the rms current, never the average:

\[\begin{aligned} P_L &= I_{rms}^2 R = (2.9175)^2(50) = 425.6~\text{W} \\ \text{FF} &= \frac{V_{rms}}{V_{dc}} = \frac{145.87}{77.65} = 1.879 \\ \eta_r &= \frac{P_{dc}}{P_L} = \frac{V_{dc}^2/R}{I_{rms}^2 R} = \frac{120.60}{425.6} \times 100 = 28.3~\% \end{aligned}\]

\(P_L = 426~\text{W}\), FF \(= 1.88\), \(\eta_r = 28.3~\%\)

Part (d) — device rating and the price of phase control

\[\begin{aligned} \text{PIV} &= V_m = 325.3~\text{V} \\ V_{dc}\big|_{\alpha = 0} &= \frac{V_m}{\pi} = 103.54~\text{V} \\ \frac{V_{dc}(\alpha = 60^\circ)}{V_{dc}(0)} &= \frac{77.65}{103.54} = 0.750 \end{aligned}\]

PIV \( = 325~\text{V}\) (choose a 600 V device); delaying to 60\(^\circ\) cuts the DC output to 75% of its uncontrolled value.

The form factor of 1.88 is the warning: the load carries almost twice as much rms as its average, so conduction losses and heating stay high even though the useful DC output has been cut by more than a quarter. Phase control trades output for very poor waveform quality.

PROBLEM 02

Choosing the Firing Angle for Required Output

Problem Statement

The same half-wave controlled rectifier (230 V rms, 50 Hz, \(R = 50~\Omega\)) must now deliver a specified average output.

Design. Find the firing angle \(\alpha\) that gives \(V_{dc} = 100~\text{V}\).
Express that delay as a time in milliseconds after the supply zero crossing.
Find the load power at this firing angle.
Show that half the maximum average output always corresponds to \(\alpha = 90^\circ\), whatever the supply voltage.

Solution

\(V_m = 325.27~\text{V}\), \(R = 50~\Omega\), \(f = 50~\text{Hz}\)
Target \(V_{dc} = 100~\text{V}\); resistive load, so \(V_{dc} = \dfrac{V_m}{2\pi}(1 + \cos\alpha)\).

Part (a) — invert the transfer relation

\[\begin{aligned} 1 + \cos\alpha &= \frac{2\pi V_{dc}}{V_m} = \frac{2\pi (100)}{325.27} = 1.93169 \\ \cos\alpha &= 0.93169 \\ \alpha &= \cos^{-1}(0.93169) = 21.30^\circ \end{aligned}\]

\(\alpha = 21.3^\circ\)

Part (b) — delay in time

One full cycle is \(1/f = 20~\text{ms}\), i.e. \(360^\circ\):

\[\begin{aligned} t_d &= \frac{\alpha}{360^\circ} \times \frac{1}{f} = \frac{21.30}{360} \times 20~\text{ms} = 1.183~\text{ms} \end{aligned}\]

Fire 1.18 ms after each positive-going zero crossing.

Part (c) — load power at that angle

\[\begin{aligned} V_{rms} &= \frac{V_m}{2}\left[\frac{1}{\pi}\left(\pi - \alpha + \frac{\sin 2\alpha}{2}\right)\right]^{1/2} \qquad (\alpha = 0.37176~\text{rad}) \\ &= 162.63\left[\frac{1}{\pi}\left(2.7698 + 0.3384\right)\right]^{1/2} = 161.77~\text{V} \\ P_L &= \frac{V_{rms}^2}{R} = \frac{(161.77)^2}{50} = 523.4~\text{W} \end{aligned}\]

\(V_{rms} = 162~\text{V}\), \(I_{rms} = 3.24~\text{A}\), \(P_L = 523~\text{W}\)

Part (d) — the 90\(^\circ\) result

The maximum average output is at \(\alpha = 0\):

\[\begin{aligned} V_{dc(\max)} &= \frac{V_m}{2\pi}(1 + 1) = \frac{V_m}{\pi} = 103.54~\text{V} \\ \tfrac{1}{2}V_{dc(\max)} &= \frac{V_m}{2\pi} \;\Rightarrow\; 1 + \cos\alpha = 1 \;\Rightarrow\; \cos\alpha = 0 \;\Rightarrow\; \alpha = 90^\circ \end{aligned}\]

\(V_m\) cancels, so the result is independent of the supply. Numerically \(V_{dc}(90^\circ) = 51.77~\text{V} = \tfrac{1}{2}(103.54)\).

\(\alpha = 90^\circ\) always halves the average output; here that is 51.8 V.

The control sensitivity is \(\mathrm{d}V_{dc}/\mathrm{d}\alpha = -V_m\sin\alpha/2\pi\), which vanishes at \(\alpha = 0\) and peaks at \(90^\circ\): here it is 0.328 V per degree at \(\alpha = 21.3^\circ\) against 0.904 V per degree at \(90^\circ\). Small firing angles buy very little control, which is why practical phase controllers are set up to work near the middle of the range.

PROBLEM 03

Single-Phase Full Converter with Inductive Load

Problem Statement

A single-phase full converter (four SCRs in a bridge) is fed from 230 V rms, 50 Hz. The load is highly inductive, so the load current is continuous and essentially constant at \(I_d = 20~\text{A}\).

Find the average output voltage and the power delivered at \(\alpha = 30^\circ\).
Find the rms and fundamental rms values of the supply current, and hence the input power factor.
Find the average output voltage at \(\alpha = 120^\circ\) and explain what the circuit is now doing.
State what the load must contain for that mode to be possible.

Solution

\(V_s = 230~\text{V}\) rms, \(V_m = 325.27~\text{V}\), \(I_d = 20~\text{A}\) constant
Continuous conduction: each pair of SCRs conducts for exactly \(\pi\) radians, so the output voltage follows the supply for a full half cycle starting at \(\alpha\).
Ideal devices, ripple-free load current.

Part (a) — average output and power

\[\begin{aligned} V_{dc} &= \frac{1}{\pi}\int_{\alpha}^{\alpha + \pi} V_m \sin\omega t \; d(\omega t) = \frac{2V_m}{\pi}\cos\alpha \\ &= \frac{2(325.27)}{\pi}\cos 30^\circ = (207.07)(0.8660) = 179.33~\text{V} \\ P_{dc} &= V_{dc} I_d = (179.33)(20) = 3587~\text{W} \end{aligned}\]

\(V_{dc} = 179.3~\text{V}\), \(P_{dc} = 3.59~\text{kW}\)

Part (b) — supply current and power factor

The supply current is a square wave of amplitude \(I_d\), delayed by \(\alpha\) with respect to the supply voltage:

\[\begin{aligned} I_s &= I_d = 20.0~\text{A (rms, square wave)} \\ I_{s1} &= \frac{4 I_d}{\sqrt{2}\,\pi} = \frac{4(20)}{\sqrt{2}\,\pi} = 18.006~\text{A} \\ \text{distortion factor} &= \frac{I_{s1}}{I_s} = 0.9003, \qquad \text{displacement factor} = \cos\alpha = 0.8660 \\ \text{PF} &= \frac{I_{s1}}{I_s}\cos\alpha = (0.9003)(0.8660) = 0.7797~\text{lagging} \end{aligned}\]

\(I_s = 20~\text{A}\), \(I_{s1} = 18.0~\text{A}\), PF \( = 0.780\) lagging.

Part (c) — \(\alpha = 120^\circ\)

\[\begin{aligned} V_{dc} &= (207.07)\cos 120^\circ = (207.07)(-0.5000) = -103.54~\text{V} \\ P_{dc} &= V_{dc} I_d = (-103.54)(20) = -2071~\text{W} \end{aligned}\]

\(\cos\alpha\) has changed sign, so \(V_{dc}\) is negative while \(I_d\) — set by the direction the SCRs can conduct — is still positive. The product is negative: 2.07 kW now flows from the DC side into the AC supply. The converter is operating as a line-commutated inverter.

\(V_{dc} = -103.5~\text{V}\); the converter has entered the inversion mode, returning 2.07 kW to the mains.

Part (d) — what the load must contain

An SCR bridge cannot reverse its current, so power reversal has to come from a voltage reversal. The load must therefore contain an active source able to hold the DC terminal negative — a separately excited DC machine acting as a generator, or a battery — with the inductance keeping the current continuous. A passive R–L load can never drive the converter into inversion.

\[V_{rms(\text{output})} = V_s = 230~\text{V} \quad \text{(independent of } \alpha \text{ in continuous conduction)}\]

Inversion requires a DC-side EMF (regenerating machine or battery) plus enough inductance for continuous conduction.

The rms output voltage stays at 230 V for every \(\alpha\) — only the average is controlled. That is why the ripple, and therefore the inductance needed for smooth current, is worst near \(\alpha = 90^\circ\) where the average is zero but the rms is undiminished.

PROBLEM 04

Latching Current and Gate Pulse Width

Problem Statement

An SCR with latching current \(I_L = 40~\text{mA}\) and holding current \(I_H = 12~\text{mA}\) switches a series R–L load across a \(100~\text{V}\) DC supply, with \(R = 20~\Omega\) and \(L = 0.5~\text{H}\).

Find the minimum gate pulse width that will leave the SCR latched.
A 100 \(\mu\)s gate pulse is tried instead. Show what happens.
Design. Choose a gate pulse width with sensible margin and state the current reached at the end of it.
Once conducting, the load resistance is switched. Find the largest resistance that keeps the SCR on, and test \(R = 5~\text{k}\Omega\) and \(R = 10~\text{k}\Omega\).

Solution

\(V = 100~\text{V}\) DC, \(R = 20~\Omega\), \(L = 0.5~\text{H}\), so \(\tau = L/R = 25.0~\text{ms}\) and \(I_{\text{final}} = V/R = 5~\text{A}\)
\(I_L = 40~\text{mA}\) (to latch on), \(I_H = 12~\text{mA}\) (to stay on)
Ideal SCR with zero on-state drop; the anode current rises from zero at the instant of firing.

Part (a) — time to reach the latching current

The inductance stops the current appearing instantly. With the SCR turned on,

\[\begin{aligned} i(t) &= \frac{V}{R}\left(1 - e^{-t/\tau}\right) = 5\left(1 - e^{-t/25\,\text{ms}}\right) \\ I_L &= \frac{V}{R}\left(1 - e^{-t/\tau}\right) \;\Rightarrow\; t = -\tau \ln\left(1 - \frac{I_L R}{V}\right) \\ &= -(25.0~\text{ms})\ln\left(1 - \frac{(0.040)(20)}{100}\right) = -(25.0)\ln(0.99200) \\ &= 200.8~\mu\text{s} \end{aligned}\]

The gate pulse must last at least \(201~\mu\text{s}\).

Part (b) — a 100 \(\mu\)s pulse

\[\begin{aligned} i(100~\mu\text{s}) &= 5\left(1 - e^{-0.0040}\right) = 5(0.003992) = 19.96~\text{mA} \end{aligned}\]

That is well below \(I_L = 40~\text{mA}\). When the gate drive is removed the regenerative action has not yet taken hold, so the device reverts to the forward blocking state and the load current collapses.

Only 20.0 mA is reached — the SCR fails to latch and turns off when the pulse ends.

Part (c) — design of the gate pulse

Take roughly 50% margin over the 201 \(\mu\)s minimum to cover device spread and the tolerance on \(L\); choose \(t_g = 300~\mu\text{s}\):

\[\begin{aligned} i(300~\mu\text{s}) &= 5\left(1 - e^{-0.0120}\right) = 59.64~\text{mA} \;>\; I_L = 40~\text{mA} \quad \checkmark \end{aligned}\]

Use \(t_g = 300~\mu\text{s}\), which reaches 60 mA — 1.5 times the latching current.

In practice a train of narrow pulses over that interval is preferred to one long pulse: it delivers the same effective drive duration while keeping the average gate dissipation low.

Part (d) — holding current after the load changes

\[\begin{aligned} R_{\max} &= \frac{V}{I_H} = \frac{100~\text{V}}{12~\text{mA}} = 8.333~\text{k}\Omega \\ R = 5~\text{k}\Omega: \quad I &= \frac{100}{5~\text{k}\Omega} = 20.0~\text{mA} > I_H \quad \text{stays on} \\ R = 10~\text{k}\Omega: \quad I &= \frac{100}{10~\text{k}\Omega} = 10.0~\text{mA} < I_H \quad \text{turns off} \end{aligned}\]

The SCR stays latched for any load resistance below \(8.33~\text{k}\Omega\): it conducts at 5 k\(\Omega\) (20 mA) and commutates off at 10 k\(\Omega\) (10 mA).

Note the two currents are different quantities: \(I_L = 40~\text{mA}\) is the current needed to establish conduction and \(I_H = 12~\text{mA}\) is the smaller current needed to maintain it — typically \(I_L \approx 3.3 I_H\), because once the internal regeneration is fully established it sustains itself on less current.

PROBLEM 05

UJT Relaxation Oscillator Trigger Design

Problem Statement

A UJT relaxation oscillator generates the gate pulses for an SCR. The unijunction has an intrinsic stand-off ratio \(\eta = 0.63\), interbase resistance \(R_{BB} = 7~\text{k}\Omega\), peak-point current \(I_P = 25~\mu\text{A}\), valley point \((V_V, I_V) = (1.5~\text{V}, 6~\text{mA})\), and the emitter diode drops \(V_D = 0.7~\text{V}\). It runs from \(V_{BB} = 20~\text{V}\), with a timing resistor \(R\) charging a capacitor \(C\) on the emitter.

Find the peak-point (firing) voltage \(V_P\).
Find the oscillation frequency for \(R = 50~\text{k}\Omega\), \(C = 0.1~\mu\text{F}\).
Design. Choose \(R\) for a triggering frequency of 500 Hz with \(C = 0.1~\mu\text{F}\), and verify that it lies inside the permitted range of \(R\).
Choose \(R_{B2}\) for temperature compensation and \(R_{B1}\) for the output pulse, and estimate the standing DC level at \(B_1\) and the width of the trigger pulse.

Solution

\(\eta = 0.63\), \(V_{BB} = 20~\text{V}\), \(V_D = 0.7~\text{V}\), \(R_{BB} = 7~\text{k}\Omega\)
\(I_P = 25~\mu\text{A}\), \((V_V, I_V) = (1.5~\text{V}, 6~\text{mA})\)
The capacitor charges through \(R\) towards \(V_{BB}\) and dumps almost instantaneously through the emitter into \(R_{B1}\) once \(V_P\) is reached; the discharge time is neglected.

Part (a) — peak-point voltage

The interbase divider holds the emitter junction reverse biased at \(\eta V_{BB}\); the emitter must climb one diode drop above that before the junction conducts:

\[V_P = \eta V_{BB} + V_D = (0.63)(20) + 0.7 = 12.6 + 0.7 = 13.30~\text{V}\]

\(V_P = 13.3~\text{V}\)

Part (b) — period and frequency

The capacitor rises exponentially from (essentially) zero towards \(V_{BB}\); set that equal to \(V_P \approx \eta V_{BB}\) at \(t = T\):

\[\begin{aligned} V_{BB}\left(1 - e^{-T/RC}\right) &= \eta V_{BB} \;\Rightarrow\; T = RC \ln\!\left(\frac{1}{1 - \eta}\right) \\ \ln\!\left(\frac{1}{1 - 0.63}\right) &= \ln\!\left(\frac{1}{0.37}\right) = 0.99425 \\ T &= (50~\text{k}\Omega)(0.1~\mu\text{F})(0.99425) = 4.9713~\text{ms} \\ f &= \frac{1}{T} = 201.2~\text{Hz} \end{aligned}\]

\(T = 4.97~\text{ms}\), \(f = 201~\text{Hz}\)

Part (c) — design for 500 Hz

\[\begin{aligned} T &= \frac{1}{f} = \frac{1}{500} = 2.0~\text{ms} \\ R &= \frac{T}{C \ln[1/(1-\eta)]} = \frac{2.0\times 10^{-3}}{(1.0e-07)(0.99425)} = 20.116~\text{k}\Omega \;\Rightarrow\; R = 20~\text{k}\Omega \end{aligned}\]

Now check the two limits on \(R\). It must be small enough that the charging current can still supply \(I_P\) at the peak point (otherwise the UJT never fires), and large enough that the current at the valley point is below \(I_V\) (otherwise the device latches on and never resets):

\[\begin{aligned} R_{\max} &= \frac{V_{BB} - V_P}{I_P} = \frac{20 - 13.30}{25~\mu\text{A}} = 268.0~\text{k}\Omega \\ R_{\min} &= \frac{V_{BB} - V_V}{I_V} = \frac{20 - 1.5}{6~\text{mA}} = 3.083~\text{k}\Omega \\ 3.08~\text{k}\Omega &< 20~\text{k}\Omega < 268~\text{k}\Omega \quad \checkmark \end{aligned}\]

With the standard 20 k\(\Omega\) value:

\[f = \frac{1}{(20~\text{k}\Omega)(0.1~\mu\text{F})(0.99425)} = 502.9~\text{Hz}\]

\(R = 20~\text{k}\Omega\) with \(C = 0.1~\mu\text{F}\) gives 503 Hz, an error of \(+0.6~\%\), and sits well inside 3.08–268 k\(\Omega\).

Part (d) — the base resistors and the output pulse

\(R_{B2}\) compensates the drift of \(V_P\) with temperature; the standard value is

\[\begin{aligned} R_{B2} &= \frac{10^4}{\eta V_{BB}} = \frac{10^4}{(0.63)(20)} = 793.7~\Omega \;\Rightarrow\; R_{B2} = 820~\Omega \\ V_{B1(\text{dc})} &= V_{BB}\frac{R_{B1}}{R_{B1} + R_{BB} + R_{B2}} = 20\frac{100}{7920} = 0.253~\text{V} \\ t_{\text{pulse}} &\approx R_{B1} C = (100~\Omega)(0.1~\mu\text{F}) = 10~\mu\text{s} \end{aligned}\]

\(R_{B2} = 820~\Omega\), \(R_{B1} = 100~\Omega\); standing level at \(B_1\) is 0.25 V and the trigger spike is about 10 \(\mu\)s wide.

\(R_{B1}\) sets both the amplitude and the width of the spike: too small and the SCR gate sees too little drive, too large and the standing DC level starts to bias the gate permanently. The 10 \(\mu\)s width is comfortably longer than the turn-on time of a small SCR but far shorter than the period, so gate dissipation is negligible.

PROBLEM 06

Snubber Design for dv/dt and di/dt

Problem Statement

An SCR switches a \(10~\Omega\) resistive load across a \(400~\text{V}\) DC rail at 50 Hz. The device is rated at \(\mathrm{d}v/\mathrm{d}t = 50~\text{V}/\mu\text{s}\) and \(\mathrm{d}i/\mathrm{d}t = 50~\text{A}/\mu\text{s}\). Protection is a series inductor \(L_s\) and an \(R_s\)–\(C_s\) snubber connected across the SCR.

Find the minimum series inductance, choose a value, and state the \(\mathrm{d}i/\mathrm{d}t\) achieved.
Design. With \(C_s = 0.1~\mu\text{F}\), choose \(R_s\) so the re-applied \(\mathrm{d}v/\mathrm{d}t\) stays within the rating, using \(\mathrm{d}v/\mathrm{d}t = 0.632\,V/(R_s C_s)\). State the value achieved.
Find the capacitor discharge current when the SCR fires and the resulting peak device current.
Find the power rating needed for \(R_s\), and comment on the damping the chosen values give.

Solution

\(V = 400~\text{V}\) DC, \(R_L = 10~\Omega\), switching at 50 Hz
Ratings: \(\mathrm{d}v/\mathrm{d}t \le 50~\text{V}/\mu\text{s}\), \(\mathrm{d}i/\mathrm{d}t \le 50~\text{A}/\mu\text{s}\)
Steady load current \(I_L = V/R_L = 40~\text{A}\); the snubber capacitor is fully charged to \(V\) before the device fires.

Part (a) — series inductor for \(\mathrm{d}i/\mathrm{d}t\)

At the instant of turn-on the whole supply voltage appears across \(L_s\), since the SCR drop and the load drop are both still nearly zero:

\[\begin{aligned} \left.\frac{\mathrm{d}i}{\mathrm{d}t}\right|_{\max} &= \frac{V}{L_s} \;\Rightarrow\; L_s \ge \frac{V}{(\mathrm{d}i/\mathrm{d}t)_{\text{rated}}} = \frac{400~\text{V}}{50~\text{A}/\mu\text{s}} = 8.0~\mu\text{H} \\ \text{choose } L_s &= 10~\mu\text{H} \;\Rightarrow\; \frac{\mathrm{d}i}{\mathrm{d}t} = \frac{400}{10~\mu\text{H}} = 40~\text{A}/\mu\text{s} \end{aligned}\]

\(L_s = 10~\mu\text{H}\) (minimum 8 \(\mu\)H) gives 40 A/\(\mu\)s, 1.25 times inside the rating.

Part (b) — snubber for \(\mathrm{d}v/\mathrm{d}t\)

When the SCR turns off, the voltage across it recovers through \(R_s C_s\). Taking the initial rate as the exponential rise reaching 63.2% in one time constant:

\[\begin{aligned} \frac{\mathrm{d}v}{\mathrm{d}t} &= \frac{0.632\,V}{R_s C_s} \;\Rightarrow\; R_s C_s \ge \frac{0.632\,V}{(\mathrm{d}v/\mathrm{d}t)_{\text{rated}}} = \frac{(0.632)(400)}{50\times 10^{6}} = 5.056~\mu\text{s} \\ R_s &\ge \frac{5.056~\mu\text{s}}{0.1~\mu\text{F}} = 50.56~\Omega \;\Rightarrow\; R_s = 56~\Omega\ \text{(E24)} \\ \frac{\mathrm{d}v}{\mathrm{d}t} &= \frac{(0.632)(400)}{(56)(0.1~\mu\text{F})} = \frac{252.8}{5.6~\mu\text{s}} = 45.14~\text{V}/\mu\text{s} \end{aligned}\]

\(R_s = 56~\Omega\), \(C_s = 0.1~\mu\text{F}\), giving \(\mathrm{d}v/\mathrm{d}t = 45.1~\text{V}/\mu\text{s}\), inside the 50 V/\(\mu\)s rating.

Part (c) — discharge current at turn-on

\(C_s\) is charged to the full rail while the SCR blocks. At firing it dumps through \(R_s\) and the device, adding to the load current:

\[\begin{aligned} I_{\text{dis}} &= \frac{V}{R_s} = \frac{400}{56} = 7.143~\text{A} \\ I_{T(\text{pk})} &= I_L + I_{\text{dis}} = 40 + 7.14 = 47.14~\text{A} \end{aligned}\]

\(I_{\text{dis}} = 7.1~\text{A}\), so the SCR sees a peak of 47.1 A at turn-on instead of 40 A.

Part (d) — resistor rating and damping

Each switching cycle charges and then discharges \(C_s\); both halves dissipate \(\tfrac{1}{2}C_sV^2\) in \(R_s\), so the cycle total is \(C_sV^2\):

\[\begin{aligned} P_{R_s} &= f C_s V^2 = (50)(1.0e-07)(400)^2 = 0.800~\text{W} \\ \zeta &= \frac{R_s}{2}\sqrt{\frac{C_s}{L_s}} = \frac{56}{2}\sqrt{\frac{0.1~\mu\text{F}}{10~\mu\text{H}}} = (28)(0.1000) = 2.80 \end{aligned}\]

\(P_{R_s} = 0.80~\text{W}\) — use a 2 W non-inductive resistor; \(\zeta = 2.8\), so the \(L_s\)–\(C_s\)–\(R_s\) loop is heavily overdamped.

Sizing \(R_s\) from the \(\mathrm{d}v/\mathrm{d}t\) requirement has forced \(\zeta \gg 1\), so there is no voltage overshoot at turn-off — but the same large \(R_s\) is what keeps the turn-on discharge spike down to 7.1 A. Shrinking \(R_s\) towards the usual \(\zeta \approx 0.5\) would improve the damping figure while violating the \(\mathrm{d}v/\mathrm{d}t\) limit and multiplying the discharge current; here the rating, not the damping, is the binding constraint.