By the end of this chapter you should be able to:
- Compute the overall gain of a cascade as a product and as a sum in decibels, and account for the loading of each stage by the next.
- Compare RC, direct and transformer coupling, and choose between them for a given signal band and load.
- Analyse the Darlington pair: composite \(\beta\), input resistance, the doubled \(V_{BE}\) and the multiplied leakage current.
- Explain why the cascode has the gain of a common-emitter stage and the bandwidth of a common-base stage.
- Locate every low-frequency break by finding the resistance each capacitor works into, and identify the dominant one.
- Derive the Miller capacitances \(C_f(1+|A_v|)\) and \(C_f(1+1/|A_v|)\) and use them to find the high-frequency poles.
- Relate \(f_\beta\), \(f_T\) and the gain–bandwidth product, and compute the bandwidth of \(n\) identical cascaded stages.
Every amplifier so far in this course has had one transistor in it, and every one of them has had a gain that was fixed by the moment you chose \(R_C\) and \(I_E\). Two things are wrong with that. The first is that one stage rarely gives enough gain: a moving-coil microphone delivers about 2 mV, a loudspeaker wants several volts, and the factor of a few thousand between them is beyond what a single common-emitter stage will deliver with any margin for the tolerances of Chapter 18. The second is that the mid-band gain we have been computing is a fiction outside a band of frequencies we never bothered to identify. Every capacitor in Figure 19.1 was declared a short circuit, and every capacitance inside the transistor was ignored altogether. Neither assumption holds everywhere.
This chapter removes both simplifications. It first asks what happens when stages are put in series — how the gains combine, why decibels make the bookkeeping easier, and why the answer is always smaller than the product of the datasheet gains because each stage loads the one before it. It then examines two composite arrangements, the Darlington pair and the cascode, which exist because a cascade can be built for something other than raw gain. Finally it works out the frequency response from both ends: the low-frequency roll-off caused by the coupling and bypass capacitors we deliberately put in, and the high-frequency roll-off caused by the capacitances the transistor has whether we want them or not. The Miller effect ties the two halves of the chapter together, because it is the reason a cascode exists at all.
1 Why Cascade, and What Cascading Costs
Put two amplifiers in series and the output of the first becomes the input of the second, so the voltage gains multiply:
A product of \(n\) numbers, each of which may be negative. Two inverting stages give a non-inverting cascade, three give an inverting one, and the phase of the output alternates with the number of stages — a fact worth remembering before wrapping feedback round the whole chain.
Products are awkward to think about, and the decibel converts the product into a sum. For a voltage ratio,
The factor is 20 rather than 10 because the decibel is defined on power, and power goes as the square of voltage into a fixed resistance. A voltage ratio of \(\sqrt{2}\) is 3.01 dB, which is why the half-power points of any response are the points where the voltage has fallen to \(1/\sqrt{2}\) of mid-band. Gain of 10 is 20 dB, 100 is 40 dB, 1000 is 60 dB — each extra factor of ten is another 20 dB.
Loading is the catch. The gain of a stage is \(-R_L'/r_e\), and \(R_L'\) is whatever the collector sees, which now includes the input impedance of the next stage. Chapter 19 found that a common-emitter stage has \(Z_i = 1036\ \Omega\) — low, because \((1+\beta)r_e\) is only 1294 Ω. Putting that in parallel with the 2 kΩ collector resistor is a serious loss.
Cascade two copies of the Chapter 19 amplifier: \(\beta = 100\), \(I_E = 2.029\) mA, \(r_e = 12.81\ \Omega\), \(r_\pi = 1294\ \Omega\), \(r_o = 49.78\ \text{k}\Omega\), \(R_1 = 22\) kΩ, \(R_2 = 6.8\) kΩ, \(R_C = 2\) kΩ. The second stage drives a 10 kΩ load; the source has \(R_s = 600\ \Omega\).
Second stage first, because nothing loads it except \(R_L\):
First stage. Its load is \(R_C\) in parallel with \(r_o\) and with the input impedance of stage 2, which is \(Z_{i2} = R_1\|R_2\|r_\pi = 5194\|1294 = 1036\ \Omega\):
Overall. \(A_v = (-52.54)(-125.85) = +6612\), non-inverting, which in decibels is \(34.41 + 42.00 = 76.41\) dB. Including the input divider formed by \(R_s\) and \(Z_{i1} = 1036\ \Omega\), \(A_{vs} = 6612 \times 1036/1636 = 4187\), or 72.44 dB.
What the loading cost. Had stage 1 been able to drive stage 2 without loading — if stage 2 had an infinite input impedance — stage 1 would have given \(-125.85\) as well, and the cascade would have given 15 838, or 84.0 dB. The 1036 Ω input of stage 2 has therefore thrown away 7.59 dB, a factor of 2.4 in voltage. That is not a defect of the arithmetic; it is a design fact, and it is the standing argument for putting an emitter follower or a high-impedance FET stage between two voltage amplifiers.
Three conclusions follow, and all three are used later. Only the last stage of a cascade sees the real load, so only the last stage's gain can be computed from the datasheet without asking what comes after it. Every earlier stage is loaded by the input impedance of its successor and must be computed from the output end backwards. And the input impedance of the cascade is the input impedance of the first stage alone, while the output impedance is that of the last stage alone — the middle of the chain is invisible from either end.
2 Coupling One Stage to the Next
Cascading is not simply a matter of joining two collectors to two bases. The collector of the first stage in Figure 25.2 sits at 6.0 V d.c.; the base of the second wants to sit at 2.7 V. Wire them together and the second transistor saturates, the first loses its load line, and both bias designs collapse. Something must pass the signal and block the d.c. difference, and the three ways of doing it are the three coupling methods.
RC coupling uses a series capacitor, as in Figure 25.2. It is by far the commonest arrangement because it is cheap, small, and completely isolates the two bias networks: each stage can be designed on its own, exactly as in Chapter 18, and then joined. The price is that the capacitor and the resistances on either side of it form a high-pass filter, so the response falls away at low frequency — Section 5 works out where. An electrolytic coupling capacitor also leaks a few microamps, which is why its polarity must be right.
Direct coupling connects the collector of one stage straight to the base of the next and lets the two bias designs interact deliberately. Since there is no capacitor, the response extends all the way to d.c. — the lower cut-off frequency is zero — which is essential for amplifying a thermocouple output, a strain-gauge bridge or any other slowly varying quantity. Two costs follow. Levels must be planned across the whole chain, because each collector's quiescent voltage becomes the next base's, so a designer runs out of supply rail after two or three stages unless PNP and NPN stages are alternated. And any drift in the first stage — a change in \(V_{BE}\) of 2 mV per degree, say — is amplified by every stage that follows it and is indistinguishable at the output from a real signal. That single fact drove the development of the differential pair, which Chapter 26 uses as the input stage of every operational amplifier.
Transformer coupling uses the mutual inductance of two windings. It blocks d.c. perfectly, and it can transform impedance as well: a transformer of turns ratio \(n:1\) makes a load \(R_L\) appear as \(n^2R_L\) at the primary.
A 15.81:1 transformer makes an 8 Ω loudspeaker look like the 2 kΩ that the collector of our stage wants to work into. Nothing else can do that without losing power, which is why transformer coupling survived so long in output stages and in radio-frequency tuned amplifiers, where the transformer's leakage inductance is deliberately resonated to give a band-pass response.
It has largely disappeared because a transformer is heavy, expensive, and restricted at both ends of the band by its winding capacitance and leakage inductance. Chapter 20's complementary-symmetry output stage does the same impedance-transforming job with two transistors and no iron.
| Coupling | Lower cut-off | D.C. isolation | Impedance transformation | Typical use |
|---|---|---|---|---|
| RC | set by \(C\) and the resistance it sees — 23 Hz here | complete | none | audio and general-purpose voltage amplifiers |
| Direct | zero — response extends to d.c. | none; levels interact | none | instrumentation, op-amps, integrated circuits |
| Transformer | set by primary inductance | complete, and galvanic | \(n^2\); 15.81:1 turns 8 Ω into 2 kΩ | power output stages, tuned RF amplifiers |
3 Two Composites: The Darlington Pair and the Cascode
Not every cascade is built for voltage gain. Two arrangements of two transistors are used so often that they are treated as single devices, and each answers a limitation that one transistor cannot escape.
The Darlington pair. Connect the emitter of \(Q_1\) to the base of \(Q_2\) and tie the two collectors together. The emitter current of \(Q_1\) is the base current of \(Q_2\), so
With \(\beta_1 = \beta_2 = 100\), \(\beta_D = 10\,000 + 100 + 100 = 10\,200\), or 80.17 dB of current gain from two ordinary transistors.
The consequence that matters is the input resistance. Reflecting the emitter load up through both devices in turn, with \(I_{E2} = 2\) mA so that \(r_{e2} = 13.0\ \Omega\) and \(I_{E1} = 2/101 = 19.8\ \mu\)A so that \(r_{e1} = 26/0.0198 = 1313\ \Omega\), and with \(R_E' = R_E\|R_L = 1000\|1000 = 500\ \Omega\):
Against 51.8 kΩ for a single transistor in the same circuit, that is a factor of 104. The follower gain is \(A_v = R_E'/(R_E' + r_{e2} + r_{e1}/(1+\beta_2)) = 500/526.0 = 0.951\), and the output impedance falls to \(R_E\|[r_{e2} + (r_{e1}+R_s'/(1+\beta_1))/(1+\beta_2)] = 25.4\ \Omega\). A Darlington emitter follower is the standard way to drive a heavy load from a source that can supply almost no current.
The base-emitter drop doubles. Two junctions are now in series between base and emitter, so \(V_{BE(\text{on})} \approx 1.4\) V rather than 0.7 V, and every bias calculation must use the doubled figure. A voltage-divider design that assumed 0.7 V will place the Q-point 0.7 V too high on the base and put the pair much closer to saturation than intended.
Leakage is multiplied. The collector-base leakage \(I_{CBO}\) of \(Q_1\) appears in the base of \(Q_2\) and is amplified by \(\beta_2\). A 10 nA leakage at the first base becomes \((1+\beta_2)(10\ \text{nA}) = 1.01\ \mu\)A of collector current, and since \(I_{CBO}\) roughly doubles for every 10 °C, a Darlington is markedly less stable with temperature than a single device. Integrated Darlingtons include a resistor of a few kilohms from the base of \(Q_2\) to the common emitter precisely to bleed this leakage away before \(Q_2\) can amplify it.
Saturation is poor. \(Q_2\) cannot saturate below \(V_{CE(\text{sat}),1} + V_{BE,2} \approx 0.9\) V, because \(Q_1\)’s collector is tied to \(Q_2\)’s collector. As a switch a Darlington therefore dissipates several times as much as a single transistor, which is why power MOSFETs displaced Darlingtons in switching applications.
The cascode. The second composite exists for bandwidth. Section 6 shows that the collector-base capacitance of a common-emitter stage is multiplied at its input by \((1+|A_v|)\), so a gain of 126 turns 4 pF into 507 pF and wrecks the high-frequency response. The common-base stage of Chapter 19 does not suffer from this at all, because its base is grounded and there is no voltage swing across the feedback capacitance — but its input impedance is only \(r_e\), a dozen ohms, so nothing can drive it.
The cascode stacks one on the other. A common-emitter transistor \(Q_1\) takes the signal at its base, and its collector is loaded not by \(R_C\) but by the emitter of a common-base transistor \(Q_2\) sitting above it, whose base is held at a fixed voltage and decoupled to ground. The load \(Q_1\) sees is therefore \(r_{e2}\), a dozen ohms, so
The overall gain is the product, \(-125.85\) — exactly that of the single common-emitter stage, since \(r_{e2}\) cancels. Nothing has been lost.
What has changed is the Miller multiplication at the input of \(Q_1\), which is now \((1+1.00) = 2\) instead of \((1+125.85) = 126.85\). The input capacitance falls from 549 pF to 50 pF and the input pole moves from 762 kHz to 8.38 MHz, a factor of 11. That is the whole point of the cascode, and it is why it appears in the front end of every wideband amplifier and in the gain stage of most integrated op-amps.
4 The Three Frequency Regions
Plot the gain of a coupled amplifier against frequency on logarithmic axes and it divides cleanly into three regions, each governed by different components and each with its own asymptotic behaviour.
- The low-frequency region. The external capacitors — coupling and bypass — have appreciable reactance. Each forms a high-pass network with the resistance it works into, so the gain falls as frequency falls, at 20 dB per decade for each capacitor that has come into play. Internal capacitances are irrelevant here, being far too small to matter at 20 Hz.
- The mid-band. The external capacitors are short circuits and the internal ones are open circuits. This is where every calculation of Chapter 19 applies, and it is the only region in which the gain is a real constant. Its width is the number a designer usually cares about.
- The high-frequency region. The internal capacitances \(C_\pi\) and \(C_\mu\), plus the stray capacitance of the wiring and the input capacitance of whatever follows, shunt the signal to ground. Each forms a low-pass network, so the gain falls as frequency rises, again at 20 dB per decade per pole. The external capacitors are irrelevant here, being perfect short circuits.
The bandwidth is defined between the two frequencies at which the gain has fallen to \(1/\sqrt{2}\) of its mid-band value, that is by 3.01 dB, and where the power delivered to a fixed load has therefore halved:
For the stage analysed below, \(f_L = 23.2\) Hz and \(f_H = 754\) kHz, so the bandwidth is 753 977 Hz and quoting it as 754 kHz loses nothing. The approximation fails only for deliberately narrow-band amplifiers, such as the tuned RF stages a transformer-coupled design produces.
The Bode magnitude plot is the tool for all of this. It draws \(20\log_{10}|A_v|\) against \(\log_{10} f\) and replaces each first-order factor by two straight lines: horizontal below the break frequency, sloping at \(\pm 20\) dB per decade above or below it. The true curve is 3 dB from the corner of the asymptotes at the break itself and 1 dB away an octave either side, so the construction is accurate enough to design with. Where several breaks are well separated, the one furthest right on the low side and furthest left on the high side dominates.
Read the figure from the middle outwards. The mid-band sits at 42.00 dB. Going down in frequency, the bypass capacitor breaks first at 19.0 Hz and the slope becomes 20 dB per decade; the input coupling capacitor adds a second break at 9.7 Hz, making the slope 40 dB per decade; the output coupling capacitor adds a third at 2.8 Hz, making it 60. Going up in frequency, the Miller-loaded input node breaks at 754 kHz and the output node at 8.2 MHz. Because the three low-frequency breaks are not widely separated, the true \(-3\) dB point at 23.2 Hz sits above the dominant break at 19.0 Hz.
5 Low-Frequency Response: Coupling and Bypass Capacitors
Each capacitor in the circuit, taken by itself with the others treated as short circuits, forms a single high-pass section. The break frequency is where the capacitor's reactance equals the total resistance in series with it round the loop it sits in:
The whole of the low-frequency analysis is the identification of \(R_{\text{eq}}\) for each capacitor. Getting the resistance right is the entire difficulty; the formula never changes.
The input coupling capacitor \(C_1\). It sits between the source and the base, so the resistance in its loop is the source resistance plus the amplifier's input impedance:
The output coupling capacitor \(C_2\). It sits between the collector and the load. Looking left it sees \(R_C\) in parallel with \(r_o\), which is essentially \(R_C\); looking right it sees \(R_L\):
The emitter bypass capacitor \(C_E\). This is the one that is nearly always got wrong. The capacitor does not work into \(R_E\); it works into \(R_E\) in parallel with the resistance looking up into the emitter, which by the reflection rule of Chapter 19 is \(r_e\) plus the total base-circuit resistance divided by \((1+\beta)\):
Note the size of the discrepancy: the emitter resistor is 1 kΩ and the resistance the capacitor sees is 17.82 Ω, a factor of 56. A designer who used \(R_E\) would specify 8.4 µF where 470 µF is needed, and would build an amplifier whose gain collapsed below about a kilohertz. It is also why the bypass capacitor is always the largest component on the board and always the dominant low-frequency break.
With breaks at 2.82, 9.73 and 19.01 Hz, the normalised response is the product of three first-order high-pass factors:
At \(f = 19.01\) Hz the three factors give \(0.707 \times 0.890 \times 0.989 = 0.622\), which is \(-4.12\) dB — already past the half-power point rather than at it. Solving the product for \(-3.01\) dB gives \(f_L = 23.19\) Hz. The dominant-pole estimate of 19.01 Hz is therefore 18 per cent optimistic. A useful approximation when the breaks are close is
which is within 8 per cent of the exact answer and takes no iteration. If a lower cut-off of 20 Hz is specified and 23.2 Hz is what you get, the fix is to enlarge \(C_E\): raising it from 470 µF to 1000 µF moves \(f_{CE}\) to 8.93 Hz and \(f_L\) to about 12.9 Hz. Enlarging \(C_2\) would do almost nothing, because a break at 2.82 Hz is already far outside the band.
The design rule that follows is to place one break clearly dominant and the others at least a decade below it. Then the dominant-pole estimate is accurate, the phase shift at the band edge is close to 45° rather than 135°, and — if the amplifier is later enclosed in feedback — there is no risk of three low-frequency poles conspiring to produce 180° of extra phase shift and turning the amplifier into the motorboating oscillator of Chapter 29.
6 The Miller Effect and the High-Frequency Roll-off
At high frequency the external capacitors are short circuits and the transistor's own capacitances take over. The hybrid-\(\pi\) model of Chapter 19 acquires two of them: \(C_\pi\) between base and emitter, which is dominated by the diffusion capacitance of the forward-biased junction and is therefore proportional to \(I_C\); and \(C_\mu\), the depletion capacitance of the reverse-biased collector-base junction, quoted on data sheets as \(C_{ob}\) and typically 2 to 8 pF. The trouble is entirely with \(C_\mu\), because it bridges input and output.
Miller's theorem. Let an impedance \(Z_f\) bridge two nodes whose voltages are \(v_1\) and \(v_2 = A_vv_1\). The current drawn from node 1 through it is
Node 1 behaves as though an impedance \(Z_f/(1-A_v)\) went from it to ground. For a capacitor, \(Z_f = 1/j\omega C_f\), and dividing an impedance means multiplying a capacitance, so with an inverting gain \(A_v = -|A_v|\):
The output-side result comes from repeating the calculation at node 2: the current leaving it through \(Z_f\) is \((v_2-v_1)/Z_f = v_2(1-1/A_v)/Z_f\). The input multiplication is enormous and the output multiplication negligible — for \(|A_v| = 125.85\), 4 pF becomes 507.4 pF at the input and 4.03 pF at the output. And the effect requires inverting gain: an emitter follower, with \(A_v \approx +0.95\), gives \(C_M(\text{in}) = 4(1-0.95) = 0.2\) pF, which is why followers are so fast.
Take the Chapter 19 stage with a device whose data sheet quotes \(f_T = 300\) MHz at this current and \(C_{ob} = C_\mu = 4\) pF. Then \(C_\pi = g_m/2\pi f_T - C_\mu = 0.07727/(2\pi\times3\times10^{8}) - 4\ \text{pF} = 41.0 - 4.0 = 37.0\) pF. Allow 5 pF of stray wiring capacitance at the base node and 8 pF at the collector node.
Input pole. The resistance at the base node, with the source killed, is everything in parallel:
Output pole. The resistance at the collector node is \(r_o\|R_C\|R_L = 1612.7\ \Omega\), and the capacitance is \(C_\mu(1+1/|A_v|) + C_{\text{stray}} = 4.03 + 8 = 12.03\) pF, giving \(f_{H(\text{out})} = 8.20\) MHz.
Overall. Combining the two poles, the gain is 3 dB down at 754.2 kHz. The input pole dominates completely, and of the 549.4 pF that produces it, 507.4 pF — 92 per cent — is Miller-multiplied \(C_\mu\). Take away the Miller effect, as the cascode does, and \(C_{\text{in}}\) becomes \(37 + 8 + 5 = 50\) pF, the input pole moves to 8.38 MHz, and the stage becomes eleven times faster for the price of one extra transistor and no loss of gain at all.
Note finally that \(R_{\text{th}}\) contains \(R_s\), so a stage driven from a low-resistance source is faster than the same stage driven from a high-resistance one: driving this amplifier from 10 kΩ instead of 600 Ω raises \(R_{\text{th}}\) to about 1090 Ω and drops the input pole below 270 kHz. That is a second argument for a follower in front of a common-emitter stage — it improves the bandwidth as well as the gain.
7 \(f_T\), Gain–Bandwidth and the Cost of Cascading
Two figures of merit describe the transistor itself rather than the circuit around it. The common-emitter current gain \(\beta\) is not constant with frequency: \(C_\pi\) and \(C_\mu\) shunt the base-emitter port, so beyond a break frequency \(f_\beta\) the current gain falls at 20 dB per decade.
The transition frequency \(f_T\) is where \(|\beta|\) has fallen to unity. Since the gain falls at 20 dB per decade from \(f_\beta\), the product \(\beta f_\beta\) is constant along that slope, so
\(f_T\) is the more useful of the two because data sheets quote it and because it is very nearly independent of \(\beta\). Note that \(f_T\) depends on \(g_m\) and therefore on bias current, which is why a data sheet always states the current at which \(f_T\) was measured, and why running a transistor at too low a current makes it slow.
The gain–bandwidth product of the stage is a different and smaller number. Here \(|A_v|f_H = 125.85 \times 754.2\ \text{kHz} = 94.9\) MHz, well below \(f_T = 300\) MHz, the shortfall being the Miller effect and the stray capacitance. The useful property is that for a given stage design the product is roughly constant: trading \(R_C\) for gain buys bandwidth back in the same proportion, and the same trade appears again in Chapter 26 as the fixed gain–bandwidth product of an operational amplifier.
What a cascade does to bandwidth. Suppose \(n\) identical stages, each with the same single dominant high-frequency pole at \(f_H\), are cascaded. Each contributes a factor \(1/\sqrt{1+(f/f_H)^2}\) to the magnitude, so the combined response is that factor raised to the \(n\)th power. The overall half-power frequency \(f_H(n)\) is where the product equals \(1/\sqrt{2}\):
The same algebra applied to the low-frequency end, where each stage contributes \(f/\sqrt{f^2+f_L^2}\), gives \(f_L(n) = f_L/\sqrt{2^{1/n}-1}\). The band closes from both ends by the same factor.
| Stages \(n\) | \(\sqrt{2^{1/n}-1}\) | \(f_H(n)\) from 754.2 kHz | \(f_L(n)\) from 23.19 Hz | Gain (dB) |
|---|---|---|---|---|
| 1 | 1.0000 | 754.2 kHz | 23.19 Hz | 42.00 |
| 2 | 0.6436 | 485.4 kHz | 36.03 Hz | 84.00 |
| 3 | 0.5098 | 384.5 kHz | 45.49 Hz | 126.00 |
| 4 | 0.4350 | 328.1 kHz | 53.31 Hz | 168.00 |
Read the table as an exchange rate. Going from one stage to two doubles the gain in decibels — a factor of 125.85 in voltage — and costs 36 per cent of the bandwidth. Going from three stages to four adds another 42 dB and costs 15 per cent. The marginal cost of bandwidth falls as \(n\) rises, which is the mathematical reason that multistage amplifiers are worth building at all. The shrinkage is also easy to design around: if a four-stage cascade must reach 500 kHz, each stage needs \(500/0.4350 = 1.15\) MHz, which is a matter of lowering \(R_C\), raising the bias current or using a cascode.
The first rule is exact and needs only that the loading of each stage by the next has already been accounted for. The second holds when the stages are identical and each has a single dominant pole; when they are not identical, the same construction applies numerically — multiply the individual responses and find where the product falls 3 dB — and the answer is always narrower than the narrowest single stage. There is no arrangement of cascaded stages whose bandwidth exceeds that of its worst member.
Chapter 26 follows directly. It takes a cascade of three stages — a differential input pair, a high-gain common-emitter stage and a class-AB follower — deliberately gives it an open-loop gain of \(2\times10^{5}\) and a bandwidth of 5 Hz, and then uses feedback to trade almost all of that gain back for bandwidth, linearity and predictability.
8 Summary and Key Results
| Quantity | Expression | Value |
|---|---|---|
| Overall gain | \(A_v = \prod A_{vk}\) | \((-52.54)(-125.85) = +6612\) |
| Same in decibels | \(\sum 20\log_{10}|A_{vk}|\) | \(34.41 + 42.00 = 76.41\) dB |
| Loading penalty | stage 1 driven into \(Z_{i2} = 1036\ \Omega\) | \(-125.85 \rightarrow -52.54\), a loss of 7.59 dB |
| Transformer coupling | \(n = \sqrt{R_{\text{wanted}}/R_L}\) | 15.81:1 turns 8 Ω into 2 kΩ |
| Darlington current gain | \(\beta_D = \beta_1\beta_2+\beta_1+\beta_2\) | 10 200 (80.17 dB); \(V_{BE} = 1.4\) V |
| Darlington input resistance | \((1+\beta_1)[r_{e1}+(1+\beta_2)(r_{e2}+R_E')]\) | 5.37 MΩ against 51.8 kΩ for one device |
| Darlington leakage | \((1+\beta_2)I_{CBO1}\) | 10 nA becomes 1.01 µA |
| Cascode | \(A_{v1} = -r_{e2}/r_{e1}\) | \(-1.00\), so Miller factor 2 not 126.85 |
| Coupling capacitor \(C_1\) | \(f = 1/2\pi(R_s+Z_i)C\) | 9.73 Hz with 10 µF into 1636 Ω |
| Coupling capacitor \(C_2\) | \(f = 1/2\pi(R_C+R_L)C\) | 2.82 Hz with 4.7 µF into 12 kΩ |
| Bypass capacitor \(C_E\) | \(R_{\text{eq}} = R_E\|(r_e+R_s'/(1+\beta))\) | 17.82 Ω, so 19.01 Hz with 470 µF |
| True lower cut-off | product of the three high-pass factors | 23.19 Hz, not the 19.01 Hz of the dominant pole |
| Miller capacitance | \(C_M = C_\mu(1+|A_v|)\) | 4 pF becomes 507.4 pF; output side 4.03 pF |
| High-frequency poles | \(1/2\pi RC\) at base and collector nodes | 762.4 kHz and 8.20 MHz; overall 754.2 kHz |
| \(f_\beta\) and \(f_T\) | \(f_T = \beta f_\beta = g_m/2\pi(C_\pi+C_\mu)\) | 3.00 MHz and 300 MHz |
| Stage gain–bandwidth | \(|A_v|f_H\) | 94.9 MHz, well below \(f_T\) |
| Bandwidth of \(n\) stages | \(f_H(n) = f_H\sqrt{2^{1/n}-1}\) | 754.2, 485.4, 384.5, 328.1 kHz for \(n = 1..4\) |
9 Common Mistakes
The commonest error in a cascade calculation is to take each stage's gain from its own analysis, in which the collector works into \(R_C\|R_L\), and multiply them together. In a real cascade every stage except the last works into the input impedance of the next stage, which for a common-emitter stage is about a kilohm and dominates \(R_C\) completely. For the amplifier here the unloaded product is 15 838 and the true answer is 6612 — the estimate is 2.4 times too large, or 7.59 dB. Always analyse a cascade from the output end backwards, computing each stage's load before its gain, and remember that the input impedance you need is that of the following stage including its bias divider.
Miller's theorem produces two different capacitances, not one. The input side gets \(C_f(1+|A_v|)\), which for a gain of 126 turns 4 pF into 507 pF; the output side gets \(C_f(1+1/|A_v|)\), which turns the same 4 pF into 4.03 pF. Using 507 pF at the collector as well would put the output pole at 194 kHz instead of 8.20 MHz and would suggest that the output node dominates the response, which is the opposite of the truth. The asymmetry has a simple physical reading: the input node has to supply the current that swings the far end of \(C_\mu\) through 126 times its own voltage, while the output node has to supply only the small extra current caused by the input's much smaller swing.
Two related slips. The bypass capacitor works into \(R_E\|(r_e + R_s'/(1+\beta))\), which here is 17.82 Ω against \(R_E = 1\) kΩ — a factor of 56, so a design based on \(R_E\) undersizes the capacitor by that factor and lands the lower cut-off at about a kilohertz. Then, having found the breaks correctly, it is tempting to quote the largest of them as \(f_L\). It is not: the other breaks have already removed about 1 dB by the time the dominant one has removed 3 dB, so the true \(-3\) dB point is higher — 23.19 Hz against a dominant break of 19.01 Hz here. Quote \(\sqrt{\sum f_k^2} = 21.5\) Hz as a quick estimate, or solve the product exactly, but never assume the dominant break is the answer unless the others are a decade away.
10 Chapter Review
1. Three stages have voltage gains of 40, \(-25\) and 12. Express the overall gain as a number and in decibels, and state the phase relationship between input and output.
The overall gain is the product, \(40 \times (-25) \times 12 = -12\,000\). In decibels, \(20\log_{10}40 = 32.04\) dB, \(20\log_{10}25 = 27.96\) dB and \(20\log_{10}12 = 21.58\) dB, and the sum is 81.58 dB — which checks against \(20\log_{10}12\,000 = 81.58\) dB directly. The decibel scale carries magnitude only, so the sign must be tracked separately: one inverting stage out of three leaves the cascade inverting, and the output is 180° out of phase with the input at mid-band. Note also that the decibel figure alone would not let you reconstruct the individual gains, and that if these were the gains of stages measured in isolation the true cascade gain would be smaller, since each stage would be loaded by the input impedance of the next.
2. A common-emitter stage has \(Z_i = 1.5\) kΩ, \(R_C = 3.3\) kΩ and \(R_L = 15\) kΩ, with \(r_e = 15\ \Omega\) and \(R_s = 1\) kΩ. It is driven by \(C_1 = 4.7\ \mu\)F and coupled out by \(C_2 = 2.2\ \mu\)F, and its 1.5 kΩ emitter resistor is bypassed by 100 µF. Take \(\beta = 120\) and \(R_1\|R_2 = 8\) kΩ. Find the three low-frequency breaks and estimate \(f_L\).
For \(C_1\) the resistance is \(R_s + Z_i = 1000 + 1500 = 2500\ \Omega\), so \(f_{C1} = 1/[2\pi(2500)(4.7\times10^{-6})] = 13.55\) Hz. For \(C_2\) it is \(R_C + R_L = 3300 + 15\,000 = 18\,300\ \Omega\), so \(f_{C2} = 1/[2\pi(18\,300)(2.2\times10^{-6})] = 3.95\) Hz. For \(C_E\), first find \(R_s' = R_s\|R_1\|R_2 = 1000\|8000 = 888.9\ \Omega\); then the resistance looking up into the emitter is \(r_e + R_s'/(1+\beta) = 15 + 888.9/121 = 15 + 7.35 = 22.35\ \Omega\), and in parallel with \(R_E = 1500\ \Omega\) that is 22.02 Ω. So \(f_{CE} = 1/[2\pi(22.02)(100\times10^{-6})] = 72.28\) Hz. The bypass capacitor dominates by a factor of more than five, so the quick estimate \(f_L \approx \sqrt{13.55^2+3.95^2+72.28^2} = 73.65\) Hz is close to the exact answer, which comes out at 73.9 Hz when the product of the three factors is solved. This amplifier would be unusable for audio: 100 µF is far too small for a 22 Ω source impedance, and raising it to 470 µF would move \(f_{CE}\) to 15.4 Hz and \(f_L\) to about 21 Hz.
3. A common-emitter stage has \(C_\mu = 5\) pF and a mid-band gain of \(-80\). The base node has a total resistance of 500 Ω and \(C_\pi = 30\) pF, with 5 pF of stray capacitance. Find the input pole. Then replace the stage by a cascode with the same overall gain and recompute.
The Miller capacitance at the input is \(C_\mu(1+|A_v|) = 5(1+80) = 405\) pF, so the total input capacitance is \(30 + 405 + 5 = 440\) pF and the pole sits at \(f = 1/[2\pi(500)(440\times10^{-12})] = 723.4\) kHz. In a cascode the lower transistor is loaded by the emitter of the upper one, whose resistance is \(r_e\) — the same \(r_e\) the lower device has, since they carry the same current — so the lower stage's gain is \(-1\) and the Miller factor is \((1+1) = 2\). The input capacitance becomes \(30 + 10 + 5 = 45\) pF and the pole moves to \(f = 1/[2\pi(500)(45\times10^{-12})] = 7.074\) MHz, a factor of 9.78 improvement. The overall gain is unchanged at \(-80\), because the gain the cascode loses in the lower device it recovers exactly in the common-base upper device: \((-r_e/r_e)(+R_L'/r_e) = -R_L'/r_e\). The cost is one extra transistor, a divider and a decoupling capacitor to hold the upper base, and about 1 V of headroom, since the lower transistor's collector must stay above saturation while sitting under the upper one's emitter.
4. An amplifier is required to give 80 dB of gain over 20 Hz to 200 kHz. Each available stage gives 42 dB with \(f_L = 23\) Hz and \(f_H = 754\) kHz. How many stages are needed, and does the cascade meet the specification?
Two stages give \(2 \times 42.00 = 84.00\) dB, which exceeds the 80 dB required with 4 dB to spare — useful margin, since the loading of stage 1 by stage 2 has not yet been counted and will remove some of it. Now the band. With \(n = 2\), the shrinkage factor is \(\sqrt{2^{1/2}-1} = 0.6436\), so \(f_H(2) = 754 \times 0.6436 = 485.3\) kHz and \(f_L(2) = 23/0.6436 = 35.74\) Hz. The high end is comfortable — 485 kHz against 200 kHz required — but the low end fails: 35.7 Hz against 20 Hz required. The cascade meets the gain and the upper limit but not the lower one. The fix is at the low-frequency end only, and it is cheap: increase the bypass capacitors. Each stage needs \(f_L \le 20 \times 0.6436 = 12.87\) Hz, so \(f_{CE}\) must come down from 19.0 Hz to roughly 10 Hz, which means raising \(C_E\) from 470 µF to about 1000 µF in each stage. Note the general shape of the answer: cascading always makes the low-frequency requirement harder as well as the high-frequency one, and it is the requirement with the least margin — here the lower cut-off — that fails first.
5. A Darlington pair with \(\beta_1 = \beta_2 = 80\) is used as an emitter follower with \(R_E = 2.2\) kΩ and no external load, at \(I_{E2} = 5\) mA from a 15 V supply. Find \(\beta_D\), \(r_{e1}\), \(r_{e2}\), the input resistance at the base and the voltage gain, and comment on the bias implications.
The composite current gain is \(\beta_D = \beta_1\beta_2+\beta_1+\beta_2 = 6400 + 80 + 80 = 6560\). The emitter currents are \(I_{E2} = 5\) mA and \(I_{E1} = I_{E2}/(1+\beta_2) = 5/81 = 61.73\ \mu\)A, so \(r_{e2} = 26/5 = 5.20\ \Omega\) and \(r_{e1} = 26/0.06173 = 421.2\ \Omega\). Reflecting the 2.2 kΩ emitter resistor up through both devices, \(R_{\text{in(base)}} = (1+\beta_1)[r_{e1}+(1+\beta_2)(r_{e2}+R_E)] = 81[421.2 + 81(2205.2)] = 81(179\,042) = 14.50\ \text{M}\Omega\). The gain is \(A_v = R_E/(R_E + r_{e2} + r_{e1}/(1+\beta_2)) = 2200/(2200+5.20+5.20) = 0.9953\), essentially unity. Two bias implications follow. First, the base must be biased for \(V_{BE(\text{on})} \approx 1.4\) V rather than 0.7 V, so with the emitter at \(5\ \text{mA} \times 2.2\ \text{k}\Omega = 11.0\) V the base must sit at 12.4 V, leaving only 2.6 V of headroom to the 15 V rail — the divider must be designed around that, and the pair is close to running out of room. Second, a 14.5 MΩ input resistance is meaningless unless the bias divider is comparable, and any practical divider will be a few hundred kilohms at most, so the divider, not the transistor, sets the input impedance. That is the standard reason a Darlington follower is bootstrapped: returning the divider's mid-point to the emitter through a capacitor makes the divider appear \(1/(1-A_v) = 213\) times larger to the signal while leaving the d.c. bias untouched.