By the end of this chapter you should be able to:
- Construct the FET small-signal model and state the meaning and origin of \(g_m\) and \(r_d\).
- Derive and compute \(A_v\), \(Z_i\) and \(Z_o\) for a common-source stage with and without a source bypass capacitor.
- Analyse the source follower and the common-gate stage and choose between all three configurations.
- Use a JFET in its ohmic region as a voltage-variable resistor and design an attenuator with it.
- Compare the FET and BJT amplifiers of Chapters 19 and 21 on gain, impedance, noise and linearity, with figures.
- Explain what cascading and the cascode connection each achieve, and compute the result.
Chapter 19 did this job once already for the bipolar transistor: take a device with a curved characteristic, linearise it about the Q-point, replace it by a model made of resistors and one controlled source, and then use ordinary circuit theory to find gain and impedances. Nothing about that programme changes for a field-effect transistor, and the reader who has followed Chapter 19 will find the algebra here familiar to the point of monotony.
What changes is every number that comes out of it. The JFET biased in Chapter 21 has a transconductance of 3.355 mS where the bipolar transistor of Chapter 19 had 77.27 mS, so the common-source stage built on it has a voltage gain of \(-5.79\) where the common-emitter stage managed \(-125.9\). Twenty-two times less gain is not a small difference and it is not one that better design can recover. In exchange the input impedance rises from 1.04 kΩ to 1 MΩ, the largest input the stage will accept without visible distortion rises from about 1 mV to about 90 mV, and above a few hundred ohms of source resistance the FET stage is the quieter of the two.
This chapter builds the model, derives the three configurations, quantifies all of those comparisons with numbers on both sides, and finishes with the two arrangements — multistage and cascode — that recover what a single FET stage cannot supply.
1 The Small-Signal Model: \(g_m\) and \(r_d\)
A FET in saturation is described by two partial derivatives taken at the Q-point. The first is the transconductance, which says how much drain current a change of gate voltage produces:
Derived in Chapter 21 for the JFET; for an enhancement MOSFET the equivalent forms are \(g_m = 2k(V_{GS}-V_T) = 2\sqrt{kI_D}\). Data sheets call it \(y_{fs}\) or \(g_{fs}\) and quote it in millisiemens or, on older sheets, micromhos.
The second is the drain resistance, which says how much the drain current depends on the drain voltage it is supposed to be independent of:
The residual slope of the drain characteristics of Figure 21.2, caused by the pinch-off point creeping back towards the source. A data-sheet output admittance \(y_{os} = 25\ \mu\text{S}\) means \(r_d = 40\ \text{k}\Omega\), which is the value used throughout this chapter.
The model is then one controlled source and one resistor: a current source \(g_mv_{gs}\) from drain to source, with \(r_d\) across it, and nothing at all between gate and source. That last point is the whole difference from Chapter 19. The bipolar model needed \(r_\pi = (1+\beta)r_e = 1294\ \Omega\) between base and emitter because the base draws current; the FET gate draws none, so at mid-band the input of the model is an open circuit and the input impedance of any FET stage is whatever the bias network provides.
Every input-impedance calculation in Chapter 19 ended with \((1+\beta)r_e\) in parallel with the bias network, and the transistor was almost always the smaller term. Here the transistor contributes an open circuit, so \(Z_i\) is exactly the bias network — \(R_G\) for a self-biased stage, \(R_1\|R_2\) for a divider-biased one. Since Chapter 21 showed those resistors may be megohms without disturbing the bias, a FET stage can have any input impedance the designer chooses, up to the limit set by gate leakage. At high frequencies the picture changes, because \(C_{gs}\) and the Miller-multiplied \(C_{gd}\) are then in the way; Chapter 25 takes that up.
Two cautions about \(g_m\) before it is used. It is not a constant of the device: it depends on the operating point through \(\sqrt{I_D}\), so it is set by the bias design of Chapter 21 and inherits whatever spread that design leaves. And it is an order of magnitude smaller than the bipolar equivalent at any sane current. Working the comparison backwards is instructive: to reach the 77.27 mS of the Chapter 19 amplifier, this JFET would need
which is nearly a thousand times its rated current. The gap is not a matter of biasing harder; it is structural, and it follows from the exponential characteristic of a junction against the square law of a channel.
2 The Common-Source Stage, Bypassed and Unbypassed
Draw the a.c. equivalent by the rules of Chapter 19: supplies to ground, large capacitors to short circuits, transistor to its model. With \(C_S\) in place the source is at signal ground, and the circuit reduces to \(R_G\) at the input and three resistors in parallel at the output.
The stage of Figure 24.1: the self-biased JFET of Chapter 21 (\(I_{DSS} = 12\) mA, \(V_P = -4\) V, \(R_S = 470\ \Omega\), \(R_D = 2.2\) kΩ, \(R_G = 1\) MΩ, \(V_{DD} = 16\) V), driving \(R_L = 10\) kΩ from a source of 600 Ω. From Chapter 21, \(I_D = 3.752\) mA, \(V_{GS} = -1.763\) V, \(V_{DS} = 5.983\) V, \(g_m = 3.355\) mS. Take \(y_{os} = 25\ \mu\text{S}\), so \(r_d = 40\) kΩ.
Input impedance. The gate is an open circuit, so
Output impedance. Kill the source, so \(v_{gs} = 0\) and the controlled source is an open circuit:
Voltage gain. The total drain load is \(R_L' = r_d\|R_D\|R_L = 40\,000\|2200\|10\,000 = 1725\ \Omega\), and \(v_o = -g_mv_{gs}R_L'\) while \(v_{gs} = v_i\), so
Unloaded — that is, with \(R_L\) removed — the load becomes \(r_d\|R_D = 2085\ \Omega\) and the gain rises only to \(-6.996\). The stage is not much affected by loading, because its own output impedance is low compared with a bipolar collector's, and because there is not much gain to lose.
Gain from the source. \(A_{vs} = A_vZ_i/(Z_i+R_s) = -5.789(10^6/1\,000\,600) = -5.785\). Essentially nothing is lost at the input, against the third that the bipolar stage of Chapter 19 gave away to the same 600 Ω source. That is the FET's compensating advantage in one line.
Sensitivity to device spread. Chapter 21 found that this self-bias circuit gives \(I_D\) from 1.743 mA to 5.857 mA across the device family, so \(g_m\) ranges from 2.952 mS to 3.608 mS — a spread of only 1.22 to 1, because \(g_m \propto \sqrt{I_D}\) and the square root halves the fractional variation. The gain therefore ranges from \(-5.09\) to \(-6.23\), that is \(\pm 10\) per cent, where the bypassed bipolar stage of Chapter 19 varied by \(\pm 45\) per cent over a comparable current spread. Low transconductance and square-law behaviour buy a predictability the bipolar device has to work for.
Removing the bypass capacitor. Leaving \(R_S\) unbypassed applies series-current feedback exactly as the unbypassed emitter resistor did in Chapter 19. Now \(v_{gs} = v_i - i_dR_S\), and working through the model with \(r_d\) included gives
The approximation drops \(r_d\), which is legitimate when \(r_d \gg R_S + R_L'\). For this stage the exact expression gives \(-2.200\) and the approximation \(-2.247\), an error of 2 per cent.
The design lever is a partial bypass: split \(R_S\) into an unbypassed \(R_{S1}\) and a bypassed remainder, exactly as the swamping resistor of Chapter 19 did. With \(R_L' = 1725\ \Omega\) and \(g_m = 3.355\) mS:
| \(R_{S1}\) unbypassed | \(1+g_mR_{S1}\) | \(A_v\) | Gain spread across the device family |
|---|---|---|---|
| 0 (fully bypassed) | 1.000 | \(-5.789\) | \(-5.09\) to \(-6.23\), \(\pm10.0\) % |
| 100 Ω | 1.336 | \(-4.335\) | \(-3.92\) to \(-4.58\), \(\pm7.7\) % |
| 220 Ω | 1.738 | \(-3.331\) | \(-3.09\) to \(-3.46\), \(\pm5.7\) % |
| 470 Ω (no bypass) | 2.577 | \(-2.247\) | \(-2.13\) to \(-2.31\), \(\pm3.9\) % |
The trade is the familiar one, but notice how much less there is to trade. The bipolar stage could afford to give away a factor of nine in gain for a factor of nine in linearity and stability, because it started with 126 and finished with 14.8. Starting from 5.79 there is almost nothing to give away, which is the practical reason a discrete FET common-source stage is almost always fully bypassed and the feedback is applied globally around several stages instead.
3 The Source Follower, the Common-Gate Stage, and Choosing Between Them
Common drain, the source follower. Take the output at the source, ground the drain for signals, and leave the whole of \(R_S\) unbypassed. The output voltage now subtracts directly from the gate voltage, since \(v_{gs} = v_i - v_o\), and
where \(R_S' = R_S\|R_L\|r_d\). The second form is worth memorising: \(1/g_m\) plays exactly the part \(r_e\) played in the bipolar emitter follower, and the output impedance looking back into the source is \(R_S\|(1/g_m)\).
Use the voltage-divider bias of Chapter 21 (\(V_G = 2.885\) V, \(R_1\|R_2 = 1.803\) MΩ, \(R_S = 1.5\) kΩ), remove \(R_D\) so the drain goes straight to the 16 V rail, and take the output from the source into \(R_L = 10\) kΩ. From Chapter 21, \(I_D = 3.211\) mA and \(g_m = 3.104\) mS.
Three observations. The gain is 0.797, noticeably below unity, where the bipolar emitter follower of Chapter 19 achieved 0.975 — because \(1/g_m = 322\ \Omega\) is a quarter of \(R_S'\), while \(r_e = 12.8\ \Omega\) was a fortieth of the bipolar equivalent. The output impedance is 265 Ω against the bipolar follower's 17.8 Ω, fifteen times worse, and for the same reason. But the input impedance is 1.803 MΩ against 4.72 kΩ, and the current gain is \(A_vZ_i/R_L = 0.797(1.803\ \text{M})/10\ \text{k} = 144\).
So the FET follower is not the low-impedance output stage the bipolar follower was; it is an input buffer, converting a megohm-level source into a few hundred ohms. That is precisely the job of an oscilloscope probe, an electrometer front end and the input stage of a FET-input operational amplifier, and it is why almost every real source follower in a discrete circuit is a FET rather than a bipolar transistor.
Common gate. Ground the gate for signals, drive the source, take the output at the drain. The input current is now the drain current itself, so the input impedance is \(1/g_m\) in parallel with the source bias resistor, and the gain is positive:
with \(Z_o \approx R_D = 2.2\) kΩ. Driven from a 600 Ω source the input divider throws away most of the signal, leaving \(A_{vs} = 6.050(182/782) = 1.41\), so the configuration is useless as a general voltage amplifier — exactly the conclusion Chapter 19 reached about the common-base stage, and for exactly the same reason. Its uses are the same three: terminating a transmission line, accepting current from a current source, and sitting on top of a common-source stage in the cascode of Section 6, where its low input impedance is the point rather than the problem.
| Common source | Common drain (follower) | Common gate | |
|---|---|---|---|
| Voltage gain | \(-g_mR_L' = -5.79\) | \(R_S'/(R_S'+1/g_m) = 0.797\) | \(+g_mR_L' = +6.05\) |
| Phase | inverting | non-inverting | non-inverting |
| Input impedance | \(R_G = 1\) MΩ | \(R_1\|R_2 = 1.80\) MΩ | \(R_S\|(1/g_m) = 182\ \Omega\) |
| Output impedance | \(R_D\|r_d = 2.09\) kΩ | \(R_S\|(1/g_m) = 265\ \Omega\) | \(\approx R_D = 2.2\) kΩ |
| Current gain into the stated load | \(A_vZ_i/R_L = -579\) | 144 | \(\approx 1\) |
| High-frequency behaviour | poor: Miller multiplies \(C_{gd}\) | good | excellent: no Miller effect |
| Used for | voltage gain from a high-impedance source | input buffering, impedance conversion | line termination, cascode upper device |
4 The FET as a Voltage-Variable Resistor
Everything so far has kept the device in saturation. Take it into the ohmic region instead — hold \(V_{DS}\) to a few tens of millivolts, well below \(V_{GS}-V_P\) — and the FET stops being an amplifier and becomes a resistor whose value the gate controls. Differentiating the triode equation at \(V_{DS} \to 0\) gives
Note that \(r_{DS(0)} = 1/g_{m0}\): the smallest resistance the channel can present is the reciprocal of the largest transconductance it can deliver. This is not a coincidence but the same channel conductance viewed from two ends of the characteristic.
Two properties make the arrangement useful. It is a genuine resistance, symmetrical about zero and passing current in either direction, so it can sit in the signal path of an a.c. circuit; and it is controlled by a voltage that draws no current, so the control terminal is completely isolated from the signal. Its limitation is linearity: the \(V_{DS}^2/2\) term of the triode equation is only negligible while \(V_{DS} \ll |V_P|\), so the signal across the device must be kept to perhaps 100 mV, and even then the resistance is modulated slightly by the signal itself. The standard cure is to feed half the drain voltage back to the gate through a pair of equal resistors, which cancels the square term to first order and extends the usable range by roughly a factor of ten.
Put the JFET from the source to ground and a fixed 10 kΩ resistor in series with the signal. The output, taken across the FET, is \(v_o/v_i = r_{DS}/(10\,000+r_{DS})\).
| \(V_{GS}\) | \(1-V_{GS}/V_P\) | \(r_{DS}\) | Attenuation |
|---|---|---|---|
| 0 V | 1.000 | 166.7 Ω | 0.0164, \(-35.7\) dB |
| \(-1\) V | 0.750 | 222.2 Ω | 0.0217, \(-33.3\) dB |
| \(-2\) V | 0.500 | 333.3 Ω | 0.0323, \(-29.8\) dB |
| \(-3\) V | 0.250 | 666.7 Ω | 0.0625, \(-24.1\) dB |
| \(-3.5\) V | 0.125 | 1333 Ω | 0.1176, \(-18.6\) dB |
The control range is 17.1 dB for a 3.5 V change on the gate, and it is strongly nonlinear in \(V_{GS}\) — almost all of the useful range lies in the last volt before pinch-off, because \(r_{DS}\) goes to infinity there. That is exactly the behaviour wanted in the amplitude-stabilising loop of a Wien-bridge oscillator, where the FET is the variable element and the loop drives it towards pinch-off as the amplitude rises; Chapter 29 builds that circuit. Interchanging the FET and the fixed resistor gives an attenuator that works the other way round, and putting the FET in the feedback path of an inverting op-amp stage gives a voltage-controlled gain rather than a voltage-controlled attenuation.
5 FET Against BJT: Gain, Impedance, Noise and Linearity
The two devices have now been taken through identical exercises — the same three configurations, the same style of worked example, comparable operating currents — so the comparison can be made with numbers rather than adjectives. The BJT column comes from Chapter 19: \(I_C = 2.009\) mA, \(\beta = 100\), \(r_e = 12.81\ \Omega\), \(g_m = 77.27\) mS. The FET column comes from this chapter: \(I_D = 3.752\) mA, \(g_m = 3.355\) mS.
| BJT common emitter (Ch 19) | FET common source (this chapter) | |
|---|---|---|
| Bias current | 2.009 mA | 3.752 mA |
| Transconductance | 77.27 mS | 3.355 mS |
| \(g_m/I_D\) — gain bought per milliamp | 38.5 V\(^{-1}\), and constant | 0.89 V\(^{-1}\), falling as \(1/\sqrt{I_D}\) |
| Loaded voltage gain | \(-125.9\) | \(-5.79\) |
| Input impedance | 1.04 kΩ | 1.00 MΩ |
| Gain from a 600 Ω source | \(-79.7\) — 37 % lost at the input | \(-5.79\) — 0.06 % lost |
| Output impedance | 1.92 kΩ | 2.09 kΩ |
| Follower output impedance | 17.8 Ω | 265 Ω |
| Input for 1 % second harmonic | 0.52 mV | 89.5 mV |
| Harmonics generated | all of them (exponential) | the second only (square law) |
| Gain spread over the device family | \(\pm 45\) % | \(\pm 10\) % |
| Input noise voltage at 1 kHz | 1.33 nV/√Hz | 1.81 nV/√Hz |
| Input noise current | 2.54 pA/√Hz | 0.018 pA/√Hz |
| Optimum source resistance | 524 Ω | 101 kΩ |
Gain. The factor of 23 is structural. A bipolar transistor's collector current is exponential in \(V_{BE}\), so its transconductance is \(I_C/V_T\), a fixed 38.5 siemens per amp of bias current regardless of geometry, doping or manufacturer. A FET's is \(2\sqrt{I_{DSS}I_D}/|V_P|\), which is smaller at every realistic current and gets relatively worse as the current falls. No arrangement of resistors recovers it; only more stages, or a bipolar stage after the FET, will do.
Linearity. Expand each device about its Q-point with an input \(v = V\cos\omega t\). For the FET, \(I_D \propto (V_{GS}+v-V_P)^2\) produces a fundamental term \(2(V_{GS}-V_P)V\) and a term in \(v^2 = V^2(1+\cos2\omega t)/2\), so the second-harmonic ratio is \(V/[4(V_{GS}-V_P)]\), and the series terminates: there is no third harmonic at all from an ideal square law. For the BJT, \(i_C = I_{CQ}e^{v/V_T}\) gives a second-harmonic ratio \(V/2V_T\) and an infinite series of higher harmonics. With \(V_{GS}-V_P = 2.237\) V and \(V_T = 26\) mV the one-per-cent limits are 89.5 mV and 0.52 mV, a ratio of 172. At an input of 100 mV the FET produces 1.1 per cent second harmonic and the BJT has left the small-signal region altogether.
Noise. Each device is described by an input-referred noise voltage \(e_n\) and an input-referred noise current \(i_n\), and the total input noise with a source resistance \(R_s\) is \(\sqrt{e_n^2 + (i_nR_s)^2 + 4kTR_s}\). The FET's \(e_n = \sqrt{4kT(2/3)/g_m}\) is the worse of the two, because \(e_n\) falls with \(g_m\) and the FET has less of it. But the FET's \(i_n = \sqrt{2qI_G}\) comes from a nanoamp of gate leakage rather than from 20 µA of base current, and it is 140 times smaller. The consequence is a crossover:
| \(R_s\) | Source alone | BJT total | FET total | Better device |
|---|---|---|---|---|
| 100 Ω | 1.29 nV/√Hz | 1.87 | 2.23 | BJT |
| 1 kΩ | 4.07 | 4.98 | 4.46 | FET |
| 10 kΩ | 12.9 | 28.5 | 13.0 | FET |
| 100 kΩ | 40.7 | 257 | 40.8 | FET, decisively |
| 1 MΩ | 129 | 2540 | 130 | FET, decisively |
The crossover is at \(R_s = 487\ \Omega\). Below it the bipolar transistor is quieter; above it the FET is, and above about 10 kΩ the FET adds essentially nothing to the source's own thermal noise — a noise figure of 0.02 dB at 100 kΩ against the bipolar transistor's 16.0 dB. That single table is why a moving-coil phono preamplifier is bipolar and a moving-magnet or piezoelectric one is FET, why a photodiode transimpedance amplifier is FET, and why a 50 Ω radio front end is bipolar. The one qualification is frequency: MOSFETs in particular have a large flicker-noise corner, often several kilohertz, arising from carriers trapping and detrapping at the oxide interface, so the low-frequency noise of a MOSFET can be far worse than the table suggests. JFETs, having no oxide, are much better in this respect, which is why they persist in low-noise instrumentation long after MOSFETs took over everything else.
6 Multistage and Cascode Arrangements
A gain of 5.79 is not enough for most jobs, and there are two standard ways of arranging FET stages to do better — one that multiplies the gain and one that rescues its bandwidth.
Cascading. Couple the output of one common-source stage to the gate of the next through a capacitor. The overall gain is the product of the individual gains, provided each stage's gain is computed with the next stage's input impedance as part of its load. Since a FET's input impedance is the megohm-level bias network rather than the kilohm-level input of a bipolar stage, that loading is almost negligible — which is the one place where the FET's low gain is partly compensated.
Two copies of the stage of Figure 24.1, the second's \(R_G = 1\) MΩ loading the first, with the 10 kΩ load on the second stage.
First stage. Its load is \(r_d\|R_D\|R_{G2} = 40\,000\|2200\|1\,000\,000 = 2081\ \Omega\), so \(A_{v1} = -3.355\ \text{mS}(2081) = -6.982\). The megohm gate resistor has cost only 0.2 per cent of the unloaded gain; the equivalent bipolar cascade loses a third of the first stage's gain to the second stage's 1 kΩ input.
Second stage. As computed in Worked Example 24.1, \(A_{v2} = -5.789\).
positive, because two inversions cancel. \(Z_i\) is still 1 MΩ and \(Z_o\) is still 2.09 kΩ. Two FETs and eight passive components have produced a third of the gain that one bipolar transistor gave in Chapter 19, which is a fair statement of the position; what they have also produced is a megohm input impedance, 90 mV of undistorted input range and a gain that varies by \(\pm 20\) per cent rather than \(\pm 45\) with device spread. Chapter 25 examines what cascading does to the bandwidth, which is not kind.
The cascode. The common-source stage's weakness at high frequency is the Miller effect: the gate-drain capacitance \(C_{gd}\) appears at the input multiplied by \((1+|A_v|)\), because its two ends move in opposite directions. The cure is to stop the drain from moving. Stack a common-gate stage on top of the common-source stage, so that the lower device's drain works into the upper device's source, whose input impedance is \(1/g_m = 298\ \Omega\).
The lower stage's voltage gain is then \(-g_m \times (1/g_m) = -1\). Its \(C_{gd}\) is multiplied by \((1+1) = 2\) instead of by 6.8, so the input capacitance falls by a factor of about 3.4 for this modest-gain stage — and by a factor of thirty or more in the high-gain integrated version, where the load is a current source rather than a 2.2 kΩ resistor. Meanwhile the upper device passes the same signal current on to the load, so the overall gain is unchanged:
The gain of a common-source stage with the bandwidth of a common-gate stage, at the cost of one extra device and its share of the supply voltage.
Two more benefits follow. The lower device now sees a nearly constant \(V_{DS}\), so channel-length modulation is suppressed and the effective output resistance of the pair is \(r_{d2}(1+g_{m2}r_{d1})\) rather than \(r_d\) — for these devices, \(40\ \text{k}\Omega(1+3.355\ \text{mS}\times40\ \text{k}\Omega) = 5.4\ \text{M}\Omega\), which is why the cascode is the standard high-gain stage in integrated analogue design. And the reverse isolation improves enormously, since a signal at the output has to work back through the upper device's grounded gate to reach the input at all. A common variant uses a JFET as the lower device, for its input impedance and noise, and a bipolar transistor as the upper one, for its speed.
Chapter 25 takes both arrangements further, deriving the frequency response of the coupling and bypass capacitors at the low end and of \(C_{gs}\) and \(C_{gd}\) at the high end, and showing exactly how much bandwidth cascading costs and the cascode returns.
7 Summary and Key Results
| Quantity | Expression | Value |
|---|---|---|
| Transconductance | \(g_m = 2\sqrt{I_{DSS}I_D}/|V_P|\) | 3.355 mS at \(I_D = 3.752\) mA |
| Drain resistance | \(r_d = 1/y_{os}\) | 40 kΩ for \(y_{os} = 25\ \mu\)S |
| Model topology | current source \(g_mv_{gs}\), \(r_d\) across it, open circuit at the input | no \(r_\pi\): \(Z_i\) is the bias network alone |
| CS gain, bypassed | \(A_v = -g_m(r_d\|R_D\|R_L)\) | \(-5.789\) loaded; \(-6.996\) unloaded |
| CS input and output impedance | \(Z_i = R_G\); \(Z_o = R_D\|r_d\) | 1.00 MΩ; 2085 Ω |
| CS gain, unbypassed | \(A_v \approx -g_mR_L'/(1+g_mR_S)\) | \(-2.247\) with \(R_S = 470\ \Omega\); exact value \(-2.200\) |
| Partial bypass | \(R_{S1}\) unbypassed | 100 Ω: \(A_v = -4.335\); 220 Ω: \(-3.331\) |
| Source follower | \(A_v = R_S'/(R_S'+1/g_m)\) | 0.797; \(Z_i = 1.80\) MΩ, \(Z_o = 265\ \Omega\) |
| Common gate | \(A_v = +g_mR_L'\); \(Z_i = R_S\|(1/g_m)\) | \(+6.050\); 182 Ω |
| Voltage-variable resistor | \(r_{DS} = r_{DS(0)}/(1-V_{GS}/V_P)\) | \(r_{DS(0)} = 1/g_{m0} = 166.7\ \Omega\); 17.1 dB of control range |
| Distortion limit | \(HD_2 = V/[4(V_{GS}-V_P)]\) | 89.5 mV for 1 %; BJT limit 0.52 mV |
| Noise crossover | \(\sqrt{e_n^2+(i_nR_s)^2+4kTR_s}\) | BJT quieter below 487 Ω, FET above |
| Two cascaded CS stages | \(A_{v1}A_{v2}\) | \((-6.982)(-5.789) = +40.42\), 32.1 dB |
| Cascode | lower-stage gain \(= -g_m/g_m = -1\) | same \(A_v = -5.79\); \(C_{gd}\) multiplied by 2 not 6.8; \(R_{out} = 5.4\) MΩ |
8 Common Mistakes
The habit is hard to break after Chapter 19, where every input calculation contained \((1+\beta)r_e\). A FET has no gate current at mid-band, so the model has nothing between gate and source at all and \(Z_i\) is exactly the bias network. Inventing a gate-source resistance produces an input impedance that is too low and, worse, suggests that a lighter bias divider would not help — when in fact making \(R_G\) ten times larger makes \(Z_i\) ten times larger, which is exactly the property the device was chosen for. The one place a gate-source element does belong is at high frequency, where \(C_{gs}\) is real and matters; that is Chapter 25's business, not this chapter's.
Data sheets quote \(y_{fs}\) or \(g_{fs}\) at \(V_{GS} = 0\), which is \(g_{m0} = 2I_{DSS}/|V_P| = 6.00\) mS for this device. The stage of Worked Example 24.1 is biased at \(V_{GS} = -1.763\) V, where \(g_m = 6.00(1 - 1.763/4) = 3.355\) mS, 44 per cent lower. Using the data-sheet figure predicts a gain of \(-10.4\) instead of \(-5.79\). The same trap appears in reverse when a stage is biased close to \(I_{DSS}\) and the designer conservatively uses a figure from further down the curve. Compute \(g_m\) from the actual \(I_D\) every time, using \(g_m = 2\sqrt{I_{DSS}I_D}/|V_P|\), which needs no separate knowledge of \(V_{GS}\).
The bipolar emitter follower of Chapter 19 gave \(Z_o = 17.8\ \Omega\) and a gain of 0.975, and it is the standard way to drive a heavy load. The FET follower of Worked Example 24.2 gives \(Z_o = 265\ \Omega\) and a gain of 0.797, because \(1/g_m = 322\ \Omega\) sets both and \(1/g_m\) is twenty-five times \(r_e\). Asking it to drive a 100 Ω load gives a gain of \(100/(100+322) = 0.24\), and the circuit will appear simply not to work. A FET follower is an input buffer, converting megohms to hundreds of ohms; the output stage that follows it should be bipolar.
9 Chapter Review
1. A common-source amplifier uses a JFET with \(I_{DSS} = 8\) mA and \(V_P = -3\) V, self-biased with \(R_S = 680\ \Omega\), \(R_D = 3.3\) kΩ, \(R_G = 2.2\) MΩ, \(V_{DD} = 20\) V, driving \(R_L = 22\) kΩ. Take \(r_d = 50\) kΩ. Find the Q-point, \(g_m\), \(A_v\), \(Z_i\) and \(Z_o\) with \(R_S\) bypassed, and then \(A_v\) with the bypass removed.
First the bias, by the method of Chapter 21. Substituting \(V_{GS} = -680I_D\) into Shockley's equation gives \(I_D = 0.008(1 - 226.67I_D)^2\) with \(I_D\) in amps, that is \(411.0I_D^2 - 4.627I_D + 0.008 = 0\). The roots are 9.123 mA and 2.133 mA; the first needs \(V_{GS} = -6.20\) V, beyond \(V_P\), so \(I_D = 2.133\) mA and \(V_{GS} = -1.451\) V. Checking: \(8(1-1.451/3)^2 = 8(0.5164)^2 = 2.133\) mA, which closes. The drain sits at \(20 - 2.133(3.3) = 12.96\) V and the source at 1.451 V, so \(V_{DS} = 11.51\) V against \(V_{DS(\text{sat})} = -1.451+3 = 1.549\) V — comfortably in saturation. The transconductance is \(g_m = 2\sqrt{I_{DSS}I_D}/|V_P| = 2\sqrt{8\times2.133}/3 = 2.754\) mS, which the other form confirms: \(g_{m0}(1-V_{GS}/V_P) = 5.333(1-1.451/3) = 2.754\) mS. With \(R_S\) bypassed, \(Z_i = R_G = 2.2\) MΩ, \(Z_o = R_D\|r_d = 3300\|50\,000 = 3096\ \Omega\), and the a.c. drain load is \(r_d\|R_D\|R_L = 50\,000\|3300\|22\,000 = 2714\ \Omega\), giving \(A_v = -2.754\ \text{mS}(2714) = -7.47\). Removing the bypass capacitor introduces \(1+g_mR_S = 1+2.754\ \text{mS}(680) = 2.873\) in the denominator, so \(A_v = -7.47/2.873 = -2.60\). The input impedance is unchanged at 2.2 MΩ, since the gate still draws nothing, and the output impedance rises slightly because the unbypassed source resistor raises the device's effective output resistance to \(r_d(1+g_mR_S) = 143.6\) kΩ, which in parallel with \(R_D\) is 3226 Ω.
2. Show that the common-source voltage gain is proportional to \(\sqrt{I_D}\) and explain what that implies for a designer who wants more gain from a given device.
The gain is \(A_v = -g_mR_L'\) and, from Chapter 21, \(g_m = 2\sqrt{I_{DSS}I_D}/|V_P|\), so \(|A_v| = 2R_L'\sqrt{I_{DSS}I_D}/|V_P| \propto \sqrt{I_D}\) for a fixed load. Doubling the bias current therefore increases the gain by only \(\sqrt{2} = 1.41\), and quadrupling it merely doubles the gain. That is a far worse return than the bipolar transistor offers, where \(|A_v| = R_L'/r_e = I_CR_L'/V_T\) is directly proportional to current. And it gets worse still, because in a real stage \(R_L'\) contains \(R_D\), and \(R_D\) has to shrink as \(I_D\) grows if the same \(V_{DS}\) is to be maintained from the same supply. If \(R_D\) is set by \(I_DR_D = \) constant, then \(R_D \propto 1/I_D\) and the gain actually falls as \(1/\sqrt{I_D}\). The practical conclusions are three. Raise the load resistance rather than the current: the gain is directly proportional to \(R_L'\), which is why integrated FET stages use a current source as the load and reach gains of \(g_mr_d = 3.355\ \text{mS}(40\ \text{k}\Omega) = 134\) rather than 5.79. Choose a device with a small \(|V_P|\) and a large \(I_{DSS}\), since \(g_{m0} = 2I_{DSS}/|V_P|\) is the figure of merit. And if neither is enough, cascade — two stages multiply where one stage's current only takes a square root.
3. A charge amplifier for a piezoelectric accelerometer sees a source that behaves as a 500 pF capacitor. Explain why a JFET input stage is chosen rather than a bipolar one, and estimate the noise at 100 Hz and at 10 kHz for each.
A capacitive source has an impedance \(1/(2\pi fC)\), which is 3.18 MΩ at 100 Hz and 31.8 kΩ at 10 kHz — in both cases far above the 487 Ω crossover computed in Section 5, so the FET wins on noise before any other consideration. The reason is the noise current: the total input noise is \(\sqrt{e_n^2 + (i_nZ_s)^2 + \text{source thermal noise}}\), and a capacitor generates no thermal noise of its own, so the whole of the comparison rests on the \(i_nZ_s\) term. At 100 Hz the bipolar transistor's 2.54 pA/√Hz flowing in 3.18 MΩ produces \(8.08\ \mu\text{V}/\sqrt{\text{Hz}}\), utterly swamping its 1.33 nV/√Hz voltage noise; the JFET's 0.018 pA/√Hz produces 57 nV/√Hz, so its total is \(\sqrt{1.81^2+57^2} = 57\) nV/√Hz. The FET is 140 times quieter. At 10 kHz the impedance is a hundredth as large, so the bipolar transistor gives 81 nV/√Hz and the FET \(\sqrt{1.81^2+0.57^2} = 1.90\) nV/√Hz — still 43 times better. There is a second and equally decisive reason that has nothing to do with noise: bias current. A bipolar input stage draws 20 µA of base current, which has nowhere to go in a capacitive source and would charge the input to the rail in microseconds unless a bias path is provided, and any such path shunts the signal. The JFET draws a nanoamp, so a 1 GΩ bias resistor suffices and the low-frequency corner it forms with 500 pF is at \(1/(2\pi \times 10^9 \times 500\ \text{pF}) = 0.32\) Hz. The only caveat is the flicker-noise corner: for a JFET this is typically a few tens of hertz, so the 100 Hz figure above is roughly right, whereas a MOSFET input would be several times noisier there.
4. Explain what the cascode connection does and does not achieve, and compute the input capacitance of a common-source stage with \(C_{gd} = 3\) pF and \(C_{gs} = 6\) pF, first alone with \(A_v = -5.79\) and then as the lower device of a cascode.
The Miller theorem states that a capacitance bridging input and output of an inverting stage of gain \(A_v\) appears at the input as \(C_{gd}(1+|A_v|)\), because its far end moves in the opposite direction and so a larger charge must be supplied for a given input swing. For the stage alone, the input capacitance is \(C_{in} = C_{gs} + C_{gd}(1+|A_v|) = 6 + 3(1+5.79) = 6 + 20.4 = 26.4\) pF. Placed as the lower device of a cascode, its drain works into the source of the upper device, whose input resistance is \(1/g_m = 298\ \Omega\), so its own voltage gain becomes \(-g_m(1/g_m) = -1\) exactly, and \(C_{in} = 6 + 3(1+1) = 12\) pF, a reduction of 2.2 to 1. Driven from a 100 kΩ source, the input pole moves from \(1/(2\pi \times 10^5 \times 26.4\ \text{pF}) = 60.3\) kHz to 133 kHz. What the cascode does not do is change the gain: the upper device passes the same signal current on to the same load, so the overall \(A_v\) is still \(-g_mR_L' = -5.79\). Nor does it help at all if the stage's gain was small to begin with — the benefit is proportional to the gain being removed from the Miller multiplication, so a stage with \(|A_v| = 100\) improves by a factor of 50 while this one improves only by 2.2. Its costs are one extra device, one extra bias network, and the drain-source voltage the upper device consumes, which comes straight out of the available output swing. Two further benefits, mentioned in Section 6, are the greatly increased output resistance — \(r_{d2}(1+g_{m2}r_{d1}) = 5.4\) MΩ against 40 kΩ — and the improved reverse isolation.
5. An instrumentation front end must accept a 60 mV peak signal from a 1 MΩ source with less than 2 per cent distortion, present at least 10 MΩ of input impedance, and deliver a gain of at least 30 into a 10 kΩ load. Propose a topology and justify each choice with figures from this chapter and Chapter 19.
Take the three requirements in turn. The 10 MΩ input impedance rules out any bipolar input stage immediately: Chapter 19's common-emitter stage managed 1.04 kΩ and even its emitter follower only 4.72 kΩ, and the ceiling is set by \((1+\beta)r_e\), which cannot be raised without reducing the bias current to the point where \(r_e\) and the noise both become unacceptable. A FET input is required, and since the bias network alone sets \(Z_i\), a self-biased JFET with \(R_G = 22\) MΩ delivers it directly — subject to the gate-leakage check of Chapter 21, since 1 nA through 22 MΩ is 22 mV of offset at 25 °C and would be 127 V at 150 °C, so the design must be specified for a moderate temperature or use a lower-leakage part. The 60 mV signal with 2 per cent distortion also points to a FET: the second-harmonic ratio is \(V/[4(V_{GS}-V_P)] = 60\ \text{mV}/[4(2.237)] = 0.67\) per cent for the device of this chapter, well inside the specification, whereas a bipolar stage taking 60 mV directly on its base would be grossly overdriven, its limit for 2 per cent being 1.04 mV. Noise also favours the FET decisively at 1 MΩ: from Section 5, 130 nV/√Hz against 2540 nV/√Hz. The gain of 30 is the one requirement the FET cannot meet, since a single common-source stage gives 5.79 and two cascaded give 40 but with a large signal in the second stage. The natural answer is a hybrid: a JFET source follower or common-source stage as the input, followed by a bipolar common-emitter stage for the gain. Concretely, a JFET common-source stage with \(R_G = 22\) MΩ and a gain of about \(-6\), driving the 1 kΩ input of a swamped bipolar stage — which will load it, so use a source follower between them, at \(Z_o = 265\ \Omega\) — and a bipolar stage swamped with \(R_{E1} = 100\ \Omega\) for a gain of about \(-15\) and an input of 3.57 kΩ. The product is about 90, comfortably above the required 30, and the surplus should be given away as further swamping to buy linearity and gain stability. This division of labour — FET for the input, bipolar for the gain — is exactly what a FET-input operational amplifier does internally, and Chapter 26 takes it up.