By the end of this chapter you should be able to:
- Explain why an enhancement MOSFET cannot be self-biased and what replaces the self-bias circuit of Chapter 21.
- Design and analyse drain-feedback and voltage-divider bias, and verify that the Q-point lies in saturation.
- Describe the switching trajectory between cut-off and the triode region and compute conduction loss from \(R_{DS(\text{on})}\).
- Use gate charge to estimate switching times, and compute switching loss and its variation with frequency.
- Explain the CMOS inverter transfer characteristic, its noise margins, and why it draws current only while switching.
- Describe the vertical structure of a power MOSFET and interpret a safe-operating-area diagram.
Chapter 22 left the enhancement MOSFET as a set of equations: no current below \(V_T\), a square law above it, a triode region for small \(V_{DS}\). This chapter uses the same device twice, in two ways that could hardly be more different, and the point of putting them in one chapter is that the difference is entirely a matter of where on the characteristic the device is asked to sit.
An amplifier holds the transistor at a fixed point in the saturation region and never lets it leave. It dissipates \(V_{DS}I_D\) continuously, which for the stage designed in Section 2 is 22.8 mW, and it delivers gain in exchange. A switch does the opposite: it spends its life either cut off, where the current is zero and the dissipation is zero, or deep in the triode region, where the voltage is a few tens of millivolts and the dissipation is again small. The dangerous region for a switch is precisely the saturation region the amplifier lives in, and the whole art of power switching is passing through it quickly. Section 4 computes exactly how much that transit costs.
Both halves matter. Almost every discrete MOSFET sold is used as a switch, in a motor drive, a switching regulator or a power supply; almost every MOSFET on a chip is used as a switch too, in the CMOS inverter of Section 5. The biasing of Sections 1 and 2 is what a small-signal designer needs before Chapter 24 can build an amplifier out of the result.
1 Why an Enhancement MOSFET Cannot Be Self-Biased
Chapter 21 biased a JFET by returning the gate to ground and letting the drain current develop a voltage across a source resistor. The gate then sat below the source, which is exactly what an n-channel JFET requires. Try the same circuit with an enhancement MOSFET and nothing happens: at switch-on \(I_D = 0\), so \(V_S = 0\), so \(V_{GS} = 0\), which is below \(V_T\), so \(I_D\) remains zero. The circuit has a stable operating point at the origin and stays there. Self bias fails for the enhancement device not marginally but completely.
Every workable scheme therefore delivers a positive \(V_{GS}\), and there are only two that use no extra supply. Both are treated fully in Section 2, and it is worth stating what each is doing before the arithmetic starts.
- Drain-feedback bias connects a large resistor \(R_G\) from drain to gate. No gate current flows, so no voltage is dropped across \(R_G\) and \(V_{GS} = V_{DS}\) exactly. That single equality does two things at once: it guarantees saturation, since \(V_{DS} = V_{GS} > V_{GS}-V_T\) always, and it provides negative feedback, because a device that passes too much current pulls its own drain down and therefore its own gate down with it.
- Voltage-divider bias holds the gate at a fixed \(V_G\) from a divider across the supply and puts a resistor in the source, so \(V_{GS} = V_G - I_DR_S\). The bias line is the same one drawn in Figure 21.4, only now it must intersect a transfer curve that starts at \(+V_T\) instead of at a negative pinch-off.
The parameter that varies from device to device is now \(k = \tfrac12\mu_nC_{ox}(W/L)\) rather than \(I_{DSS}\), together with \(V_T\). A discrete data sheet quotes them indirectly, as a threshold range and a single point \((V_{GS(\text{on})}, I_{D(\text{on})})\) from which \(k\) is recovered as \(I_{D(\text{on})}/(V_{GS(\text{on})}-V_T)^2\). The device used throughout Sections 1 and 2 has \(V_T = 2.0\) V and a nominal \(k = 0.5\ \text{mA/V}^2\), with \(k\) ranging from 0.35 to 0.75 mA/V\(^2\) — a spread of better than two to one, which is what each circuit has to absorb.
A data sheet rarely prints \(k\). It gives \(V_{GS(\text{th})}\), usually as a range such as 1.0 to 3.0 V measured at 250 µA, and one on-state point such as \(I_{D(\text{on})} = 8\) mA at \(V_{GS} = 6\) V. With \(V_T = 2.0\) V taken as typical, \(k = 8/(6-2)^2 = 0.5\ \text{mA/V}^2\), which is where the nominal figure used here comes from. Because \(k\) is recovered from a squared difference, an error in \(V_T\) is magnified: taking \(V_T = 1.5\) V instead would give \(k = 0.395\ \text{mA/V}^2\), 21 per cent lower. This is the practical reason the \(k\) spread quoted above is wider than a process engineer would recognise — part of it is really threshold spread in disguise.
2 Drain-Feedback and Voltage-Divider Bias, Worked
Both circuits below run from \(V_{DD} = 15\) V with \(R_D = 2.2\) kΩ, so their Q-points can be compared directly. In each case the analysis has the same three steps: write the bias equation, substitute it into the square law and solve the quadratic; reject the root that violates \(V_{GS} > V_T\); then verify that \(V_{DS} \ge V_{GS}-V_T\).
\(V_{DD} = 15\) V, \(R_D = 2.2\) kΩ, \(R_G = 10\) MΩ from drain to gate, \(V_T = 2.0\) V, \(k = 0.5\ \text{mA/V}^2\).
The bias equation. No gate current, so \(V_{GS} = V_{DS} = V_{DD} - I_DR_D\). Substituting into \(I_D = k(V_{GS}-V_T)^2\),
with \(I_D\) in amps. The roots are 7.692 mA and 4.539 mA. The first implies \(V_{GS} = 15 - 16.92 = -1.92\) V, which is below threshold and therefore spurious, so
Verification. The overdrive is \(5.013 - 2 = 3.013\) V, and \(V_{DS} = 5.013\) V exceeds it, so the device is in saturation with 2.0 V of margin. It always will be: \(V_{DS} = V_{GS}\) is greater than \(V_{GS}-V_T\) by exactly \(V_T\), whatever the current, so drain-feedback bias cannot put the device in the triode region. The transconductance is \(g_m = 2k(V_{GS}-V_T) = 2(0.5)(3.013) = 3.013\) mS and the device dissipates \(5.013 \times 4.539 = 22.8\) mW.
Device spread. Repeating with \(k = 0.35\) and \(k = 0.75\ \text{mA/V}^2\) gives 4.313 mA and 4.764 mA. That is a ratio of 1.104, or \(\pm 5.0\) per cent about the mean, from a device parameter that has changed by 114 per cent. The feedback is strong because the whole of \(R_D\) lies in the loop: a 1 mA rise in \(I_D\) pulls the gate down by 2.2 V, which at \(g_m = 3\) mS removes 6.6 mA of drain current. The loop gain is \(g_mR_D = 6.6\), and the residual spread is the open-loop spread divided by \(1+g_mR_D\).
The cost. The Q-point is not free to be placed. \(V_{DS}\) is forced to equal \(V_{GS}\), so it cannot be set independently, and the available downward swing is only \(V_{DS}-V_{DS(\text{sat})} = V_T = 2.0\) V. \(R_G\) also sits between output and input, so it appears at the input divided by \((1+|A_v|)\) by the Miller effect of Chapter 25 — with \(|A_v| \approx 6\) that is 1.4 MΩ, still large, but not the 10 MΩ the circuit appears to promise.
Same supply and drain resistor, with \(R_1 = 3.3\) MΩ, \(R_2 = 2.2\) MΩ and \(R_S = 470\ \Omega\).
The divider. The gate draws nothing, so
The bias equation. \(V_{GS} = 6 - 470I_D\), so
whose roots are 22.91 mA and 3.161 mA. The larger implies \(V_{GS} = 6 - 10.77 = -4.77\) V and is rejected, leaving
Verification. \(V_{DS} = 8.046 - 1.486 = 6.560\) V against a required \(V_{GS}-V_T = 2.514\) V, so the device is 4.05 V inside saturation — twice the margin of the drain-feedback design, and that margin is the output swing. The transconductance is \(g_m = 2(0.5)(2.514) = 2.514\) mS.
Device spread. With \(k = 0.35\) the current falls to 2.653 mA (\(V_{DS} = 7.917\) V) and with \(k = 0.75\) it rises to 3.752 mA (\(V_{DS} = 4.983\) V), a ratio of 1.414 or \(\pm 17\) per cent. Every member stays in saturation. The loop gain here is only \(g_mR_S = 2.514(0.470) = 1.18\), which is why the spread is three times worse than the drain-feedback result.
The comparison is worth stating plainly, because it inverts what Chapter 18 taught about bipolar transistors. There, collector-feedback bias was the mediocre scheme and voltage-divider bias the good one. Here it is the other way round: drain feedback holds the current five times better, because the feedback resistor is the whole drain resistor rather than a small emitter resistor, and because no gate current flows to spoil it. Voltage-divider bias wins on flexibility instead — it lets \(V_{DS}\) be chosen independently of \(V_{GS}\), which is what an amplifier needing a large output swing requires, and it presents no feedback path from output to input.
3 The Same Device as a Switch
Now abandon the Q-point. Drive the gate with a square wave that alternates between 0 V and 10 V, and the transistor no longer sits anywhere: it occupies two states and travels between them as fast as it can.
Off. With \(V_{GS} = 0\) the device is below threshold. The current is the subthreshold and junction leakage of Chapter 22, a data-sheet \(I_{DSS}\) of perhaps 25 µA at the full rated drain voltage and 125 °C, and typically nanoamps at room temperature. The dissipation is \(V_{DS}I_{\text{leak}} = 24 \times 25\ \mu\text{A} = 0.6\) mW at worst, which is negligible against everything else in this section.
On. With \(V_{GS} = 10\) V the overdrive is large, so \(V_{DS(\text{sat})} = V_{GS}-V_T\) is large, and the load current puts \(V_{DS}\) far below it: the device is deep in the triode region. Chapter 22 gave the small-\(V_{DS}\) resistance as \(1/[k_n'(W/L)(V_{GS}-V_T)]\), and a data sheet quotes the same quantity directly as \(R_{DS(\text{on})}\) at a stated gate voltage. For the power device used from here on it is 17.5 mΩ at \(V_{GS} = 10\) V and 25 °C.
The conduction loss follows at once. A switch carrying 10 A for a fraction \(D\) of each cycle dissipates
Note that it is \(I^2R\), not \(V_{CE(\text{sat})}I\) as it would be for a bipolar transistor. The distinction matters: a MOSFET's on-state drop falls to zero with the current, so at low currents it beats any bipolar device, while at high currents the \(I^2\) term eventually wins and a bipolar or IGBT saturation voltage of 1 to 2 V becomes competitive. The crossover for this device is at \(I = V_{CE(\text{sat})}/R_{DS(\text{on})} = 0.3/0.0175 = 17\) A.
Channel mobility falls as roughly \(T^{-2.4}\), so \(R_{DS(\text{on})}\) climbs steadily with junction temperature: a factor of about 1.5 at 100 °C and 1.8 at 150 °C for a typical silicon device. The conduction loss computed above therefore becomes \(100(0.0175 \times 1.5)(0.5) = 1.313\) W once the device is hot, and every thermal calculation must use the hot value or it will be optimistic by half.
The positive temperature coefficient is nevertheless the reason power MOSFETs can be paralleled without ballast resistors, which bipolar transistors cannot. If one device of a parallel set takes more than its share of current it heats up, its resistance rises, and it sheds current to the others. A bipolar transistor does the opposite — \(V_{BE}\) falls with temperature, so the hottest device takes more current — which is the thermal runaway of Chapter 18 and the reason emitter ballast resistors exist.
Between the two states the device must cross the saturation region, and while it is there both \(V_{DS}\) and \(I_D\) are large simultaneously. At the mid-point of a transition the instantaneous dissipation is roughly \(V_{DS}I_D/4 \approx 24 \times 10/4 = 60\) W, against 1.75 W in the on-state. The crossing lasts tens of nanoseconds, so the energy is small; but it is paid on every edge, and Section 4 shows that it is what limits switching frequency.
4 Gate Charge, Switching Time and the Loss Budget
How fast the transition happens is set not by the transistor's carriers — a MOSFET has no minority-carrier storage — but by how quickly the gate capacitance can be charged. The useful way to describe that is not with a capacitance, which varies wildly with voltage, but with gate charge: the total charge that must be delivered to take the gate from 0 V to a stated drive voltage under stated conditions. The device used here quotes \(Q_g = 63\) nC total, of which \(Q_{gs} = 14\) nC and \(Q_{gd} = 23\) nC.
A turn-on has three phases, and only two of them dissipate anything in the drain circuit.
- Delay. The gate charges from 0 V to \(V_{GS(\text{th})} = 4\) V. Nothing happens at the drain, so nothing is dissipated there. This consumes roughly the first half of \(Q_{gs}\).
- Current rise. The gate charges from threshold to the plateau voltage, at which the device carries the full load current. From the forward transconductance \(g_{fs} = 19\) S, \(V_{\text{plateau}} = V_{GS(\text{th})} + I_D/g_{fs} = 4 + 10/19 = 4.526\) V. The drain current rises to 10 A while \(V_{DS}\) is still the full 24 V.
- Voltage fall. The gate voltage now stops rising, because all the driver current is diverted into discharging \(C_{gd}\) as the drain falls — the Miller plateau. This phase moves \(Q_{gd} = 23\) nC and takes \(V_{DS}\) from 24 V to \(I_DR_{DS(\text{on})} = 0.175\) V.
The driver supplies 10 V through a total gate resistance of 10 Ω, so during the plateau it delivers
and during the current rise, taking the average gate voltage as \((4 + 4.526)/2 = 4.26\) V and the charge moved as \(Q_{gs}/2 = 7\) nC, \(I_G = 0.574\) A and \(t_{ri} = 12.2\) ns. Turn-off is the mirror image but slower, because the driver must now pull the gate down from the plateau to ground and the available voltage is only 4.526 V rather than 5.474 V: \(t_{rv} = 23/0.4526 = 50.8\) ns and \(t_{fi} = 16.4\) ns.
Device: \(V_{DSS} = 55\) V, \(R_{DS(\text{on})} = 17.5\) mΩ at \(V_{GS}=10\) V, \(Q_g = 63\) nC, \(Q_{gs}=14\) nC, \(Q_{gd}=23\) nC, \(V_{GS(\text{th})}=4\) V, \(g_{fs}=19\) S. Circuit: 24 V bus, 10 A clamped inductive load, duty ratio 0.5, driver 10 V through 10 Ω, junction at 100 °C.
Switching energy. Take the voltage and current transitions as linear ramps overlapping as described, so each transition contributes \(\tfrac12 V_{DS}I_D t\):
a total of 14.58 µJ per cycle. The peak instantaneous power during a transition is \(24 \times 10 = 240\) W.
Conduction loss. At 100 °C, \(R_{DS(\text{on})} = 1.5 \times 17.5 = 26.25\) mΩ, so \(P_{\text{cond}} = 100(0.02625)(0.5) = 1.313\) W, independent of frequency.
Gate-drive loss. \(P_G = Q_gV_{\text{drive}}f = 63\ \text{nC}(10)f\), all of it dissipated in the driver and \(R_G\) rather than in the transistor.
| Frequency | \(P_{\text{sw}}\) | \(P_{\text{cond}}\) | \(P_G\) | Total | Efficiency (120 W out) |
|---|---|---|---|---|---|
| 10 kHz | 0.146 W | 1.313 W | 0.006 W | 1.465 W | 98.8 % |
| 20 kHz | 0.292 W | 1.313 W | 0.013 W | 1.617 W | 98.7 % |
| 50 kHz | 0.729 W | 1.313 W | 0.032 W | 2.073 W | 98.3 % |
| 100 kHz | 1.458 W | 1.313 W | 0.063 W | 2.833 W | 97.7 % |
| 200 kHz | 2.915 W | 1.313 W | 0.126 W | 4.354 W | 96.5 % |
| 500 kHz | 7.288 W | 1.313 W | 0.315 W | 8.916 W | 93.1 % |
Reading the table. Conduction loss is a constant; switching and gate losses are proportional to frequency. They are equal at
which is the sense in which this device is a 100 kHz part. Below that frequency, choosing a device with lower \(R_{DS(\text{on})}\) improves matters; above it, choosing one with lower \(Q_g\) does. The two cannot both be improved by the same means, because both are proportional to gate area: doubling the width halves \(R_{DS(\text{on})}\) and doubles \(Q_g\). That conflict, first noticed at the end of Chapter 22, is the central trade of power-switch selection, and the figure of merit quoted on data sheets is precisely the product \(R_{DS(\text{on})}Q_g\), here \(17.5\ \text{m}\Omega \times 63\ \text{nC} = 1103\ \text{m}\Omega\,\text{nC}\).
Thermal check at 100 kHz. The transistor dissipates 2.833 W less the gate loss, say 2.77 W. In free air a TO-220 has \(R_{\theta JA} \approx 62\) °C/W, giving a rise of 172 °C and a junction temperature of about 197 °C — beyond the 175 °C rating, so the device fails. With a heatsink giving \(R_{\theta JC}+R_{\theta CS}+R_{\theta SA} = 1.0+0.5+2.0 = 3.5\) °C/W the rise is 9.7 °C and the junction sits at 35 °C in a 25 °C ambient. The heatsink, not the transistor, is what makes the design work.
The comparison that justifies switching at all. The same transistor used as a linear regulator dropping 12 V at 10 A would dissipate 120 W — forty times as much as the switch, and more than any practical heatsink will remove. That ratio, not any subtlety, is why power electronics switches.
5 The CMOS Inverter
Put a p-channel and an n-channel enhancement MOSFET in series between the rails, tie their gates together and take the output from their common drains, and the result is the complementary MOS inverter — the circuit on which essentially all digital electronics is built.
Its operation is easiest seen at the two rails. With the input at 0 V, \(V_{GSn} = 0\) so the n-channel device is off, while \(V_{SGp} = V_{DD}\) so the p-channel device is fully on: the output is pulled to \(V_{DD}\) through a small resistance, and no current flows because the lower device is off. With the input at \(V_{DD}\) the roles reverse and the output is pulled to ground. In both static states one device is off, so the path from rail to rail is broken and the static current is leakage only.
That is the property that made CMOS displace every earlier logic family. A TTL gate draws a few milliamps whatever it is doing; an NMOS gate with a resistive load draws current in one of its two states; a CMOS gate draws current only during the transition between them, when both devices are momentarily on together.
The switching threshold, where input and output are equal and both devices are in saturation. With \(V_{DD} = 5\) V, \(V_{Tn} = 1\) V, \(V_{Tp} = -1\) V and matched \(k_n = k_p\), \(V_M = 2.500\) V, exactly half the supply. Making the p-channel device three times stronger shifts \(V_M\) to 2.902 V; making it half as strong shifts it to 2.243 V. Since hole mobility is about 0.4 of electron mobility, matching requires the p-channel device to be drawn between two and three times wider, which is what a symmetrical library cell does.
The transfer characteristic and noise margins. Solving the two device equations simultaneously over the whole input range gives the curve of Figure 23.3. Its middle section is nearly vertical, because in that region both transistors are in saturation and behave as current sources, so the incremental gain is \(-(g_{mn}+g_{mp})(r_{dn}\|r_{dp})\) — a large number. The unity-gain points define the logic levels: for this matched inverter they fall at
| Parameter | Meaning | Value |
|---|---|---|
| \(V_{OH}\) | output high level | 4.625 V |
| \(V_{IL}\) | largest input still read as a 0 | 2.125 V |
| \(V_M\) | switching threshold | 2.500 V |
| \(V_{IH}\) | smallest input still read as a 1 | 2.875 V |
| \(V_{OL}\) | output low level | 0.375 V |
| \(NM_H = V_{OH}-V_{IH}\) | high-level noise margin | 1.750 V |
| \(NM_L = V_{IL}-V_{OL}\) | low-level noise margin | 1.750 V |
Both margins are 35 per cent of the supply, and they are equal because the inverter is symmetrical — the strongest practical argument for matching \(k_n\) and \(k_p\). By contrast a 74LS TTL gate offers noise margins of 0.4 V and 0.7 V on a 5 V supply, which is why CMOS is preferred in electrically noisy environments.
Where the power actually goes. Three mechanisms, in decreasing order of importance for most designs:
- Dynamic (switching) power, \(P = \alpha C_LV_{DD}^2f\). Charging a load capacitance to \(V_{DD}\) takes \(C_LV_{DD}^2\) from the supply, of which half is stored and half dissipated in the p-channel device; discharging dissipates the stored half in the n-channel device. So \(C_LV_{DD}^2\) is lost per full cycle regardless of the device resistances. For \(C_L = 50\) fF at 100 MHz on a 5 V rail this is 125 µW per gate; a million gates with an activity factor \(\alpha = 0.15\) would dissipate 18.75 W. The square-law dependence on \(V_{DD}\) is why supply voltages fell: the same chip at 1.2 V dissipates 1.08 W.
- Short-circuit (crowbar) current, flowing while the input is between \(V_{Tn}\) and \(V_{DD}-|V_{Tp}|\) and both devices conduct. It peaks at \(V_M\), where each device has \(1.5\) V of overdrive: with \(k = 100\ \mu\text{A/V}^2\) the peak is \(k(V_M-V_{Tn})^2 = 225\ \mu\text{A}\). It is typically 10 to 20 per cent of the dynamic power, and it is proportional to the input rise time, which is why slow edges are discouraged in CMOS design.
- Static leakage, the subthreshold conduction of Chapter 22 plus junction leakage. At 1 nA per gate on a 5 V rail a million gates leak 5 mW — negligible here, and dominant in a modern process where thresholds are a few hundred millivolts and the die holds billions of gates.
6 Power MOSFET Structure and the Safe Operating Area
The switch of Section 4 has an on-resistance of 17.5 mΩ and stands off 55 V. Neither is achievable with the lateral structure of Figure 22.2, in which the current runs sideways along the surface between two shallow diffusions: a lateral device that could block 55 V would need a long drift region, and its resistance would be measured in ohms.
A power MOSFET is therefore built vertically. The source metallisation and the gate polysilicon are on the top face; the drain is the whole of the bottom face, which is the substrate itself. Current leaves the source, flows a short distance laterally through a channel formed in a p-type body region under the gate, then turns and flows down through a lightly doped n\(^-\) drift layer to the drain contact. Two consequences follow. The blocking voltage is set entirely by the thickness and doping of the drift layer, so it can be traded against resistance independently of the channel. And the whole top surface can be tiled with cells — hexagonal, square or trench — wired in parallel, so a device of a few square millimetres can contain a million channels in parallel. That is where 17.5 mΩ comes from: not from one very wide transistor but from an enormous number of ordinary ones.
Two parasitic structures come free with the geometry and must be understood.
- The body diode. The p-body is shorted to the source metallisation, both to prevent the body effect of Chapter 22 and to disable the parasitic npn transistor formed by source, body and drift region. That short places a pn junction between source and drain, forward biased whenever the drain goes below the source. It is a real, rugged diode, rated at the full drain current, and it is indispensable in bridge circuits where it carries the freewheeling current of an inductive load. Its reverse-recovery charge is poor compared with a discrete fast diode, which matters at high frequency.
- Gate-drain capacitance \(C_{gd}\). This is the capacitance that produces the Miller plateau of Section 4 and that couples a fast-rising drain voltage back into the gate. If \(C_{gd}\,dV_{DS}/dt\) exceeds what the driver can sink through \(R_G\), the gate is pulled above threshold and the device turns itself on — the failure mode known as \(dv/dt\) turn-on, and the reason a low-impedance gate driver is not optional in a bridge.
The safe operating area. The SOA is a log-log plot of permitted \(I_D\) against \(V_{DS}\), and it is bounded by four straight lines, each corresponding to a different failure mechanism:
| Boundary | Set by | Slope on log-log axes | For our device |
|---|---|---|---|
| Left-hand limit | \(R_{DS(\text{on})}\) — the device cannot get below this line | \(+1\) | \(I_D = V_{DS}/0.0175\) |
| Top | maximum continuous or pulsed drain current; bond-wire and metallisation limit | 0 (horizontal) | 50 A continuous, 200 A pulsed |
| Diagonal | maximum power dissipation, \(V_{DS}I_D = P_{\max}\), which depends on pulse width | \(-1\) | \(P_{\max} = (T_{J\max}-T_C)/R_{\theta JC} = 150/1.0 = 150\) W d.c. |
| Right-hand limit | drain-source avalanche breakdown | vertical | \(V_{DSS} = 55\) V |
The switching trajectory of Figure 23.2 can be drawn on this plot, and doing so is the standard design check. In the off state the device sits at the bottom right, at 24 V and a few microamps; in the on state at the bottom left, at 0.18 V and 10 A. During a transition it travels across the middle of the diagram, through the point 12 V and 5 A where the instantaneous dissipation is 60 W. That excursion is permitted only because it lasts 50 ns: the d.c. power limit of 150 W would be violated by a continuous 60 W only in a device with poor cooling, but the pulsed limits are far higher because the silicon's own thermal capacity absorbs the energy before it reaches the case. A data-sheet SOA therefore shows several diagonals, one for each pulse width, and the 10 µs line typically sits ten times above the d.c. line.
Two further points distinguish a MOSFET SOA from the bipolar one of Chapter 20. The MOSFET has no second-breakdown boundary, or only a slight one, because current crowding is self-limiting: a hot spot has a higher resistance and sheds current, whereas in a bipolar transistor a hot spot has a lower \(V_{BE}\) and attracts it. This is why a MOSFET SOA at long pulse widths is bounded by the honest \(-1\) power hyperbola while a BJT's is cut back well below it. Against that, the MOSFET has a zero-temperature-coefficient point: at low currents the fall of \(V_T\) with temperature dominates and \(I_D\) rises with heat, while at high currents the fall of mobility dominates and \(I_D\) falls. Below the crossover — typically a few amps — a MOSFET held in the linear region can run away thermally, which is why devices used as linear pass elements or in hot-swap controllers are derated far below their switching SOA.
Chapter 24 returns the device to the saturation region and to the Q-point established in Section 2, and asks what small-signal gain can be got out of it — a question to which, after the 240 W peaks of this section, the answer will seem remarkably modest.
7 Summary and Key Results
| Quantity | Expression | Value |
|---|---|---|
| Why self bias fails | \(I_D = 0 \Rightarrow V_S = 0 \Rightarrow V_{GS} = 0 < V_T\) | the circuit sits at the origin and never starts |
| Drain-feedback bias | \(V_{GS} = V_{DS} = V_{DD}-I_DR_D\) | \(I_D = 4.539\) mA, \(V_{DS} = 5.013\) V, \(g_m = 3.013\) mS |
| its spread | loop gain \(g_mR_D = 6.6\) | 4.313 to 4.764 mA for \(k\) from 0.35 to 0.75; \(\pm5.0\) % |
| Voltage-divider bias | \(V_{GS} = V_G - I_DR_S\) | \(V_G = 6.00\) V, \(I_D = 3.161\) mA, \(V_{DS} = 6.560\) V, \(g_m = 2.514\) mS |
| its spread | loop gain \(g_mR_S = 1.18\) | 2.653 to 3.752 mA; \(\pm17\) % |
| Q-point verification | \(V_{DS} \ge V_{GS}-V_T\) | drain feedback: margin always \(=V_T=2.0\) V; divider: 4.05 V |
| Conduction loss | \(I_D^2R_{DS(\text{on})}D\) | 0.875 W at 25 °C; 1.313 W at 100 °C |
| Plateau voltage | \(V_{GS(\text{th})}+I_D/g_{fs}\) | \(4 + 10/19 = 4.526\) V |
| Switching times | \(t = Q/I_G\) | \(t_{ri}=12.2\), \(t_{fv}=42.0\), \(t_{rv}=50.8\), \(t_{fi}=16.4\) ns |
| Switching energy | \(\tfrac12V_{DS}I_Dt\) per transition | \(E_{on}=6.51\), \(E_{off}=8.07\), total 14.58 µJ/cycle |
| Loss crossover | \(f = P_{\text{cond}}/(E_{on}+E_{off})\) | 90.0 kHz; total 2.833 W at 100 kHz, 97.7 % efficient |
| Figure of merit | \(R_{DS(\text{on})}Q_g\) | 1103 mΩ·nC |
| Thermal check | \(T_J = T_A + PR_{\theta JA}\) | 197 °C in free air (fails); 35 °C with a 3.5 °C/W path |
| CMOS switching threshold | \(V_M = (V_{DD}+V_{Tp}+\sqrt{k_n/k_p}V_{Tn})/(1+\sqrt{k_n/k_p})\) | 2.500 V for matched devices on 5 V |
| CMOS noise margins | \(V_{OH}-V_{IH}\), \(V_{IL}-V_{OL}\) | 1.750 V each; \(V_{IL}=2.125\), \(V_{IH}=2.875\) V |
| CMOS dynamic power | \(\alpha C_LV_{DD}^2f\) | 125 µW per gate at 50 fF, 100 MHz, 5 V |
8 Common Mistakes
The circuit of Figure 21.3 — gate to ground through \(R_G\), source to ground through \(R_S\) — works for a JFET and for a depletion MOSFET and does nothing whatever for an enhancement device. With \(I_D = 0\) the source is at 0 V, so \(V_{GS} = 0\), which is below \(V_T\), so \(I_D\) stays at zero: the origin is a stable operating point. The symptom on the bench is a stage with the drain sitting at the supply rail and no signal at all. The cure is to put a positive voltage on the gate, either from a divider or by returning \(R_G\) to the drain rather than to ground.
A switch in the on state is in the triode region, where \(V_{DS} = I_DR_{DS(\text{on})} = 10(0.0175) = 0.175\) V and the dissipation is \(I^2R = 1.75\) W while conducting. Using the saturation value \(V_{DS(\text{sat})} = V_{GS}-V_T = 6\) V would give 60 W, thirty-four times too much, and would condemn a perfectly good design. The same error in reverse — assuming a device driven with only 5 V on its gate still has its 10 V on-resistance — is equally common and equally damaging, since \(R_{DS(\text{on})}\) may double or triple between 10 V and 5 V of drive. Always read \(R_{DS(\text{on})}\) at the gate voltage the driver actually supplies, and always at the hot junction temperature.
The 14.58 µJ of Worked Example 23.3 sounds trivial and is trivial — once. At 500 kHz it is paid a million times a second and becomes 7.29 W, five times the conduction loss and enough to destroy the device. The related error is to compare two candidate transistors on \(R_{DS(\text{on})}\) alone: the lower-resistance part is usually the physically larger one, with proportionally more gate charge, and above the crossover frequency it is the worse choice. Compute both terms, find the frequency at which they are equal, and note where the intended switching frequency falls relative to it.
9 Chapter Review
1. An enhancement MOSFET with \(V_T = 1.5\) V and \(k = 1.0\ \text{mA/V}^2\) is biased by drain feedback from \(V_{DD} = 12\) V with \(R_D = 1\) kΩ. Find the Q-point and \(g_m\), verify saturation, and state the available output swing.
With drain feedback \(V_{GS} = V_{DS} = 12 - 1000I_D\), so the square law gives \(I_D = 0.001(12 - 1000I_D - 1.5)^2 = 0.001(10.5 - 1000I_D)^2\) with \(I_D\) in amps. Expanding, \(1000I_D^2 - 22.0I_D + 0.11025 = 0\), whose roots are \(I_D = [22 \pm \sqrt{484 - 441}]/2000 = (22 \pm 6.557)/2000\), that is 14.28 mA and 7.721 mA. The first would need \(V_{GS} = 12 - 14.28 = -2.28\) V, below threshold, so it is rejected. Therefore \(I_D = 7.721\) mA and \(V_{GS} = V_{DS} = 12 - 7.721 = 4.279\) V. Checking the square law closes the loop: \(1.0(4.279-1.5)^2 = 1.0(2.779)^2 = 7.723\) mA. Saturation requires \(V_{DS} \ge V_{GS}-V_T = 2.779\) V, and \(V_{DS} = 4.279\) V exceeds it by exactly \(V_T = 1.5\) V, as drain feedback always does. The transconductance is \(g_m = 2k(V_{GS}-V_T) = 2(1.0)(2.779) = 5.557\) mS. For the output swing, the drain may fall by \(V_{DS}-V_{DS(\text{sat})} = 1.5\) V before the device enters the triode region, and may rise by \(12 - 4.279 = 7.72\) V before cut-off; the symmetrical undistorted swing is therefore only 1.5 V peak. That asymmetry is the standing weakness of drain-feedback bias, and it is why an amplifier needing a large output swing uses the divider circuit instead.
2. Explain why drain-feedback bias stabilises the drain current better than voltage-divider bias for a MOSFET, when for a BJT in Chapter 18 the divider was clearly the better circuit.
The strength of any negative-feedback bias scheme is measured by its loop gain, and in each case the loop gain is the transconductance multiplied by the resistance in the feedback path. For drain feedback that resistance is the whole of \(R_D\), because the entire drain voltage is fed back to the gate: with \(g_m = 3.013\) mS and \(R_D = 2.2\) kΩ the loop gain is 6.63, and the device spread is divided by \(1+6.63\). For divider bias the resistance in the loop is only \(R_S\), because only the source voltage is subtracted from the gate voltage: \(g_mR_S = 2.514\ \text{mS}(470) = 1.18\), so the spread is divided by 2.18. The observed results follow directly — \(\pm5\) per cent against \(\pm17\) per cent for the same \(2.1{:}1\) variation in \(k\). Why does the argument not carry over to the BJT? Two reasons. First, a bipolar divider must be made from low resistances, because base current loads it, and collector feedback would have to work through that same low-impedance divider; the FET's gate draws nothing, so \(R_G\) can be 10 MΩ and the feedback path costs no signal current at all. Second, and more fundamentally, BJT divider bias is not really a feedback scheme at heart: it works because \(I_C \approx (V_{th}-0.7)/R_E\) contains no transistor parameter whatever, since \(V_{BE}\) is a near-constant 0.7 V for every silicon transistor ever made. There is no such constant for a MOSFET — \(V_{GS}\) at a given current is a genuine device parameter — so the FET has to rely on loop gain, and drain feedback supplies more of it. The price is that drain feedback fixes \(V_{DS} = V_{GS}\) and so surrenders control of the output swing.
3. A MOSFET switch runs from 48 V at 8 A with a duty ratio of 0.4. Its \(R_{DS(\text{on})}\) is 30 mΩ at 25 °C, rising by a factor of 1.6 at the operating junction temperature, and its total switching energy is 20 µJ per cycle. Find the total loss at 40 kHz and at 250 kHz, the crossover frequency, and the heatsink needed at 250 kHz for a junction temperature of 110 °C in a 40 °C ambient, given \(R_{\theta JC} = 0.9\) °C/W and \(R_{\theta CS} = 0.4\) °C/W.
The hot on-resistance is \(1.6 \times 30 = 48\) mΩ, so the conduction loss is \(P_{\text{cond}} = I^2R_{DS(\text{on})}D = 64(0.048)(0.4) = 1.229\) W, independent of frequency. Switching loss is \(E f\): at 40 kHz that is \(20\ \mu\text{J}(40\ \text{kHz}) = 0.800\) W, giving a total of 2.029 W; at 250 kHz it is \(20\ \mu\text{J}(250\ \text{kHz}) = 5.000\) W, giving a total of 6.229 W. The two mechanisms are equal at \(f = P_{\text{cond}}/E = 1.229/20\ \mu\text{J} = 61.4\) kHz, so at 40 kHz the device is conduction-dominated and at 250 kHz it is firmly switching-dominated — a factor-of-four reduction in \(R_{DS(\text{on})}\) would buy only 0.9 W there, while halving the switching time would buy 2.5 W. For the thermal design at 250 kHz the permitted total thermal resistance is \(R_{\theta JA} = (T_J - T_A)/P = (110-40)/6.229 = 11.24\) °C/W. Subtracting the fixed parts, the heatsink must provide \(R_{\theta SA} = 11.24 - 0.9 - 0.4 = 9.94\) °C/W, which is a small clip-on extrusion — comfortable. It is worth noticing how much easier the thermal problem became by running slower: at 40 kHz the same junction limit permits \(R_{\theta JA} = 70/2.029 = 34.5\) °C/W, and no heatsink at all may be needed. The choice of switching frequency is in this sense a thermal decision as much as a magnetics one.
4. A CMOS inverter on a 3.3 V supply has \(V_{Tn} = 0.7\) V, \(V_{Tp} = -0.7\) V and matched devices. Find \(V_M\), estimate the noise margins, and compute the dynamic power of a 200,000-gate block switching at 50 MHz with a load of 30 fF per gate and an activity factor of 0.12. Compare with the same block at 5 V.
With matched devices \(\sqrt{k_n/k_p} = 1\), so \(V_M = (V_{DD}+V_{Tp}+V_{Tn})/2 = (3.3-0.7+0.7)/2 = 1.650\) V, exactly half the supply, as symmetry requires. For the noise margins the standard result for a symmetric inverter is \(V_{IL} = (3V_{DD}+2V_{Tn})/8\) and \(V_{IH} = (5V_{DD}-2V_{Tn})/8\), giving \(V_{IL} = (9.9+1.4)/8 = 1.413\) V and \(V_{IH} = (16.5-1.4)/8 = 1.888\) V, with \(V_{OH} = 3.063\) V and \(V_{OL} = 0.238\) V. The margins are therefore \(NM_H = 3.063 - 1.888 = 1.175\) V and \(NM_L = 1.413 - 0.238 = 1.175\) V. Expressed as a fraction of the supply that is 35.6 per cent, essentially the same as the 35.0 per cent obtained at 5 V — the thresholds were scaled with the supply in this example, so the shape of the characteristic is unchanged. The erosion is in absolute volts: 1.175 V of margin instead of 1.750 V, a reduction of a third. That matters because the noise a real system injects — ground bounce, crosstalk between adjacent tracks, supply droop — is set by currents and inductances and does not shrink when the rail does. Lowering \(V_{DD}\) therefore always costs immunity in the only units that count, and the alternative of not scaling \(V_T\) with it costs speed instead, since the overdrive available at the rail falls faster than the rail itself. The dynamic power is \(P = \alpha NC_LV_{DD}^2f = 0.12(200{,}000)(30\ \text{fF})(3.3)^2(50\ \text{MHz})\). Evaluating: \(0.12 \times 2\times10^5 = 2.4\times10^4\) effective gates; \(C_LV_{DD}^2 = 30\times10^{-15}(10.89) = 3.267\times10^{-13}\) J; times \(5\times10^7\) gives \(1.634\times10^{-5}\) W per gate; times \(2.4\times10^4\) gives 0.392 W. At 5 V the same block dissipates \(0.392(25/10.89) = 0.900\) W, 2.30 times more, exactly the ratio of the squares of the supply voltages. Dropping the rail from 5 V to 3.3 V thus removed 56 per cent of the dynamic power at the cost of 40 per cent of the noise margin and some speed — the trade that drove supply voltages down through the 1990s.
5. A designer proposes to use a power MOSFET as the pass element of a linear regulator, dropping 15 V at 3 A, and argues that since the device is rated at 150 W the 45 W dissipation is safe. Comment, referring to the safe operating area and to the zero-temperature-coefficient point.
The power rating alone does not settle the question, for three reasons. First, the 150 W figure is quoted with the case held at 25 °C, which no real heatsink achieves; the usable figure is \((T_{J\max}-T_C)/R_{\theta JC}\) evaluated at the case temperature the design actually produces. With \(R_{\theta JC} = 1\) °C/W and a case that sits at 80 °C, the permitted dissipation is \((175-80)/1 = 95\) W, and the thermal path from case to ambient must then remove 45 W, needing about \((80-40)/45 = 0.89\) °C/W of heatsink — a substantial extrusion with forced air. Second, and more seriously, the operating point (15 V, 3 A) lies in the middle of the SOA rather than at either corner, which is exactly where the linear-mode derating applies. Data sheets published since about 2010 show a separate d.c. SOA line that falls well below the \(-1\) power hyperbola at intermediate voltages, because of the effect the question names. Below the zero-temperature-coefficient point — typically a few amps of drain current, where the negative temperature coefficient of \(V_T\) outweighs the positive coefficient of mobility — a hotter part of the die passes more current, heats further and takes still more. In a switching application this never arises, because the device is either fully on, where the resistance's positive coefficient dominates and the die self-balances, or fully off. In linear operation at 3 A it may arise, and the failure is a local hot spot rather than a uniform overheat, so it is not prevented by keeping the average dissipation within rating. Third, the device is now in saturation continuously, so all the arguments of Section 3 about \(I^2R\) losses are irrelevant and the comparison with a switching regulator is stark: a buck converter doing the same job would dissipate a couple of watts rather than 45. The recommendation is either to use a device explicitly characterised for linear operation, with its own d.c. SOA curve and a generous derating, or — far better — to use a switching regulator and reserve the linear stage for the last volt of ripple rejection.