By the end of this chapter you should be able to:
- Describe accumulation, depletion and inversion in a MOS capacitor and identify the gate voltage at which each occurs.
- Compute a threshold voltage from doping, oxide thickness, gate material and fixed oxide charge.
- Derive the triode and saturation drain-current equations from the gradual-channel approximation and state the boundary between them.
- Distinguish enhancement-mode from depletion-mode devices and sketch the transfer characteristic of each.
- Quantify channel-length modulation, the body effect and subthreshold conduction, and say when each matters.
- Compare the JFET, the depletion MOSFET and the enhancement MOSFET, and state the handling precautions the gate oxide demands.
The JFET of Chapter 21 controls its channel with a reverse-biased junction, and that junction is the device's limitation as well as its principle. It leaks, so the input resistance falls apart above about 125 °C. It must never be forward biased, so the gate can only ever remove carriers from the channel and never add any. And it occupies silicon area on two faces of the channel, which makes the device awkward to shrink.
Replace the junction with an insulator and all three limitations go. A metal — or, since about 1970, a heavily doped polysilicon — electrode separated from the silicon by ten nanometres of thermally grown silicon dioxide will still control the channel by its field, because a field passes through an insulator perfectly well. But now no current can flow into the gate at all, in either direction and at any temperature, so the gate voltage may be positive or negative as convenient. That is the metal-oxide-semiconductor field-effect transistor, and it is the most manufactured object in human history: a modern processor contains tens of billions of them, and essentially every one is built on the physics of the next four pages.
This chapter develops the device from the MOS capacitor upwards. Sections 1 and 2 establish what a voltage on the gate does to the silicon underneath it and calculate the threshold voltage from process parameters. Section 3 builds the enhancement-mode transistor and derives its two regions. Section 4 introduces the depletion-mode device and the p-channel variants, Section 5 treats the three effects that spoil the ideal equations, and Section 6 compares all three FET families and explains why a MOSFET arrives in a conductive bag.
1 The MOS Capacitor: Accumulation, Depletion and Inversion
Before there is a transistor there is a capacitor. Take p-type silicon, grow a thin layer of silicon dioxide on it and deposit a conducting gate on top. Connect the silicon to ground and apply a voltage to the gate. The oxide is an insulator with a band gap of about 9 eV, so no current flows; whatever charge appears on the gate must be balanced by an equal and opposite charge in the silicon, and the interesting question is what form that charge takes.
Accumulation \((V_G < V_{FB})\). Make the gate negative. The field drives holes — the majority carriers in p-type material — towards the surface, and they pile up there in a thin layer perhaps a nanometre thick. The negative gate charge is balanced by an accumulation of mobile positive charge, the structure behaves as a parallel-plate capacitor of capacitance \(C_{ox}\) per unit area, and the surface is more strongly p-type than the bulk. Nothing useful for a transistor happens here, but the measured capacitance in accumulation is exactly how \(C_{ox}\), and hence the oxide thickness, is determined experimentally.
Depletion \((V_{FB} < V_G < V_T)\). Make the gate positive. Holes are now pushed away from the surface, leaving behind the negatively charged acceptor ions they had been neutralising. The balancing charge is therefore immobile: a depletion region grows into the silicon, exactly as it did on the p-side of the junction in Chapter 5, and for the same reason. Its width increases with gate voltage, and because that depletion capacitance appears in series with \(C_{ox}\), the total capacitance falls. There are no mobile carriers at the surface, so the surface still cannot conduct.
Inversion \((V_G > V_T)\). Raise the gate voltage further and the bands bend far enough that the surface, though physically p-type, has more electrons in it than holes. Those electrons come from thermal generation and from the source and drain diffusions of a real transistor, and they form a thin conducting sheet at the surface — an inversion layer, or channel, of n-type material inside p-type silicon. The convention is to call the surface strongly inverted when the electron concentration at the surface equals the hole concentration in the bulk, which happens when the bands have bent by \(2\phi_F\), where
The bulk Fermi potential of Chapter 3, measured from the intrinsic level. For \(N_A = 3\times10^{17}\ \text{cm}^{-3}\) and \(n_i = 10^{10}\ \text{cm}^{-3}\) at 300 K, \(\phi_F = 0.02585\ln(3\times10^{7}) = 0.4451\) V, so strong inversion needs \(2\phi_F = 0.8902\) V of band bending.
Once strong inversion is reached the depletion region stops growing. Any further gate charge is balanced by additional electrons in the inversion layer rather than by additional ionised acceptors, because the inversion charge responds exponentially to surface potential while the depletion charge responds only as a square root. The depletion region is therefore frozen at its maximum width
and this is the single most important fact about the MOS structure: beyond threshold, the gate talks to the mobile channel charge and to nothing else. The device becomes linear in \((V_{GS}-V_T)\), and the whole family of drain-current equations follows.
2 Threshold Voltage, and What Sets It
The threshold voltage is the gate-to-source voltage at which strong inversion is reached. It is not a fundamental constant but the sum of four contributions, each of which a process engineer can adjust:
Reading left to right: the work-function difference between gate and substrate; the correction for charge trapped in the oxide; the band bending required for strong inversion; and the voltage needed to support the depletion charge that has already appeared before inversion starts.
Each term deserves a sentence. The work-function difference \(\phi_{ms}\) exists because the gate and the silicon have different Fermi levels when isolated, so a contact potential appears when they are joined, exactly as it did at the junction of Chapter 5. Choosing an n\(^{+}\) polysilicon gate rather than a p\(^{+}\) one shifts \(V_T\) by about 1.1 V, which is why gate doping is a design variable. The fixed oxide charge \(Q_f\) is a positive charge, mostly incompletely oxidised silicon, sitting within about 2 nm of the interface; it is always positive, so it always makes \(V_T\) more negative, and reducing it from the \(10^{12}\ \text{cm}^{-2}\) of early processes to the \(10^{10}\) of a modern one was what made stable n-channel MOS possible at all. The bulk term \(2\phi_F\) is fixed by the doping. And the depletion term is simply \(Q_{dep}/C_{ox}\), the voltage dropped across the oxide by the depletion charge underneath it.
Take a substrate doping \(N_A = 3\times10^{17}\ \text{cm}^{-3} = 3\times10^{23}\ \text{m}^{-3}\), an oxide thickness \(t_{ox} = 10\) nm, an n\(^{+}\) polysilicon gate, and a fixed oxide charge equivalent to \(10^{11}\) elementary charges per cm\(^2\). Use \(\varepsilon_{ox} = 3.9\varepsilon_0\), \(\varepsilon_s = 11.7\varepsilon_0\), \(n_i = 10^{10}\ \text{cm}^{-3}\) and \(kT/q = 25.85\) mV.
Oxide capacitance.
Bulk potential and depletion charge. \(\phi_F = 0.02585\ln(3\times10^{23}/10^{16}) = 0.4451\) V, so \(2\phi_F = 0.8902\) V, and
so \(Q_{dep}/C_{ox} = 2.977\times10^{-3}/3.453\times10^{-3} = 0.8622\) V.
Flat-band voltage. For an n\(^{+}\) gate on p-type silicon the work-function difference is approximately \(-(E_g/2q + \phi_F) = -(0.56 + 0.4451) = -1.0051\) V. The fixed charge is \(Q_f = 10^{11}\times10^{4}\times1.602\times10^{-19} = 1.602\times10^{-4}\ \text{C/m}^2\), so \(Q_f/C_{ox} = 0.0464\) V and
Threshold.
A comfortably positive threshold, so the device is off with its gate grounded — an enhancement-mode transistor. Notice how nearly the three terms cancel: a change of a tenth of a volt in any one of them is a fifteen per cent change in \(V_T\). That is why threshold control is the hardest part of a MOS process, and why a shallow ion implant into the channel — a \(V_T\)-adjust implant, which adds a further \(qN_{imp}/C_{ox}\) term — is used on every commercial line to trim the result.
Two design levers follow immediately from the formula. Thinning the oxide raises \(C_{ox}\), which shrinks both the \(Q_f\) and \(Q_{dep}\) terms and pulls \(V_T\) towards \(\phi_{ms} + 2\phi_F\); with the same doping and a 20 nm oxide the same process would give \(V_{T0} = 1.52\) V. Raising the substrate doping raises both \(2\phi_F\) and \(Q_{dep}\) and so raises \(V_T\) strongly; at \(N_A = 10^{18}\ \text{cm}^{-3}\), \(V_{T0}\) would be 1.50 V. The two levers are used together, because doping also controls the source and drain depletion widths and therefore how short the channel may be made.
3 The Enhancement MOSFET: Gradual Channel, Triode and Saturation
Add an n\(^{+}\) source and an n\(^{+}\) drain either side of the gate, and the capacitor becomes a transistor. With \(V_{GS} < V_T\) there is no inversion layer, so source and drain are two back-to-back diodes and no current flows. With \(V_{GS} > V_T\) the inversion layer connects them, and a drain voltage drives a current along it. The channel has been enhanced into existence, which is where the name comes from.
The current follows from what is called the gradual-channel approximation: assume the field perpendicular to the channel, set by the gate, is much larger than the field along it, set by the drain, so the inversion charge at any point \(y\) along the channel can be computed as though that point were an isolated MOS capacitor. If the channel potential there is \(V(y)\), the local gate-to-channel voltage is \(V_{GS}-V(y)\) and the inversion charge per unit area is
The drift current carried by that sheet is \(I_D = W|Q_n|\mu_n E = W\mu_nC_{ox}[V_{GS}-V-V_T]\,dV/dy\). Since \(I_D\) is the same everywhere along the channel, integrate from source to drain:
The triode, or ohmic, equation. It is valid as long as the channel exists over the whole of its length, that is for \(V_{DS} \le V_{GS}-V_T\).
For very small \(V_{DS}\) the quadratic term is negligible and \(I_D \propto V_{DS}\): the device is a resistor of value
controlled by the gate. This is the switching mode of Chapter 23 and the voltage-variable resistor of Chapter 24. For our process with \(\mu_n = 400\ \text{cm}^2/\text{V}\,\text{s}\), \(k_n' = \mu_nC_{ox} = 138.1\ \mu\text{A/V}^2\), and with \(W/L = 20\) and \(V_{GS} = 3\) V the on-resistance is \(1/[138.1\ \mu \times 20 \times 2.299] = 157.5\ \Omega\); raising \(V_{GS}\) to 5 V lowers it to 84.2 Ω. The way to a low on-resistance is a wide device driven hard, and Chapter 23 shows what a power MOSFET does about it.
As \(V_{DS}\) rises, the gate-to-channel voltage at the drain end, \(V_{GS}-V_{DS}\), falls, so the inversion charge there thins. When \(V_{DS} = V_{GS}-V_T\) it reaches zero: the channel is pinched off at the drain, exactly as in the JFET though by an entirely different mechanism. Beyond that point the extra drain voltage is dropped across the short pinched-off region and the current saturates. Substituting \(V_{DS} = V_{GS}-V_T\) into the triode equation gives
for \(V_{DS} \ge V_{GS}-V_T\). The constant \(k = \tfrac12 k_n'(W/L)\) is the only thing that distinguishes one device from another on a given process, and it is set by a drawn geometry, so it is under the designer's control to within a per cent or two. For our example, \(k = \tfrac12(138.1\ \mu)(20) = 1.381\ \text{mA/V}^2\), giving \(I_D = 2.33\) mA at \(V_{GS} = 2\) V and 7.30 mA at \(V_{GS} = 3\) V. Differentiating gives \(g_m = 2k(V_{GS}-V_T) = 2\sqrt{kI_D}\), so \(g_m = 6.35\) mS at \(V_{GS} = 3\) V.
The form of the result deserves attention. It is the same square law as Shockley's equation for the JFET, but written about a positive threshold rather than a negative pinch-off, and with the multiplying constant \(k\) set by geometry rather than by an uncontrollable channel thickness. That single difference is why MOSFETs can be matched to a fraction of a per cent on the same die while JFETs cannot, and it is the reason integrated analogue circuits are built from MOSFETs.
On the process of Worked Example 22.1 (\(k_n' = 138.1\ \mu\text{A/V}^2\), \(V_T = 0.701\) V, minimum drawn length \(L = 0.5\ \mu\text{m}\)), design a transistor to pass 5 mA in saturation at \(V_{GS} = 2.5\) V.
The overdrive is fixed by the specification: \(V_{GS}-V_T = 2.5 - 0.701 = 1.799\) V. The required \(k\) follows from the square law,
Take \(W/L = 22\), so \(W = 11\ \mu\text{m}\) at the minimum length. Then \(k = \tfrac12(138.1\ \mu)(22) = 1.519\ \text{mA/V}^2\), the actual current is \(1.519(1.799)^2 = 4.918\) mA, and the transconductance is \(g_m = 2k(V_{GS}-V_T) = 5.467\) mS. The same device used as a switch with 5 V on its gate has \(R_{DS(\text{on})} = 1/[138.1\ \mu(22)(4.299)] = 76.6\ \Omega\), and its gate capacitance is \(C_{ox}WL = 3.453\ \text{fF}/\mu\text{m}^2 \times 5.5\ \mu\text{m}^2 = 19.0\) fF. Those last two numbers are in direct conflict — widening the device to halve the on-resistance doubles the gate capacitance and therefore doubles the charge the driver must move — and Chapter 23 shows that the conflict is exactly what sets the optimum size of a power switch.
4 Depletion-Mode and p-Channel Devices
The enhancement device has no channel until one is created. A depletion-mode MOSFET is made by implanting a thin n-type layer between source and drain during manufacture, so a channel is physically present with the gate at zero volts. The gate then does what the JFET's gate did: a negative gate voltage repels electrons out of the implanted channel and depletes it, reducing the current, and cut-off occurs at some negative \(V_{GS(\text{off})}\).
But because the gate is insulated it can also be driven positive without any junction conducting, and a positive gate attracts more electrons into the channel and increases the current beyond its zero-bias value. The depletion MOSFET is therefore the only one of the three FETs that works in both directions about \(V_{GS} = 0\), and its transfer characteristic is the same parabola as the JFET's but extended into the first quadrant:
Shockley's equation again, now valid for \(V_{GS} > 0\) as well. For a device with \(I_{DSS} = 10\) mA and \(V_{GS(\text{off})} = -5\) V: \(I_D = 3.6\) mA at \(V_{GS} = -2\) V, 10.0 mA at 0 V, 14.4 mA at \(+1\) V and 19.6 mA at \(+2\) V.
That extension is genuinely useful. A depletion MOSFET can be self-biased with a source resistor exactly as in Section 4 of Chapter 21, or it can be biased at \(V_{GS} = 0\) with the gate tied straight to the source, which needs no bias components at all and gives \(I_D = I_{DSS}\) with a transconductance of \(g_{m0}\). Tying gate to source also turns the device into a two-terminal current regulator diode, which is what the constant-current diodes in a data book actually are.
p-channel devices. Build the same structures on an n-type substrate with p\(^{+}\) source and drain, and the channel is a layer of holes. Every voltage and every current reverses: \(V_{GS}\), \(V_{DS}\) and \(V_T\) are all negative for a p-channel enhancement device, and the drain current flows out of the drain terminal. The equations are unchanged if magnitudes are used throughout — \(I_D = k(|V_{GS}|-|V_T|)^2\) in saturation, and the saturation condition becomes \(|V_{DS}| \ge |V_{GS}|-|V_T|\).
The one asymmetry that cannot be argued away is mobility. Hole mobility in the inversion layer is roughly \(0.4\) times electron mobility, so for the same geometry, oxide and overdrive a p-channel device carries about \(40\) per cent of the current and has about \(40\) per cent of the transconductance. In CMOS design this is corrected by drawing the p-channel device between two and three times as wide as its n-channel partner, which is why the p-type transistors in a die photograph are the visibly larger ones and why a CMOS inverter is not physically symmetrical even when it is electrically so.
5 Channel-Length Modulation, the Body Effect and Subthreshold Conduction
The square law and the triode equation describe an idealised device. Three departures from it matter in practice, and each corresponds to an assumption made silently in Section 3.
Channel-length modulation. Section 3 assumed that beyond pinch-off all the extra drain voltage appears across a region of zero length, so the current is exactly constant. In fact the pinch-off point moves back towards the source as \(V_{DS}\) rises, shortening the effective channel from \(L\) to \(L - \Delta L\), and since \(I_D \propto 1/L\) the current rises. The effect is modelled empirically by
The exact analogue of the Early effect of Chapter 17, with \(V_A = 1/\lambda\) playing the part of the Early voltage. With \(\lambda = 0.02\ \text{V}^{-1}\), \(V_A = 50\) V, and a device biased at \(V_{GS} = 3\) V has \(I_D\) rising from 7.593 mA at \(V_{DS} = 2\) V to 8.761 mA at \(V_{DS} = 10\) V — a 15 per cent rise — corresponding to \(r_d = 1/(0.02\times7.301\ \text{mA}) = 6.85\ \text{k}\Omega\). Because \(\Delta L\) is a fixed physical distance, \(\lambda\) is inversely proportional to \(L\): a short-channel device has a much larger \(\lambda\), a much smaller \(r_d\) and therefore a much lower maximum voltage gain, which is one of the standing frustrations of analogue design in a scaled process.
The body effect. Section 2 computed \(V_T\) assuming the source and the substrate are at the same potential. They often are not: in an integrated circuit all the n-channel devices share one p-type substrate, tied to the most negative rail, while their sources sit at whatever the circuit puts them. A source that is positive with respect to the body reverse biases the source-body junction, which widens the depletion region under the channel, increases \(Q_{dep}\), and therefore raises the gate voltage needed to reach inversion. Replacing \(2\phi_F\) by \(2\phi_F + V_{SB}\) in the depletion-charge term gives
For the process of Worked Example 22.1, the body-effect coefficient is
A source-follower stage puts its source 2 V above the substrate. Then
so \(V_T\) rises from 0.701 V to 1.392 V — it has doubled. For a device biased with \(V_{GS} = 3\) V the overdrive therefore falls from 2.299 V to 1.608 V and the drain current from 7.301 mA to 3.570 mA, a fall of 51 per cent. Push the source to 4 V above the body and the shift is 1.159 V, \(V_T = 1.860\) V, and the current is down to 1.796 mA, a quarter of its original value. Nothing about the gate has changed; the transistor has been throttled entirely from underneath.
The practical consequences are three. Wherever it is possible, tie each source to its own body — discrete MOSFETs are made this way, with the body bonded internally to the source, which is also what creates the body diode discussed in Chapter 23. In an integrated circuit that is only possible for devices in their own well, so p-channel devices in an n-well escape the effect and n-channel devices in a common substrate do not. And a source follower, whose source moves with the signal, suffers a \(V_T\) that moves with the signal too, which turns the body effect into distortion and limits the gain of a MOS follower to about 0.8 even when \(g_mR_S\) is large.
Subthreshold conduction. The square law says \(I_D = 0\) for \(V_{GS} < V_T\). It is not. Below threshold the surface is weakly inverted, the channel charge depends exponentially rather than quadratically on surface potential, and the current is a diffusion current very like the bipolar transistor's:
\(S\) is the subthreshold swing, the gate voltage change needed to alter the current by a factor of ten. The factor \(n = 1 + C_{dep}/C_{ox}\) lies between about 1.2 and 2. With \(n = 1.5\), \(S = 2.3(1.5)(25.85\ \text{mV}) = 89.3\) mV per decade.
That number is a hard physical limit — no ordinary MOSFET can switch off faster than about 60 mV per decade at room temperature, the \(n=1\) value — and it governs digital design far more than most students expect. A transistor 0.35 V below threshold conducts \(10^{-3.9}\), that is one part in 8300, of its threshold current: negligible for one device, but a chip with a billion of them turned off leaks a hundred thousand times the current of a single one. It also explains why supply voltages stopped falling around 1 V: \(V_T\) cannot be reduced without an exponential penalty in standby leakage, and \(V_{DD}\) cannot fall far below \(V_T\) without losing all the speed. In analogue design the same region is used deliberately, since a MOSFET biased in weak inversion has the exponential characteristic and the high \(g_m/I_D\) of a bipolar transistor at a nanoamp of current.
6 Comparing the Three Families, and Handling the Oxide
Three FET families have now appeared, and the table gathers them together. All three obey a square law, all three have \(g_m\) proportional to \(\sqrt{I_D}\), and all three have the same three-terminal small-signal model that Chapter 24 will build. They differ in where the transfer curve begins and in what the gate is made of.
| n-channel JFET | n-channel D-MOSFET | n-channel E-MOSFET | |
|---|---|---|---|
| Gate isolation | reverse-biased pn junction | SiO\(_2\), typically 10–100 nm | SiO\(_2\), typically 2–100 nm |
| Channel at \(V_{GS}=0\) | present | present (implanted) | absent |
| Useful \(V_{GS}\) range | \(V_P \le V_{GS} \le 0\) only | either polarity | \(V_{GS} > V_T\) only |
| Transfer equation | \(I_{DSS}(1-V_{GS}/V_P)^2\) | \(I_{DSS}(1-V_{GS}/V_{GS(\text{off})})^2\) | \(k(V_{GS}-V_T)^2\) |
| Gate current | \(\sim1\) nA, doubling every 10 °C | \(\sim1\) pA, essentially temperature-independent | \(\sim1\) pA |
| Input capacitance | a few pF | a few pF (small signal) to nF (power) | a few pF to nF |
| Typical worked device | \(I_{DSS}=12\) mA, \(V_P=-4\) V, \(g_{m0}=6.0\) mS | \(I_{DSS}=10\) mA, \(V_{\text{off}}=-5\) V, \(g_{m0}=4.0\) mS | \(V_T=0.70\) V, \(k=1.381\) mA/V\(^2\), \(g_m=6.35\) mS at 3 V |
| Simplest bias | self bias, gate to ground | gate tied to source: \(I_D=I_{DSS}\) | drain feedback or divider (Chapter 23) |
| Chiefly used for | low-noise high-impedance front ends | RF amplifiers, current regulator diodes | everything digital; all power switching |
The last row is not a small point. The enhancement MOSFET is the only one of the three that is off when its gate is at zero volts, and that single property is what makes CMOS logic possible: a gate that draws no static current and is off by default. The other two families are specialities. The industry makes perhaps a billion depletion MOSFETs a year and something like \(10^{20}\) enhancement ones.
Silicon dioxide breaks down at a field of roughly \(10^{9}\) V/m, that is 10 MV/cm. A 10 nm oxide therefore fails at about \(10^{9}\times10\times10^{-9} = 10\) V, which is why a small-signal MOSFET is rated at \(\pm 20\) V on its gate and a fine-geometry logic device at less than 2 V. Because no current flows into the gate, there is nothing to discharge a static charge that arrives there, and the breakdown is instantaneous and permanent — a punched-through oxide is a short circuit, not a recoverable fault.
The numbers make the danger clear. The gate of a device with \(W = 10\ \mu\text{m}\) and \(L = 0.5\ \mu\text{m}\) has a capacitance of \(C_{ox}WL = 17.3\) fF. A human body walking across a carpet is modelled as 100 pF charged to 2 kV, holding 200 nC and 200 µJ. Bringing that to a floating gate would put over a kilovolt across ten nanometres of glass. Hence every precaution: conductive foam or shorting rings on the leads in storage, wrist straps and grounded work surfaces, soldering irons with earthed bits, and the gate lead soldered first and unsoldered last so it is never the floating terminal. Modern devices include integral gate protection — back-to-back Zener diodes to source, which clamp at about 15 V — and these make ordinary handling safe but add leakage and capacitance, which is why the very lowest-noise and highest-impedance parts still omit them and are supplied with their leads shorted together.
Chapter 23 takes the enhancement device of Section 3 and does two things with it. It places a Q-point in the saturation region, using the same graphical and algebraic machinery as Chapter 21, and then it abandons the Q-point entirely and drives the same transistor between cut-off and the triode region as a switch — which is what the overwhelming majority of the MOSFETs ever manufactured actually do.
7 Summary and Key Results
| Quantity | Expression | Value |
|---|---|---|
| Oxide capacitance | \(C_{ox} = \varepsilon_{ox}/t_{ox}\) | 3.453 fF/µm\(^2\) |
| Bulk potential | \(\phi_F = (kT/q)\ln(N_A/n_i)\) | 0.4451 V; \(2\phi_F = 0.8902\) V |
| Maximum depletion width | \(W_{d(\max)} = \sqrt{2\varepsilon_s(2\phi_F)/qN_A}\) | 61.9 nm |
| Flat-band voltage | \(V_{FB} = \phi_{ms} - Q_f/C_{ox}\) | \(-1.0051 - 0.0464 = -1.0515\) V |
| Threshold voltage | \(V_{T0} = V_{FB} + 2\phi_F + Q_{dep}/C_{ox}\) | \(-1.0515 + 0.8902 + 0.8622 = 0.7009\) V |
| Process transconductance | \(k_n' = \mu_nC_{ox}\); \(k = \tfrac12 k_n'(W/L)\) | 138.1 µA/V\(^2\); \(k = 1.381\) mA/V\(^2\) |
| Triode current | \(2k[(V_{GS}-V_T)V_{DS} - V_{DS}^2/2]\) | 1.781 mA at \(V_{GS}=3\) V, \(V_{DS}=0.3\) V |
| On-resistance | \(1/[k_n'(W/L)(V_{GS}-V_T)]\) | 157.5 Ω at \(V_{GS}=3\) V; 84.2 Ω at 5 V |
| Saturation current | \(I_D = k(V_{GS}-V_T)^2\) | 2.331 mA at 2 V; 7.301 mA at 3 V |
| Transconductance | \(g_m = 2k(V_{GS}-V_T) = 2\sqrt{kI_D}\) | 3.589 mS at 2 V; 6.351 mS at 3 V |
| Channel-length modulation | \(I_D(1+\lambda V_{DS})\); \(r_d = 1/\lambda I_D\) | \(\lambda = 0.02\): \(V_A = 50\) V, \(r_d = 6.85\) kΩ at 7.30 mA |
| Body effect | \(\Delta V_T = \gamma(\sqrt{2\phi_F+V_{SB}}-\sqrt{2\phi_F})\) | \(\gamma = 0.914\ \text{V}^{1/2}\); \(V_{SB}=2\) V gives \(+0.691\) V, \(V_T = 1.392\) V |
| Subthreshold swing | \(S = 2.3\,n\,kT/q\) | 89.3 mV/decade at \(n=1.5\); 59.5 mV/decade is the \(n=1\) limit |
| Oxide breakdown | \(E_{bd} \approx 10\) MV/cm | 10 nm oxide fails near 10 V; gate rated \(\pm20\) V |
8 Common Mistakes
Both equations are quadratic and both look plausible for any pair of voltages, so an unchecked substitution gives a wrong answer without any warning. At \(V_{GS} = 3\) V and \(V_{DS} = 0.3\) V the device of this chapter passes \(2k[(2.299)(0.3) - 0.045] = 1.781\) mA; the saturation formula would have claimed 7.301 mA, four times too much. The discipline is to compute the overdrive \(V_{GS}-V_T\) first, compare it with \(V_{DS}\), and only then choose an equation. It is worth noticing that the two agree exactly at the boundary, \(V_{DS} = V_{GS}-V_T\), which is a useful arithmetic check on any answer near the knee.
In a discrete MOSFET it is, because the manufacturer bonds it internally. In an integrated circuit it is tied to a rail, and any device whose source sits above that rail has a raised threshold. A student who analyses a MOS source follower or the upper device of a stacked pair using \(V_{T0}\) will predict a gain and an operating current that the circuit does not have: in Worked Example 22.3, 2 V of \(V_{SB}\) doubled \(V_T\) and halved the drain current. The symptom in a simulation is a follower whose output sits a volt lower than expected and whose gain is 0.8 rather than the 0.95 the small-signal algebra predicts, and the cause is that \(V_T\) is a function of the output voltage.
It conducts, exponentially, at about a decade per 90 mV. That is unimportant for one small-signal device, where 0.35 V of margin gives a current 8300 times smaller than the threshold current, and decisive for a memory array or a battery-powered chip where a billion such devices sit in parallel. It also matters at temperature, since the subthreshold swing is proportional to \(kT/q\) and the threshold voltage falls by roughly 2 mV per degree, so leakage at 100 °C can be a hundred times its value at 25 °C. Treating the square law as literally true below threshold, and therefore predicting zero standby current, is the commonest source of wildly optimistic power estimates.
9 Chapter Review
1. An n-channel enhancement MOSFET has \(V_T = 1.2\) V and \(k = 0.8\ \text{mA/V}^2\). Find \(I_D\) and state the region of operation for (a) \(V_{GS} = 1.0\) V, \(V_{DS} = 5\) V; (b) \(V_{GS} = 3.2\) V, \(V_{DS} = 1.0\) V; (c) \(V_{GS} = 3.2\) V, \(V_{DS} = 6\) V. Then find \(g_m\) in case (c).
In every case compute the overdrive first. (a) \(V_{GS} - V_T = 1.0 - 1.2 = -0.2\) V, which is negative: the device is below threshold and is cut off, with \(I_D\) equal to the subthreshold leakage, of the order of nanoamps rather than zero. (b) The overdrive is \(3.2 - 1.2 = 2.0\) V and \(V_{DS} = 1.0\) V is less than that, so the device is in the triode region: \(I_D = 2k[(V_{GS}-V_T)V_{DS} - V_{DS}^2/2] = 2(0.8)[(2.0)(1.0) - 0.5] = 1.6(1.5) = 2.40\) mA. Note that the effective drain-source resistance here is \(1.0/2.40\ \text{mA} = 417\ \Omega\), considerably more than the small-signal value \(1/[2k(V_{GS}-V_T)] = 1/3.2\ \text{mS} = 313\ \Omega\), because \(V_{DS}\) is not small. (c) The overdrive is still 2.0 V and \(V_{DS} = 6\) V exceeds it, so the device is in saturation: \(I_D = k(V_{GS}-V_T)^2 = 0.8(4.0) = 3.20\) mA. Finally \(g_m = 2k(V_{GS}-V_T) = 2(0.8)(2.0) = 3.20\) mS, which can be checked from the other form, \(2\sqrt{kI_D} = 2\sqrt{0.8\times3.20} = 3.20\) mS.
2. Explain physically why the depletion region under the gate stops widening once strong inversion is reached, and why this makes the drain current a linear function of \((V_{GS}-V_T)\) rather than a square root of it.
Below threshold the only charge available to balance the gate is the fixed acceptor charge exposed by pushing holes away, and exposing more of it means depleting deeper. Since the depletion charge grows only as the square root of the band bending — \(Q_{dep} = \sqrt{2q\varepsilon_sN_A\psi_s}\) — a large increase in gate voltage produces only a modest increase in charge, and the surface potential climbs steadily. Once the surface potential reaches \(2\phi_F\) the picture changes, because the electron concentration at the surface depends exponentially on surface potential: a further 60 mV of band bending multiplies the inversion charge by ten. So an exponentially responsive reservoir of mobile charge has become available, and it supplies whatever the gate demands with a negligible further change in surface potential. The potential is therefore pinned at approximately \(2\phi_F\), and since the depletion width depends only on the surface potential, the depletion width is pinned too, at \(W_{d(\max)} = 61.9\) nm for the process worked here. The consequence for the drain current is direct. Above threshold, all of the incremental gate charge goes into the inversion layer, so \(|Q_n| = C_{ox}(V_{GS}-V_T)\) exactly — a linear relation with no square root in it, because the awkward square-root term has been frozen into the constant \(V_T\). The drain current is that charge times its velocity, and the square law of the saturation region comes from integrating along a channel whose charge falls linearly from source to drain, not from the depletion physics at all.
3. A MOS process has \(t_{ox} = 20\) nm and \(N_A = 5\times10^{17}\ \text{cm}^{-3}\), with an n\(^{+}\) poly gate and negligible fixed charge. Compute \(C_{ox}\), \(\phi_F\), \(V_{T0}\) and \(\gamma\), and comment on whether this device would be usable in a 3.3 V logic family.
The oxide capacitance is \(C_{ox} = 3.9(8.854\times10^{-12})/(20\times10^{-9}) = 1.727\times10^{-3}\ \text{F/m}^2\), half that of the 10 nm process because capacitance is inversely proportional to thickness. The bulk potential is \(\phi_F = 0.02585\ln(5\times10^{23}/10^{16}) = 0.4583\) V, so \(2\phi_F = 0.9166\) V. The depletion charge is \(Q_{dep} = \sqrt{2(1.602\times10^{-19})(1.036\times10^{-10})(5\times10^{23})(0.9166)} = 3.901\times10^{-3}\ \text{C/m}^2\), giving \(Q_{dep}/C_{ox} = 2.259\) V — more than double the earlier value, because the doping is higher and the capacitance lower, and both changes push the same way. With negligible fixed charge, \(V_{FB} = \phi_{ms} = -(0.56+0.4583) = -1.018\) V, so \(V_{T0} = -1.018 + 0.9166 + 2.259 = 2.157\) V. The body-effect coefficient is \(\gamma = \sqrt{2q\varepsilon_sN_A}/C_{ox} = 2.360\ \text{V}^{1/2}\), which is very large. This device is not usable in a 3.3 V family. A threshold of 2.16 V leaves only 1.14 V of overdrive at the full rail, so the drive current is small, the on-resistance high and the gate delay long; worse, any device whose source is lifted even 1 V above the substrate acquires \(\Delta V_T = 2.360(\sqrt{1.9166}-\sqrt{0.9166}) = 1.008\) V and has essentially no overdrive left. The fixes are the two levers of Section 2: thin the oxide, which reduces both the depletion term and \(\gamma\) proportionally, and reduce the substrate doping or add a \(V_T\)-adjust implant of the opposite type. A 10 nm oxide alone would bring \(V_{T0}\) to 1.03 V and \(\gamma\) to 1.18 V\(^{1/2}\), which is workable.
4. Compare the depletion MOSFET with the JFET as amplifying devices, and explain why the depletion MOSFET is nevertheless a rarity while the enhancement MOSFET is not.
As amplifiers they are nearly interchangeable. Both have a channel at zero gate bias, both obey the same square law, both give \(g_m = g_{m0}(1 - V_{GS}/V_{\text{off}})\), and both are biased by the identical self-bias and divider-bias circuits of Chapter 21 — the graphical construction of Figure 21.4 applies to a depletion MOSFET without a single change. The depletion MOSFET is better in three respects: its gate current is a picoamp rather than a nanoamp and does not double with temperature, so its input resistance survives to 150 °C; its gate may be driven positive, which extends the usable transfer curve into the first quadrant and raises the achievable \(g_m\) for a given device; and it can be biased with gate tied directly to source, needing no bias network at all. The JFET's compensating advantage is noise: a junction gate has no oxide interface, and interface states are the source of the flicker noise that dominates MOSFET performance below a few kilohertz, so a JFET input stage is still preferred for low-frequency low-noise work. The reason the depletion MOSFET is nevertheless rare is that it is normally on, and being normally on is a disqualification in the two applications that consume nearly all transistors. In logic, a device that conducts with its gate at zero volts cannot form a CMOS gate, which draws no static current precisely because both devices are off at the rails. In power switching, a normally-on device is a hazard, since a failure of the gate drive turns the switch on rather than off. Both of those want an enhancement device, and the market for the depletion type is confined to RF amplifiers, constant-current diodes and a few start-up circuits where being normally on is exactly the wanted property.
5. A 10 nm gate oxide is rated for continuous operation at 10 MV/cm with a maximum gate voltage of \(\pm20\) V quoted only because of the internal protection diodes. A technician measures a device on the bench with an unearthed soldering iron carrying 30 V of leakage. Estimate the field in the oxide and explain what the protection circuit does and does not do.
The field is simply the voltage divided by the thickness: \(E = 30\ \text{V}/(10\times10^{-9}\ \text{m}) = 3\times10^{9}\) V/m, that is 30 MV/cm, three times the breakdown field. The oxide punches through at once, and since breakdown in an oxide is destructive rather than reversible — a filament of silicon is formed through the glass — the device is permanently shorted from gate to channel. It is worth putting the number the other way round: the oxide survives up to \(10^{9}\times10\times10^{-9} = 10\) V of gate-source voltage on its own, so even the \(\pm20\) V data-sheet rating is an assertion about the protection network rather than about the oxide. The integral protection is a pair of back-to-back Zener diodes from gate to source, which conduct when the gate exceeds about \(\pm15\) V and clamp it there. What they do is absorb the modest energy of an electrostatic discharge from a person or a workbench: the human-body model of 100 pF at 2 kV stores \(\tfrac12CV^2 = 200\ \mu\text{J}\), and a clamp that limits the voltage to 15 V while passing the resulting current for a microsecond dissipates that harmlessly. What they do not do is protect against a continuous overvoltage from a low-impedance source: a leaky soldering iron, a supply rail connected to the wrong pin, or a signal generator set to 30 V will simply drive current through the clamp until it or the oxide fails. The protection network is also not free — it adds a few picofarads of input capacitance and a leakage current of the order of a nanoamp, which is why the highest-impedance electrometer parts omit it and are shipped with a shorting spring across the leads instead.