By the end of this chapter you should be able to:
- Describe the structure of an n-channel JFET and explain why the gate current is of the order of a nanoamp.
- Explain channel narrowing, locate the pinch-off voltage \(V_P\), and distinguish the ohmic region from the saturation region on the drain characteristic.
- State and use Shockley's equation, and derive \(g_m = g_{m0}(1 - V_{GS}/V_P)\) from it.
- Analyse fixed, self and voltage-divider bias both algebraically and by the graphical intersection of the bias line with the transfer curve.
- Explain why self bias is inherently degenerative and quantify how much device spread each scheme removes.
- Choose a bias scheme for a given specification and justify it against the equivalent BJT design of Chapter 18.
Chapters 16 to 20 built an amplifier out of a device that works by injecting minority carriers across a forward-biased junction. Everything good about the bipolar transistor and everything awkward about it follows from that one fact. The good part is a transconductance of 77 mS at 2 mA, which no other three-terminal device of comparable size comes close to. The awkward part is that the control terminal is a forward-biased diode: it draws current, it loads whatever drives it, its \(V_{BE}\) drifts by \(-2\) mV per degree, and \(\beta\) varies by three to one between two devices out of the same bag.
The junction field-effect transistor answers a different question. Suppose we keep the controlling junction reverse biased, so that it draws essentially no current at all, and use the depletion region it creates to squeeze a conducting channel rather than to inject anything into it. The gate then behaves as a capacitor rather than as a diode, the input resistance rises from tens of kilohms to tens of gigohms, and the drain current becomes a function of gate voltage alone. That is the JFET, and this chapter develops it from the geometry of the depletion region up to three biasing schemes, each worked as a full design with both an algebraic and a graphical solution. The device is less good at amplifying than the bipolar transistor of Chapter 19 and very much better at not disturbing what it is measuring, and the whole of Part 5 is an exploration of that trade.
1 Structure, and Why the Gate Draws No Current
Take a bar of n-type silicon with an ohmic contact at each end. One end is called the source, because electrons enter the bar there; the other is the drain, because they leave there. On its own the bar is just a resistor, and if the bar is \(L\) long, \(W\) wide and \(2a\) thick with donor density \(N_D\), Chapter 4 gives its resistance as \(L/(q\mu_n N_D \cdot 2aW)\). Now diffuse a heavily doped p\(^{+}\) region into the top face and another into the bottom face, and connect the two together. That is the gate, and the device is complete.
What has been added is two pn junctions, one on each face of the bar, arranged so that their depletion regions eat into the channel from both sides. Chapter 5 showed that the depletion region of an asymmetrically doped junction lies almost entirely in the lightly doped side, so essentially the whole of each depletion layer sits inside the n-channel and none of it inside the p\(^{+}\) gate. Chapter 5 also gave the width of that layer as
The depletion width grows as the square root of the reverse bias. Squeezing the channel is therefore something we do with a voltage, and the square root is the origin of the square law that dominates the rest of this chapter.
The device is operated with the gate junction reverse biased at all times: for an n-channel JFET that means \(V_{GS} \le 0\). The current that flows in a reverse-biased silicon junction is the saturation current of Chapter 6, and for the small junction areas involved it is of the order of a nanoamp. A typical data sheet quotes \(I_{GSS} = 1\) nA at \(V_{GS} = -20\) V, which is a d.c. input resistance of
The comparison with the bipolar transistor is stark. A BJT biased at \(I_C = 2\) mA with \(\beta = 100\) draws 20 µA of base current, and its d.c. input resistance \(V_{BE}/I_B\) is 35 kΩ. The JFET's is six hundred thousand times larger. Nothing in an electrometer, a pH meter, a charge amplifier for a piezoelectric sensor or the front end of an oscilloscope probe could be built with the bipolar device without an elaborate bias-current cancellation scheme; with a JFET it needs no scheme at all.
Reverse saturation current is thermally generated, so it roughly doubles for each 10 °C rise, exactly as the diode leakage of Chapter 6 did. The 1 nA quoted at 25 °C becomes \(1\ \text{nA}\times 2^{12.5} = 5.79\ \mu\text{A}\) at 150 °C, and the input resistance collapses from 20 GΩ to 3.45 MΩ. A gate resistor of 10 MΩ that develops 10 µV of offset at room temperature develops 58 V of offset at 150 °C — which is to say the circuit stops working entirely. The rule that follows is that \(R_G\) is chosen from the highest operating temperature, not from the specification at 25 °C.
Two further consequences of the structure are worth noting now. First, the JFET is a majority-carrier device: the current in the channel is carried by electrons drifting from source to drain, and no minority carrier is injected anywhere. Minority-carrier storage was what limited the switching speed of the bipolar transistor and what produced its recovery time, so the JFET has neither. Second, because both gate regions are tied together and both deplete the channel, the two depletion layers approach each other from above and below, and the channel is squeezed symmetrically. It is the point at which they meet that gives the device its most important parameter.
2 Pinch-Off, and the Two Regions of Operation
Start with \(V_{GS} = 0\) and raise \(V_{DS}\) from zero. At first the channel behaves as the resistor it is, and \(I_D\) rises in proportion to \(V_{DS}\). But the drain current itself produces an ohmic drop along the channel, so the channel is no longer at one potential: the source end sits at 0 V and the drain end at \(V_{DS}\). The gate is at 0 V, so the reverse bias across the gate junction is nearly zero at the source end and equal to \(V_{DS}\) at the drain end. The depletion layers therefore taper, thin at the source and thick at the drain, which is the middle panel of Figure 21.1.
As \(V_{DS}\) rises further the drain end of the channel gets narrower, its resistance rises, and the characteristic bends over. At some particular \(V_{DS}\) the two depletion layers meet at the drain end. This is pinch-off, and the value of \(V_{DS}\) at which it happens with \(V_{GS} = 0\) defines the pinch-off voltage \(V_P\). For the device used throughout this chapter, \(V_P = -4\) V, which by the sign convention explained below means that pinch-off occurs at \(V_{DS} = 4\) V when \(V_{GS} = 0\).
The obvious expectation — that closing the channel stops the current — is wrong, and it is worth being clear about why. The channel does not close: it reaches a minimum thickness at which the field along it is just sufficient to sweep every arriving electron through. Any tendency of the current to fall would reduce the ohmic drop along the channel, reduce the reverse bias at the drain end, and re-open the channel. The device settles at the current for which the pinch-off point sits exactly at the drain. Raising \(V_{DS}\) beyond that moves the pinch-off point a small distance back towards the source and drops the extra voltage across the short depleted length, leaving the current almost unchanged. The situation is the direct analogue of the reverse-biased collector junction of Chapter 16, which also collected every carrier that reached it regardless of how hard it was reverse biased.
Pinch-off happens when the reverse bias across the gate junction at the drain end reaches \(|V_P|\). That reverse bias is \(V_{DS} - V_{GS}\), so the condition is \(V_{DS} - V_{GS} = |V_P| = -V_P\), giving \(V_{DS(\text{sat})} = V_{GS} - V_P\). With \(V_P = -4\) V this is 4 V at \(V_{GS} = 0\), 3 V at \(V_{GS} = -1\) V, 2 V at \(-2\) V and 1 V at \(-3\) V. Every one of the four curves in Figure 21.2 turns over at its own value, and the locus of those turning points is itself a parabola.
The characteristic therefore has two regions, and every calculation in this chapter and the next three begins by deciding which one the device is in.
- The ohmic (triode) region, \(V_{DS} < V_{GS} - V_P\). The channel conducts along its whole length and the device is a voltage-controlled resistor. For small \(V_{DS}\) the drain-source resistance is \(r_{DS} = r_{DS(0)}/(1 - V_{GS}/V_P)\), where \(r_{DS(0)} = |V_P|/(2I_{DSS}) = 4/(2\times12\ \text{mA}) = 166.7\ \Omega\) for our device. Section 6 of Chapter 24 makes an attenuator out of exactly this.
- The saturation (pinch-off, or active) region, \(V_{DS} \ge V_{GS} - V_P\). The current is almost independent of \(V_{DS}\) and is controlled by \(V_{GS}\) alone. This is the amplifying region, and it is where every Q-point in this chapter is placed. The residual slope corresponds to a drain resistance \(r_d\) of tens of kilohms, the exact analogue of the Early-effect resistance \(r_o\) of Chapter 17.
- Breakdown, at \(V_{DS}\) large enough to avalanche the gate junction at the drain end. Since that junction already carries \(V_{DS} - V_{GS}\), making \(V_{GS}\) more negative reduces the usable drain voltage — the breakdown knees in Figure 21.2 march leftwards as one goes down the family. A data sheet quotes \(BV_{DGO}\), from which the usable \(V_{DS}\) at a given \(V_{GS}\) follows.
Note the terminology trap. The saturation region of a FET is the useful amplifying region, the one that corresponds to the active region of a BJT. The saturation region of a BJT, by contrast, is the bottomed-out region that corresponds to the FET's ohmic region. The two devices use the same word for opposite ends of the characteristic, and there is no help for it except to be careful.
3 Shockley's Equation, the Square Law and \(g_m\)
In the saturation region the drain current is a function of \(V_{GS}\) alone, and integrating the channel conductance over the tapered geometry gives a result that is very nearly a parabola. The parabolic approximation is universally used and is accurate to a few per cent over most of the range:
Shockley's equation. \(I_{DSS}\) is the drain current with the gate shorted to the source, and \(V_P\) is the pinch-off voltage. Some data sheets write \(V_{GS(\text{off})}\) instead of \(V_P\); for a JFET the two are numerically the same thing seen from opposite terminals, and both are negative for an n-channel device.
Two consequences of the square law are used constantly and are worth committing to memory. Putting \(V_{GS} = V_P/2\) gives \(I_D = I_{DSS}/4\), so half-way to cut-off in voltage is a quarter of the way in current. Putting \(I_D = I_{DSS}/2\) gives \(V_{GS} = V_P(1 - 1/\sqrt{2}) = 0.293V_P\), which for our device is \(-1.17\) V. Both are useful for sketching a transfer curve from the two data-sheet numbers alone: plot \((0, I_{DSS})\), \((V_P, 0)\), \((V_P/2, I_{DSS}/4)\) and \((0.3V_P, I_{DSS}/2)\), and join them.
Transconductance. The parameter that matters for amplification is not the current but the slope of the transfer curve, since that is what converts a signal voltage on the gate into a signal current in the drain. Differentiating Shockley's equation,
The leading factor is the transconductance at \(V_{GS} = 0\), written \(g_{m0}\) or \(y_{fs}\) on a data sheet:
The last form is often the most convenient, because it gives \(g_m\) directly from the Q-point current without needing \(V_{GS}\). It also shows that \(g_m \propto \sqrt{I_D}\), which is the single most important difference between a FET and a BJT: for the bipolar device \(g_m = I_C/V_T\) is proportional to current, not to its square root.
| \(V_{GS}\) (V) | \(I_D\) (mA) | \(g_m\) (mS) | \(V_{DS(\text{sat})}\) (V) |
|---|---|---|---|
| 0 | 12.000 | 6.000 | 4.0 |
| \(-0.5\) | 9.188 | 5.250 | 3.5 |
| \(-1.0\) | 6.750 | 4.500 | 3.0 |
| \(-1.5\) | 4.688 | 3.750 | 2.5 |
| \(-2.0\) | 3.000 | 3.000 | 2.0 |
| \(-2.5\) | 1.688 | 2.250 | 1.5 |
| \(-3.0\) | 0.750 | 1.500 | 1.0 |
| \(-3.5\) | 0.188 | 0.750 | 0.5 |
| \(-4.0\) | 0 | 0 | 0 |
Read the table as a designer would. To get a large \(g_m\) one must bias close to \(V_{GS} = 0\), which means close to \(I_{DSS}\), which means accepting the full manufacturing spread of \(I_{DSS}\) and a large quiescent dissipation. Biasing further down the curve buys predictability at the direct cost of gain. The best a designer can do with this device is 6 mS, and 6 mS is thirteen times worse than the 77 mS the bipolar transistor of Chapter 19 achieved at a third of the current. That is the price of the insulated — or here, reverse-biased — gate, and Chapter 24 quantifies what it costs in amplifier gain.
The p-channel device. Interchange every doping: an n-type gate diffused into a p-type channel. Holes now carry the channel current, so the drain is made negative with respect to the source and the gate must be made positive to reverse bias the junction. Shockley's equation is unchanged in form; only the signs of \(V_{GS}\), \(V_P\) and \(V_{DS}\) reverse, and \(V_P\) is now positive. A p-channel device with \(I_{DSS} = 8\) mA and \(V_P = +3\) V biased at \(V_{GS} = +1.2\) V passes \(8(1 - 1.2/3)^2 = 2.88\) mA. Because hole mobility is roughly a third of electron mobility, a p-channel JFET of the same geometry has about a third of the transconductance, so n-channel devices are used wherever there is a choice. The p-channel part earns its place in complementary circuits and in stages that must be referred to the positive rail, exactly as the PNP transistor did in Chapter 16.
4 Fixed Bias and Self Bias
Biasing a JFET means choosing \(V_{GS}\), because \(V_{GS}\) fixes \(I_D\) through Shockley's equation. That sounds easier than biasing a BJT, and in one respect it is: no base current flows, so no \(\beta\) enters the equations and no divider is loaded. In another respect it is much harder, because \(I_{DSS}\) and \(V_P\) are not merely temperature dependent but genuinely different from device to device. The family used in the three designs below is a realistic one:
| Device | \(I_{DSS}\) | \(V_P\) | \(g_{m0}\) |
|---|---|---|---|
| minimum | 5 mA | \(-2\) V | 5.0 mS |
| typical (used for all worked numbers) | 12 mA | \(-4\) V | 6.0 mS |
| maximum | 20 mA | \(-6\) V | 6.7 mS |
Every bias circuit below is judged by two questions. Where is the Q-point for the typical device? And how far does it move for the minimum and maximum devices?
Fixed bias is the direct approach: apply a fixed negative voltage between gate and source from a separate supply, through a large gate resistor \(R_G\). No gate current flows, so no voltage is dropped across \(R_G\) and \(V_{GS} = -V_{GG}\) exactly. \(R_G\) is there only to provide a d.c. path for the gate leakage and to set the a.c. input impedance; 1 MΩ is typical.
Take \(V_{DD} = 16\) V, \(R_D = 2.2\) kΩ, \(R_G = 1\) MΩ and \(V_{GG} = 1.5\) V, so \(V_{GS} = -1.5\) V.
Typical device. Shockley's equation gives
so \(V_{DS} = 16 - 4.688(2.2) = 5.688\) V. Check saturation: \(V_{DS(\text{sat})} = V_{GS} - V_P = -1.5 + 4 = 2.5\) V, and 5.688 V comfortably exceeds it. The transconductance is \(g_m = 6(0.625) = 3.750\) mS and the device dissipates \(5.688 \times 4.688 = 26.7\) mW.
Minimum device. \(I_D = 5(1 - 1.5/2)^2 = 5(0.25)^2 = 0.313\) mA. The drain sits at \(16 - 0.69 = 15.31\) V, almost at the rail; there is 0.7 V of downward output swing and the stage is useless.
Maximum device. \(I_D = 20(1 - 1.5/6)^2 = 20(0.75)^2 = 11.25\) mA, so \(V_{DS} = 16 - 24.75 = -8.75\) V, which is impossible. What actually happens is that the device leaves saturation and sits in the ohmic region with \(V_{DS}\) of a few tenths of a volt and \(I_D \approx 16/2.2\ \text{k}\Omega = 7.3\) mA. It has bottomed, and it will not amplify at all.
The ratio of the extreme currents is \(11.25/0.313 = 36\). One value of \(V_{GG}\) cannot serve a family whose transfer curves differ that much, and fixed bias survives only where every device is individually adjusted — which is to say, in a laboratory experiment and nowhere else.
Self bias removes the second supply and, much more importantly, makes \(V_{GS}\) depend on the current the device chooses to pass. Put a resistor \(R_S\) between source and ground, and return the gate to ground through \(R_G\). Since no gate current flows, the gate is at exactly 0 V; the source is at \(I_D R_S\); therefore
The bias line. It is a straight line through the origin of the transfer plot with slope \(-1/R_S\), and the Q-point is where it cuts the transfer curve.
This is degenerative in the exact sense of Chapter 18's emitter resistor, and the feedback loop is worth tracing in words. Suppose the device passes more current than intended — because it is a maximum-\(I_{DSS}\) sample, or because it has warmed up. More current raises \(I_DR_S\), which raises the source voltage, which makes \(V_{GS}\) more negative, which moves the device further towards cut-off and reduces the current. The correction happens automatically and instantly, and it costs nothing but the voltage dropped across \(R_S\). The same loop is what allows the JFET's negative temperature coefficient of \(I_{DSS}\) and the positive coefficient of \(|V_P|\) to be tolerated: whatever the device does, the resistor argues against it.
Same supply and drain resistor: \(V_{DD} = 16\) V, \(R_D = 2.2\) kΩ, \(R_G = 1\) MΩ, and now \(R_S = 470\ \Omega\).
The algebra. Substitute \(V_{GS} = -I_DR_S\) into Shockley's equation:
which rearranges to the quadratic \(165.675\,I_D^{2} - 3.820\,I_D + 0.012 = 0\) with \(I_D\) in amps. Its roots are 19.31 mA and 3.752 mA. The first is rejected: it would need \(V_{GS} = -9.08\) V, far beyond \(V_P\), where Shockley's equation does not apply. The physical root is
The check. Put \(V_{GS} = -1.763\) V back into Shockley's equation: \(12(1 - 1.763/4)^2 = 12(0.5591)^2 = 3.752\) mA. It closes. And \(V_{DS(\text{sat})} = -1.763 + 4 = 2.237\) V, so with 5.983 V across the device we are 3.75 V inside the saturation region — comfortable, and that margin is the available downward output swing.
The graphical solution. Draw the transfer curve from the two data-sheet numbers, then draw the bias line \(V_{GS} = -I_DR_S\) through the origin. One convenient second point is \(I_D = 6\) mA, \(V_{GS} = -6(0.470) = -2.82\) V. The two curves cross at \((-1.76\ \text{V},\ 3.75\ \text{mA})\), which is what the algebra gave. The graphical method is not merely a check: it is the only method available when the transfer curve is measured rather than modelled, and it makes the effect of device spread visible at a glance, since the same bias line simply crosses three different parabolas.
Small-signal parameter. \(g_m = 6(1 - 1.763/4) = 6(0.5591) = 3.355\) mS, used throughout Chapter 24.
Device spread. Solving the same quadratic with the minimum and maximum devices gives 1.743 mA (\(V_{GS} = -0.819\) V) and 5.857 mA (\(V_{GS} = -2.753\) V). The ratio is 3.36, against 36 for fixed bias — a tenfold improvement bought with one resistor and 1.76 V of headroom.
5 Voltage-Divider Bias and the Graphical Picture
Self bias has one structural limitation. Its bias line passes through the origin, so its slope is the only thing a designer can choose, and slope alone cannot make the line steep and place the Q-point at a useful current. A shallow line (large \(R_S\)) gives good rejection of device spread but a small \(I_D\) and therefore a small \(g_m\); a steep line (small \(R_S\)) gives a large \(I_D\) but tracks the parabola closely and rejects very little.
Voltage-divider bias breaks that coupling by lifting the gate to a fixed positive voltage \(V_G\), so the bias line no longer passes through the origin:
The gate draws no current, so the divider is completely unloaded — unlike the BJT divider of Chapter 18, where \(R_1\|R_2\) had to be kept below about \(0.1(1+\beta)R_E\). Here \(R_1\) and \(R_2\) may be megohms, which is what keeps the input impedance high.
Now \(V_G\) and \(R_S\) can be chosen independently: \(R_S\) sets the slope, hence the rejection, and \(V_G\) shifts the whole line right to restore the current. A large \(R_S\) with a compensating \(V_G\) gives a nearly horizontal bias line, which intersects all three parabolas at almost the same current. The limit is headroom: every volt spent raising the source robs the drain of output swing.
Design for a Q-point near \(I_D = 3.2\) mA on the typical device, from \(V_{DD} = 16\) V, keeping the gate resistance in the megohm range.
Choosing the divider. Take \(R_1 = 10\) MΩ and \(R_2 = 2.2\) MΩ. Then
Choosing \(R_S\). Try \(R_S = 1.5\) kΩ. Substituting \(V_{GS} = 2.885 - 1500I_D\) into Shockley's equation gives the quadratic \(1687.5\,I_D^{2} - 16.492\,I_D + 0.035554 = 0\), whose roots are 6.562 mA and 3.211 mA. The larger is rejected because it implies \(V_{GS} = -6.96\) V, beyond \(V_P\), so
The rest of the circuit. With \(R_D = 1.5\) kΩ: \(V_S = 3.211(1.5) = 4.816\) V, \(V_D = 16 - 3.211(1.5) = 11.184\) V, so \(V_{DS} = 6.368\) V. Saturation needs \(V_{DS} > V_{GS} - V_P = 2.069\) V, which is satisfied with 4.30 V to spare. The device dissipates 20.4 mW and \(g_m = 6(1 - 1.931/4) = 3.104\) mS.
Device spread. Solving the same equation for the other two members of the family:
| Device | \(I_D\) | \(V_{GS}\) | \(V_{DS}\) | \(V_{DS(\text{sat})}\) |
|---|---|---|---|---|
| minimum (5 mA, \(-2\) V) | 2.344 mA | \(-0.631\) V | 8.968 V | 1.369 V |
| typical (12 mA, \(-4\) V) | 3.211 mA | \(-1.931\) V | 6.368 V | 2.069 V |
| maximum (20 mA, \(-6\) V) | 4.110 mA | \(-3.280\) V | 3.670 V | 2.720 V |
The current spread is now 1.75 to 1, or \(\pm 27\) per cent about the mean, against 3.36 for self bias and 36 for fixed bias. Every member of the family remains in saturation, although the maximum device has only 0.95 V of margin, and that is the number a designer checks rather than the current. Raising \(R_S\) and \(V_G\) together would tighten the spread further at the cost of that margin; there is no free improvement.
Figure 21.4 makes the whole argument visible. The fixed-bias line is vertical, so it inherits every bit of the parabola's variation. The self-bias line is tilted, and where it crosses a taller parabola it does so at a more negative \(V_{GS}\), which pulls the current back down. The divider line is tilted much further and shifted right, so it crosses all three parabolas within a narrow band of current. Nothing else in JFET biasing is more important than that picture, and a student who can draw it can solve any bias problem in the subject, including ones for which no closed-form solution exists because the transfer curve is a measured one.
6 Comparing JFET and BJT Biasing
Chapter 18 solved a formally similar problem and reached a formally similar answer, and the differences between them are instructive.
| BJT (Chapter 18) | JFET (this chapter) | |
|---|---|---|
| Controlling quantity | base current; \(I_C = \beta I_B\) | gate voltage; \(I_D = I_{DSS}(1-V_{GS}/V_P)^2\) |
| What varies between samples | \(\beta\), typically 3:1 | \(I_{DSS}\) 4:1 and \(V_P\) 3:1, and they are not independent |
| What varies with temperature | \(V_{BE}\) at \(-2\) mV/°C; \(I_{CBO}\) doubling per 10 °C; \(\beta\) rising | \(I_{DSS}\) falling and \(|V_P|\) falling; the two partly cancel near \(I_D \approx 0.3I_{DSS}\) |
| Divider loading | \(R_1\|R_2 \le 0.1(1+\beta)R_E\); typically a few kΩ | none — the divider may be megohms |
| Bias equation | linear; solved directly | quadratic; solved by formula or graphically |
| Achieved spread here | voltage divider: \(I_C\) within a few per cent | voltage divider: \(I_D\) within \(\pm 27\) per cent |
| Transconductance at the Q-point | 77.3 mS at 2.01 mA | 3.10 mS at 3.21 mA |
| Cost of the stabilising resistor | \(R_E\) can be bypassed for a.c. and costs 2 V | \(R_S\) can be bypassed and costs 4.8 V |
The row that matters most is the second-to-last. A voltage-divider-biased BJT holds its collector current to a few per cent because the bias equation is \(I_C \approx (V_{th}-0.7)/R_E\) and neither \(V_{th}\), nor 0.7 V, nor \(R_E\) depends on the transistor at all. There is no equivalent for the JFET: \(V_{GS}\) at a given current is a device parameter that ranges over volts, not a near-constant 0.7 V, so the bias line must do the work of averaging over that range and cannot eliminate it. Twenty-seven per cent is close to the best a two-resistor scheme can do, and designs that need better use a current source in the source lead or an active feedback loop.
The compensating advantage is the row above it. The JFET divider is unloaded, so it can be made from megohm resistors, and the a.c. input impedance of the stage is \(R_1\|R_2 = 1.8\) MΩ instead of the 1.04 kΩ the bipolar stage of Chapter 19 managed. Three orders of magnitude of input impedance in exchange for a factor of twenty-five in \(g_m\) and a factor of ten in bias precision is a bargain in some applications and a disaster in others, which is why both devices are still made.
One further point deserves emphasis before Chapter 22 replaces the reverse-biased junction with an oxide. Everything in Sections 4 and 5 — the bias line, the graphical intersection, the degenerative source resistor, the trade between rejection and headroom — carries over unchanged to the depletion MOSFET, and carries over with only a change of sign and of transfer equation to the enhancement MOSFET of Chapter 23. What changes in the next chapter is how the channel is controlled, not how the operating point is placed.
7 Summary and Key Results
| Quantity | Expression | Value |
|---|---|---|
| Gate input resistance | \(V_{GS}/I_{GSS}\) | 20 GΩ at 25 °C; 3.45 MΩ at 150 °C |
| Pinch-off condition | \(V_{DS(\text{sat})} = V_{GS} - V_P\) | 4 V at \(V_{GS}=0\); 2 V at \(V_{GS}=-2\) V |
| Ohmic-region resistance | \(r_{DS} = r_{DS(0)}/(1-V_{GS}/V_P)\) | \(r_{DS(0)} = |V_P|/2I_{DSS} = 166.7\ \Omega\) |
| Shockley's equation | \(I_D = I_{DSS}(1-V_{GS}/V_P)^2\) | \(I_{DSS}/4\) at \(V_P/2\); \(I_{DSS}/2\) at \(0.293V_P = -1.17\) V |
| Transconductance | \(g_m = g_{m0}(1-V_{GS}/V_P) = 2\sqrt{I_{DSS}I_D}/|V_P|\) | \(g_{m0} = 6.00\) mS; \(g_m \propto \sqrt{I_D}\) |
| Fixed bias | \(V_{GS} = -V_{GG}\) | \(I_D = 4.688\) mA, \(V_{DS} = 5.688\) V; family spread 36:1 |
| Self bias | \(V_{GS} = -I_DR_S\) | \(R_S = 470\ \Omega\): \(I_D = 3.752\) mA, \(V_{GS} = -1.763\) V, \(g_m = 3.355\) mS; spread 3.36:1 |
| Voltage-divider bias | \(V_{GS} = V_G - I_DR_S\) | \(V_G = 2.885\) V, \(R_S = 1.5\) kΩ: \(I_D = 3.211\) mA, \(V_{GS} = -1.931\) V, \(g_m = 3.104\) mS; spread 1.75:1 |
| Q-point verification | \(V_{DS} > V_{GS}-V_P\) | divider design: 6.368 V against 2.069 V required |
| Divider loading | gate current \(\approx 0\) | \(R_1\|R_2 = 1.803\) MΩ permissible; the BJT equivalent was 5.19 kΩ |
| p-channel device | same equation, all signs reversed | \(I_{DSS}=8\) mA, \(V_P=+3\) V, \(V_{GS}=+1.2\) V gives 2.88 mA |
8 Common Mistakes
Substituting the bias line into Shockley's equation always produces two roots, and only one of them is physical. For the design of Worked Example 21.2 they are 19.31 mA and 3.752 mA. The larger root corresponds to \(V_{GS} = -9.08\) V, which is well beyond \(V_P = -4\) V, where the device is cut off and Shockley's equation is simply not valid — the equation is a parabola and continues happily past its own zero, but the transistor does not. The test is always the same: compute \(V_{GS}\) for each root and reject any that falls outside \(V_P \le V_{GS} \le 0\). Drawing the graphical solution once makes the point permanently, because the spurious root sits on the branch of the parabola that lies to the left of \(V_P\) and has no physical existence.
Shockley's equation describes the saturation region only. Applying it to a device that has been driven into the ohmic region gives an answer that is not merely inaccurate but qualitatively wrong — it predicts a current the circuit cannot supply. In Worked Example 21.1 the maximum device wanted 11.25 mA through a 2.2 kΩ resistor from a 16 V rail, which is arithmetically impossible; the device actually sits in the ohmic region at about 7.3 mA with \(V_{DS}\) of a few hundred millivolts, and it has no transconductance to speak of. Every JFET calculation should therefore end with the line \(V_{DS} \stackrel{?}{>} V_{GS} - V_P\), and the margin by which it is satisfied is the available output swing.
Chapter 18 insisted that \(R_1\|R_2\) be kept below about a tenth of \((1+\beta)R_E\), because base current flowing out of the divider shifts \(V_{th}\). Students trained on that rule often carry it across and design a JFET divider from 22 kΩ and 6.8 kΩ. Nothing goes wrong with the bias — the Q-point is exactly where the calculation says — but the a.c. input impedance of the stage has been thrown away, falling from 1.8 MΩ to 5.2 kΩ and taking with it the one property the JFET was chosen for. The divider current also becomes a real load on the supply. The correct rule for a FET is the opposite one: make \(R_1\) and \(R_2\) as large as leakage and noise permit, with the ceiling set by the gate leakage at the maximum operating temperature, not by the bias equations.
9 Chapter Review
1. A JFET has \(I_{DSS} = 10\) mA and \(V_P = -5\) V. It is self-biased with \(R_S = 1\) kΩ, \(R_D = 2\) kΩ, \(R_G = 1\) MΩ and \(V_{DD} = 20\) V. Find the Q-point, verify the region of operation, and compute \(g_m\).
Substitute \(V_{GS} = -1000I_D\) into Shockley's equation. Since \(1 - V_{GS}/V_P = 1 - (-1000I_D)/(-5) = 1 - 200I_D\), the equation becomes \(I_D = 0.010(1-200I_D)^2\) with \(I_D\) in amps, that is \(400I_D^2 - 5I_D + 0.010 = 0\). The roots are \(I_D = [5 \pm \sqrt{25-16}]/800 = (5\pm3)/800\), so 10.00 mA or 2.500 mA. The first implies \(V_{GS} = -10.0\) V, far beyond \(V_P = -5\) V, and is rejected. Taking \(I_D = 2.500\) mA gives \(V_{GS} = -2.500\) V and \(10(1-2.5/5)^2 = 10(0.5)^2 = 2.500\) mA, which closes exactly. The drain voltage is \(20 - 2.5(2) = 15.0\) V and the source is at 2.5 V, so \(V_{DS} = 12.5\) V. Saturation requires \(V_{DS} > V_{GS} - V_P = -2.5 + 5 = 2.5\) V, which is satisfied with 10 V of margin. Finally \(g_{m0} = 2(10)/5 = 4.0\) mS and \(g_m = 4.0(1 - 2.5/5) = 2.0\) mS. This design happens to land exactly on the half-cut-off point, where \(I_D = I_{DSS}/4\) and \(g_m = g_{m0}/2\).
2. Explain, without algebra, why self bias reduces the effect of device spread but a fixed gate voltage does not, and why voltage-divider bias does better than either.
Think of the transfer characteristic as belonging to the device and the bias arrangement as contributing a line on the same axes; the Q-point is where they cross. Fixed bias contributes a vertical line at \(V_{GS} = -V_{GG}\). A vertical line crosses a taller parabola at a proportionally larger current, so the operating current inherits the whole of the device variation — for the family in this chapter, a factor of 36. Self bias contributes a line through the origin sloping down to the left, so a device that tries to pass more current is met by a more negative \(V_{GS}\), which pushes it back towards cut-off. That is negative feedback in the ordinary sense: the output quantity, \(I_D\), acts back on the controlling quantity, \(V_{GS}\), in the direction that opposes the change. The steeper the transfer curve relative to the bias line, the more effective the correction, and the spread falls to 3.36 to 1. But a self-bias line must pass through the origin, so making it flatter (larger \(R_S\)) necessarily drags the Q-point down towards small currents and small \(g_m\). Voltage-divider bias removes that constraint by lifting the whole line to a positive intercept \(V_G\): the slope can then be made as flat as headroom allows while \(V_G\) restores the current to a useful value. In the limit of a very flat line the circuit approximates a current source in the source lead, and the operating current becomes almost independent of the device altogether.
3. Design a self-bias circuit for a JFET with \(I_{DSS} = 8\) mA and \(V_P = -4\) V to give \(I_D = 2\) mA, from a 15 V supply, with \(V_{DS} = 7\) V. Then state the transconductance and the largest undistorted output swing.
Work backwards from the wanted current. Shockley's equation inverted gives the required gate-source voltage: \(2 = 8(1 - V_{GS}/(-4))^2\), so \((1 + V_{GS}/4)^2 = 0.25\), \(1 + V_{GS}/4 = 0.5\) and \(V_{GS} = -2.0\) V. The source resistor follows immediately from the bias line: \(R_S = -V_{GS}/I_D = 2.0/2\ \text{mA} = 1.0\) kΩ. For the drain resistor, apply Kirchhoff round the output loop: \(V_{DD} = I_DR_D + V_{DS} + I_DR_S\), so \(15 = 2\ \text{mA}(R_D) + 7 + 2.0\), giving \(I_DR_D = 6.0\) V and \(R_D = 3.0\) kΩ. Take \(R_G = 1\) MΩ. Checking the region: \(V_{DS(\text{sat})} = V_{GS} - V_P = -2 + 4 = 2.0\) V, and \(V_{DS} = 7\) V, so the device is 5 V inside saturation. The transconductance is \(g_{m0} = 2(8)/4 = 4.0\) mS and \(g_m = 4.0(1 - 2/4) = 2.0\) mS. For the output swing, the drain can fall until \(V_{DS}\) reaches \(V_{DS(\text{sat})} = 2\) V, a fall of 5 V, and can rise until the device cuts off, at which point no current flows in \(R_D\) and the drain reaches \(V_{DD} = 15\) V, a rise of 6 V from its quiescent 9 V. The symmetrical limit is therefore 5 V peak, or 10 V peak-to-peak, and the stage is limited by the saturation boundary rather than by the supply rail. Moving the Q-point up by half a volt, to \(V_{DS} = 7.5\) V, would put the drain at 9.5 V and balance the two limits at 5.5 V each.
4. A data sheet gives \(I_{DSS}\) between 4 mA and 12 mA and \(V_{GS(\text{off})}\) between \(-1.5\) V and \(-4.5\) V. A voltage-divider bias circuit uses \(V_G = 3\) V and \(R_S = 2\) kΩ. Find the two extreme drain currents and comment on whether \(R_S\) should be raised.
For each device solve \(I_D = I_{DSS}(1 - (V_G - I_DR_S)/V_P)^2\) with \(V_G = 3\) V and \(R_S = 2\) kΩ, and reject any root whose \(V_{GS}\) falls outside \(V_P \le V_{GS} \le 0\). For the minimum device, \(I_{DSS} = 4\) mA and \(V_P = -1.5\) V, the quadratic is \(7111.1\,I_D^2 - 33.0\,I_D + 0.036 = 0\), with roots 2.887 mA and 1.753 mA. The first implies \(V_{GS} = -2.774\) V, beyond \(V_P = -1.5\) V, so the operating point is \(I_D = 1.753\) mA at \(V_{GS} = -0.507\) V. For the maximum device, \(I_{DSS} = 12\) mA and \(V_P = -4.5\) V, the same substitution gives roots 5.236 mA and 2.686 mA; the first needs \(V_{GS} = -7.47\) V and is rejected, so \(I_D = 2.686\) mA at \(V_{GS} = -2.371\) V. The extreme currents are therefore 1.753 mA and 2.686 mA, a ratio of 1.53 or \(\pm 21\) per cent about the mean — a good result for a spread that was 3:1 in \(I_{DSS}\) and 3:1 in \(V_P\). The source voltages are 3.51 V and 5.37 V, so the two devices sit almost 2 V apart on the source, and it is the drain that must be given room for that. Raising \(R_S\) would flatten the bias line further and tighten the spread, but \(V_G\) would have to rise with it to keep the current up, and every volt added to \(V_G\) and \(V_S\) is a volt removed from the drain's output swing. With 2 kΩ already dropping about 4 V of a typical 15 V supply, there is little room left, and the answer is that \(R_S\) is close to its practical maximum.
5. Compare a JFET stage biased at \(I_D = 3.2\) mA with the BJT stage of Chapter 19 biased at \(I_C = 2.0\) mA, in terms of transconductance, input impedance and the sensitivity of the operating point. What would each be chosen for?
The transconductances are \(g_m = 2\sqrt{I_{DSS}I_D}/|V_P| = 2\sqrt{12\times3.21}/4 = 3.10\) mS for the JFET and \(g_m = I_C/V_T = 2.009/26 = 77.3\) mS for the BJT: the bipolar device has twenty-five times more transconductance at two-thirds of the current, because its exponential characteristic is far steeper than a square law. Expressed as \(g_m/I_D\), the figure of merit for how efficiently a device converts bias current into gain, the BJT gives 38.5 per volt (a constant, equal to \(1/V_T\)) and the JFET gives 0.97 per volt. The input impedances go the other way: the JFET stage's is the divider resistance, 1.8 MΩ, limited only by leakage, while the BJT stage's is \(R_1\|R_2\|(1+\beta)r_e = 1.04\) kΩ, limited by the transistor itself and impossible to raise much because \((1+\beta)r_e\) is the smaller term. On operating-point sensitivity the BJT wins: its divider bias holds \(I_C\) to a few per cent because the bias equation contains no transistor parameter at all, whereas the JFET's best two-resistor scheme leaves \(\pm 27\) per cent because \(V_{GS}\) at a given current is itself a device parameter spanning volts. So the BJT is chosen wherever gain per milliamp, matched pairs, or a precisely known operating current matters — general-purpose amplification, current mirrors, differential pairs, output stages. The JFET is chosen wherever the source must not be loaded or the device must not add noise at high source impedance: electrometers, charge amplifiers, oscilloscope and instrumentation front ends, and the input stage of a low-noise operational amplifier, where a JFET pair is placed in front of a bipolar circuit that supplies the gain the JFET cannot.