By the end of this chapter you should be able to:
- Trace the operation of the standard TTL NAND gate with both inputs HIGH and with one input LOW, giving the voltage at every internal node.
- Explain the function of each element of the totem-pole output stage, including the series diode, and account for the supply-current spike at each transition.
- Calculate fan-out in both states from \(I_{OL}\), \(I_{OH}\), \(I_{IL}\) and \(I_{IH}\), for a uniform load and for a mixed one.
- Explain how a Schottky clamp removes storage time, and place the 74, 74L, 74S, 74LS, 74ALS and 74F variants on a speed–power plot.
- Size the pull-up resistor for a wired-AND connection of open-collector outputs, giving both the upper and the lower bound.
- State the rule for tri-state bus sharing and the correct way to terminate an unused TTL input.
Transistor–transistor logic was introduced by Texas Instruments in 1964 and it defined what a logic family is. Before TTL, a designer bought gates; after TTL, a designer bought a catalogue of parts guaranteed to work with one another — the 74 series, which grew to several hundred functions and is still the numbering scheme used by the CMOS parts that replaced it. Understanding TTL is therefore not archaeology. The pin-outs, the function numbers, the input and output conventions and most of the vocabulary of Chapter 12 came from this circuit.
It also rewards study because everything in it is visible. There are four transistors, four resistors and a diode, each of which is there for a reason you can trace, and the two features that give the family its character — the multi-emitter input and the totem-pole output — each solve a specific problem and each create a new one. This chapter works through the circuit in both logic states, computes the fan-out from data-sheet currents, sizes a real pull-up resistor, and explains the three output configurations a 74-series part can have.
1 The Multi-Emitter Input and How the NAND Works
Figure 13.1 is the complete standard 7400 NAND gate. Read it in three parts: the input transistor Q1 with R1, the phase splitter Q2 with R2 and R3, and the totem-pole output stage of Q3, the diode D and Q4.
Q1 is a single transistor with one base, one collector and two emitters, both diffused into the same base region. It is not two transistors, and the saving is real: an eight-input 7430 needs an eight-emitter Q1 and no more silicon than the two-emitter version. Functionally the emitters behave as two diodes sharing a common anode, which is why the earlier DTL family, which really did use a diode AND array, converts into TTL by replacing the diodes with a single transistor.
Both inputs HIGH. Neither emitter junction can be forward biased, because both inputs sit near the supply. Current from R1 has nowhere to go except through the base–collector junction of Q1, which is forward biased and passes it on into the base of Q2. So Q1 operates in reverse: what is drawn as its collector acts as an emitter. Q2 turns on, and the current through its emitter resistor R3 develops enough voltage to turn Q4 on and drive it into saturation. The output is pulled to \(V_{CE(\text{sat})} \approx 0.2\ \text{V}\): a logic LOW. The gate is a NAND, so LOW out for all inputs HIGH is exactly right.
Meanwhile Q3 must be off, or it would fight Q4. With Q2 saturated, the voltage at Q2’s collector is \(V_{CE(\text{sat})}\) above Q4’s base, that is \(0.2 + 0.7 = 0.9\ \text{V}\). For Q3 to conduct it would need its base at least a \(V_{BE}\) above its emitter, and the diode D adds a further 0.7 V before the output is reached:
Only 0.9 V is available, so Q3 is firmly off. That single inequality is why the diode is in the circuit. Remove D and the requirement falls to 0.9 V, exactly the voltage present — Q3 would sit on the edge of conduction throughout every LOW output, wasting current and raising \(V_{OL}\).
One input LOW. Say A is pulled to 0.2 V by the LOW output of a preceding gate. That emitter junction is now forward biased, so the current in R1 flows out of the input pin into the driving gate rather than into Q2’s base:
The data sheet specifies \(I_{IL} \le 1.6\ \text{mA}\), allowing for supply and resistor tolerance. Note the sign of what this means physically: a TTL input in the LOW state is a current source pushing about a milliamp back into whatever drives it, and the driver must swallow it. This is the origin of the whole current-sinking discussion below.
With Q1 saturated, its collector — and therefore Q2’s base — sits at \(0.2 + 0.2 = 0.4\ \text{V}\), well below the 0.7 V Q2 needs, so Q2 is off. No current flows in R3, Q4’s base is held at ground and Q4 is off. Q2’s collector rises towards the supply, Q3 conducts as an emitter follower, and the output is pulled HIGH through R4, Q3 and D:
Guaranteed \(V_{OH(\min)}\) is only 2.4 V, because the data sheet must allow for the minimum supply and worst-case junction drops. The typical 3.5 V is what a meter shows, and it is the reason a TTL HIGH never looks like 5 V on an oscilloscope.
2 The Totem-Pole Output and the Switching Spike
Why not simply replace Q3, D and R4 with a resistor from the output to \(V_{CC}\)? Because a passive pull-up would have to be large enough not to overload Q4 in the LOW state and small enough to charge the load capacitance quickly in the HIGH state, and for a 5 V TTL output those two demands are irreconcilable. A 4 kΩ pull-up driving 50 pF gives a 10–90 % rise time of \(2.2 R C = 440\ \text{ns}\), which would throw away all of the family’s speed.
The totem pole solves this by making the pull-up active. Q3 is an emitter follower with an output resistance of a few tens of ohms, so it can deliver tens of milliamps into the load capacitance for the few nanoseconds the edge lasts, then settle back to sourcing only \(I_{OH}\). The 130 Ω resistor R4 is not there to slow the edge; it is there to limit the current when both output transistors are momentarily on, which is precisely what happens at every transition.
Consider the HIGH-to-LOW transition. Q4 turns on quickly, because Q2 is driving its base hard. Q3 turns off slowly, because Q2 must first remove the stored charge from Q3’s base region. For an overlap of roughly 10 ns both devices conduct, and the current is limited only by R4 and the two saturation drops in the path:
Measured spikes reach about 30 mA, roughly fifteen times the gate’s steady supply current. Without R4 the same calculation would give over an ampere, and Q3 would not survive many transitions.
Take a 30 mA spike lasting 10 ns, with a rise of 30 mA in 2 ns, on a board where the track and lead inductance between the package and the supply is about 20 nH.
Charge demanded per transition:
Voltage dip if that charge comes from a local 0.1 µF capacitor:
Voltage spike if it has to come down the supply track instead:
Compare the 300 mV with the 0.30 V LOW-state noise margin of 74LS from Chapter 12. One undecoupled package switching can consume the entire noise margin of every gate near it. That is the whole argument for a 0.1 µF ceramic capacitor across each package, mounted with the shortest possible leads — it is a local reservoir that supplies the spike without involving the supply track at all.
The spike also shows up as power. Averaged over time it is an extra supply current of \(Q f\); at 10 MHz that is \(0.3\ \text{nC} \times 10\ \text{MHz} = 3\ \text{mA}\), or 15 mW per gate on top of the static dissipation. TTL power is not quite independent of frequency after all, and the departure is entirely due to this mechanism.
3 Current Sourcing, Sinking and Fan-Out
The asymmetry of the input circuit gives TTL its characteristic loading behaviour. When a driving output is LOW, every load input pushes about a milliamp into it, and Q4 must sink the sum without its collector rising above \(V_{OL(\max)}\). When the driving output is HIGH, each load input draws only its reverse leakage, tens of microamps, out of Q3. The LOW state is therefore the demanding one by a factor of forty, and it is the state that sets fan-out.
| Parameter | 7400 (standard) | 74LS00 | 74S00 | 74ALS00 |
|---|---|---|---|---|
| \(I_{OL(\max)}\) — sink capability | 16 mA | 8 mA | 20 mA | 8 mA |
| \(I_{OH(\max)}\) — source capability | 400 µA | 400 µA | 1 mA | 400 µA |
| \(I_{IL(\max)}\) — per input, LOW | 1.6 mA | 0.4 mA | 2.0 mA | 0.1 mA |
| \(I_{IH(\max)}\) — per input, HIGH | 40 µA | 20 µA | 50 µA | 20 µA |
| Fan-out within the family | 10 | 20 | 10 | 80 |
(a) Standard 7400 driving standard 7400 inputs.
Fan-out 10 in both states — the family was designed to come out even.
(b) A standard 7400 driving 74LS inputs.
Twenty LS loads, and here it is the HIGH state that binds, because LS reduced the input LOW current by four times but the input HIGH leakage by only two.
(c) A 74LS00 driving standard 7400 inputs.
Only five. An LS output has half the sink capability of a standard output but is being asked to absorb four times the current per input. Substituting an LS part into an old design to save power can silently halve its fan-out margin, and the symptom will be a \(V_{OL}\) that has crept up to 0.7 V.
A standard input is 1 UL; an LS input is 0.25 UL; a standard output drives 10 UL and an LS output 5 UL. Working in unit loads turns every mixed-family fan-out question into one addition and one comparison, which is why the notation survives on data sheets.
4 The Schottky Clamp and the 74 Sub-Families
The speed of standard TTL is limited by one effect: storage time. A bipolar transistor driven into saturation accumulates excess minority carriers in its base, and when the drive is removed those carriers must recombine or be swept out before the collector current can begin to fall. The delay this adds, \(t_s\), can be 10–20 ns, comparable with everything else in the gate put together.
The cure is to stop the transistor saturating. A Schottky diode — a metal–semiconductor junction with a forward drop of about 0.4 V and, decisively, no minority-carrier storage of its own — is connected from base to collector. As the collector falls towards the base, the Schottky diode conducts and diverts the surplus base drive straight to the collector, clamping the base–collector forward bias at 0.4 V and holding
Slightly above the 0.2 V of a saturated device, but the transistor is now in the active region rather than in saturation, so \(t_s\) is essentially zero. The cost is that \(V_{OL}\) rises, which is why 74LS specifies 0.5 V where standard TTL specifies 0.4 V — and why 74LS has the poorer LOW noise margin of the two.
The clamp is a speed technique; the resistor values are a power technique. Combining them in different proportions produced the sub-families that fill a 74-series data book.
| Series | What changed | \(t_{pd}\) | Power/gate | SPP |
|---|---|---|---|---|
| 74 | Original saturated TTL | 9 ns | 10 mW | 90 pJ |
| 74L | All resistors raised about tenfold | 33 ns | 1 mW | 33 pJ |
| 74S | Schottky clamps, resistors lowered | 3 ns | 19 mW | 57 pJ |
| 74LS | Schottky clamps with 74L-style resistors | 9.5 ns | 2 mW | 19 pJ |
| 74ALS | Oxide isolation, smaller geometry | 4 ns | 1.2 mW | 4.8 pJ |
| 74F | Same process tuned for speed | 3.4 ns | 4 mW | 13.6 pJ |
Read the table down the SPP column and the story is clear. 74L is not an improvement on 74 — it trades three times the delay for a tenth of the power, moving along the same curve, and its product of 33 pJ against 90 pJ merely reflects that slower operation is more efficient. 74S is an improvement: 57 pJ against 90 pJ, achieved by a circuit change rather than a resistor change. 74LS combines both ideas and reaches 19 pJ, which is why it, and not 74S, became the default part. 74ALS at 4.8 pJ is a process improvement of the same kind on a later fabrication line.
All the sub-families share the same logic levels and pin-outs, so they intermix freely — subject to the fan-out arithmetic of Worked Example 13.2, which is exactly where mixed designs go wrong.
5 Open-Collector Outputs, Wired-AND and Pull-Up Sizing
Two totem-pole outputs must never be connected together. If one drives HIGH and the other LOW, the HIGH gate’s Q3 and the LOW gate’s Q4 form a path from \(V_{CC}\) to ground limited only by 130 Ω, which passes tens of milliamps, produces an indeterminate voltage somewhere in the forbidden band, and eventually destroys one of the two parts.
The open-collector output removes the problem by removing the pull-up. Q3, D and R4 are simply omitted and Q4’s collector is brought straight to the pin. Such an output can pull the pin LOW but cannot drive it HIGH at all; an external resistor to \(V_{CC}\) must do that. Now any number of outputs may be tied together, because none of them can source current.
The resulting node is LOW if any connected output is LOW, and HIGH only if all of them are HIGH. That is an AND of the outputs, obtained with a single resistor and no gate at all, and it is called a wired-AND. It is a genuinely useful function: an interrupt line onto which any of twenty peripherals may assert a request, or a “system ready” line that is HIGH only when every subsystem agrees, needs no logic whatever.
Four 7401 open-collector NAND outputs are wired together and drive five 74LS inputs from a 5 V supply. Data-sheet values: each open-collector output can sink \(I_{OL} = 16\ \text{mA}\) at \(V_{OL} = 0.4\ \text{V}\) and leaks \(I_{OH} = 250\ \mu\text{A}\) when off; each 74LS input takes \(I_{IL} = 0.4\ \text{mA}\) and \(I_{IH} = 20\ \mu\text{A}\). Take \(V_{OH}\) to be at least 2.7 V. Find the permitted range of \(R_p\).
Upper bound — the HIGH state. With every output off, \(R_p\) has to supply the leakage of all four outputs plus the input current of all five loads, and the drop it develops must not take the node below 2.7 V:
Lower bound — the LOW state. One output must hold the node at 0.4 V while sinking both the resistor current and the current pushed back by the five inputs, without exceeding its 16 mA rating:
Choice. Any value from 330 Ω to 2.0 kΩ works; take the standard 1 kΩ. Checking it:
- HIGH level: \(V_{OH} = 5 - (1\ \text{k}\Omega)(1.10\ \text{mA}) = 3.90\ \text{V}\), comfortably above the 2.0 V that a 74LS input demands.
- LOW state: the active output sinks \(4.6/1000 + 2.0\ \text{mA} = 6.6\ \text{mA}\) of its 16 mA budget.
- Speed: with about 50 pF on the node, the 10–90 % rise time is \(2.2R_pC = 110\ \text{ns}\). This is the real penalty — the LOW edge is driven by a transistor and takes a few nanoseconds, the HIGH edge is a passive RC and takes a hundred. Wired-AND nodes are slow, and that is intrinsic.
- Power: while the node is LOW the resistor dissipates \((4.6)^2/1000 = 21\ \text{mW}\), more than ten LS gates.
Choosing 330 Ω would cut the rise time to 36 ns but raise the sink current to 15.9 mA, leaving no margin at all. Choosing 2 kΩ would halve the power and double the rise time. The choice is a straight speed-against-power trade, made explicit by the two bounds.
Open-collector parts have a second use that has nothing to do with wired-AND. Because the output transistor’s collector is isolated, the pull-up may go to a different and higher supply: a 7406 inverting buffer is rated to 30 V and 40 mA, so it drives relays, lamps and opto-isolators directly, and it shifts a 5 V logic level up to a 15 V CMOS rail — a technique Chapter 15 uses.
6 Tri-State Outputs, Bus Sharing and Unused Inputs
Wired-AND restores shared connections but sacrifices the active pull-up and with it the speed. For a data bus, where many devices must take turns driving the same wires at full speed, a different answer is needed: keep the totem pole, but add the ability to switch both transistors off on command. An output in that condition is neither HIGH nor LOW but disconnected — a high-impedance or Hi-Z state — and an output with three possible conditions is called tri-state.
The implementation is economical. An extra emitter is added to Q1 for the enable input, and a diode is run from that emitter to Q3’s base. When the enable is asserted LOW, Q1 saturates and turns Q2 and hence Q4 off, exactly as an ordinary LOW input would; at the same time the added diode clamps Q3’s base down to about 0.4 V, which is below the 1.6 V it needs, so Q3 is off as well. Both transistors are off together and the pin presents only a leakage of some tens of microamps.
The rule for using them is absolute: exactly one driver on a bus line may be enabled at any instant. Enabling two in opposite states recreates the totem-pole conflict described above, with the same tens of milliamps and the same risk to the parts, and this failure — bus contention — is the classic fault in a first bus design. In practice the enables are generated by a decoder (Chapter 18) so that the hardware makes multiple assertion impossible, rather than by separate signals that software has to keep disjoint.
Disabled outputs still leak, so a bus is loaded even by drivers that are silent. Eight disabled 74LS244 outputs at 20 µA each add 160 µA to whatever the enabled driver must supply, and each contributes several picofarads. A bus with sixteen devices on it is a capacitive load of well over 100 pF, which is why bus drivers are specified with large \(I_{OL}\) — 24 mA for a 74LS244 against 8 mA for a 74LS00.
An unused TTL input floats to a level that behaves as a HIGH, because with no external connection the emitter junction is reverse biased and no current flows out of the pin. It is tempting to leave it. Do not: the pin is a high-impedance node with a few picofarads of capacitance sitting next to switching signals, and it will pick up enough coupled noise to cross the 0.8 V threshold. The correct treatments are:
- Unused AND/NAND inputs: tie to \(V_{CC}\) through a 1 kΩ resistor. The resistor matters, because a TTL input is only rated to 5.5 V and a direct connection exposes the emitter junction to any transient on the supply rail. One resistor may serve several inputs: with 25 inputs at 40 µA each the drop is \(25 \times 40\ \mu\text{A} \times 1\ \text{k}\Omega = 1.0\ \text{V}\), still leaving 4.0 V at the pins.
- Unused OR/NOR inputs: tie directly to ground. There is no rating problem in this direction, and the input then sinks nothing.
- Tie to a used input on the same gate: logically correct and needs no components, but it doubles the load presented to the driving gate, so it costs a unit of fan-out.
- Unused whole gates: tie their inputs so the output is HIGH. A LOW output dissipates more, and on a 74LS package that is 2 mW thrown away for nothing.
Chapter 14 shows that CMOS makes the same requirement far more urgent. A floating TTL input is a noise problem; a floating CMOS input can put the gate in its linear region and burn it.
7 Summary and Key Results
| Element or feature | What it does | Key number |
|---|---|---|
| Multi-emitter Q1 | Performs the AND function and speeds turn-off by pulling stored charge out of Q2 | \(I_{IL} = (5-0.7-0.2)/4\text{k} = 1.02\ \text{mA}\) |
| Phase splitter Q2 | Produces the two antiphase drives the totem pole needs | Collector 0.9 V when saturated |
| Totem-pole Q3, D, Q4 | Active pull-up for a fast HIGH edge; diode keeps Q3 off during a LOW output | Q3 needs 1.6 V at its base; only 0.9 V available |
| R4 = 130 Ω | Limits the through-current while both output devices conduct | \(I_{\text{spike}} = (5-1.6)/130 = 26\ \text{mA}\) |
| Schottky clamp | Holds \(V_{BC}\) at 0.4 V so the transistor never saturates | \(V_{CE} = 0.7-0.4 = 0.3\ \text{V}\); \(t_s \approx 0\) |
| Open collector | No pull-up, so outputs may be tied for a wired-AND | \(329\ \Omega \le R_p \le 2.09\ \text{k}\Omega\); use 1 kΩ |
| Tri-state | Both output devices off together, giving a Hi-Z third state | One driver enabled at a time; 20 µA leakage each |
8 Common Mistakes
It looks harmless on a diagram and it is destructive on a board. A HIGH output’s Q3 and a LOW output’s Q4 form a path limited only by the 130 Ω resistor, drawing about 26 mA continuously and settling at an indeterminate voltage inside the forbidden band. Only open-collector outputs may be tied together, and they need a pull-up resistor to have a HIGH state at all.
Both bounds are real and they come from different states. Taking only the HIGH-state calculation gives a maximum and tempts you to use the largest available resistor, which makes the rise time enormous; taking only the LOW-state calculation gives a minimum and tempts you into a value that leaves the output sinking its full rated current with no margin. Compute both, then choose a standard value with room on each side — 1 kΩ inside a 330 Ω to 2.09 kΩ window.
The logic levels match and the pin-outs match, so the substitution seems free. It is not: an LS output sinks 8 mA where a standard output sinks 16 mA, so driving standard TTL inputs at 1.6 mA each its fan-out falls from 10 to 5. If the node already had six or seven loads on it, \(V_{OL}\) will rise above 0.8 V and the circuit will fail intermittently, usually when warm.
9 Chapter Review
1. With both inputs of a 7400 HIGH, give the voltage at Q2’s collector and show that Q3 cannot conduct.
With both inputs HIGH, Q2 and Q4 are both saturated. Q4’s base sits at \(V_{BE} = 0.7\ \text{V}\) above ground and Q2’s collector is one \(V_{CE(\text{sat})}\) above that, so \(V_{C2} = 0.7 + 0.2 = 0.9\ \text{V}\). For Q3 to conduct, its base must reach \(V_{OL} + V_D + V_{BE3} = 0.2 + 0.7 + 0.7 = 1.6\ \text{V}\). Only 0.9 V is available, so Q3 is off by a margin of 0.7 V — which is exactly the margin the series diode provides.
2. A 74LS00 output drives four standard 7400 inputs and \(n\) 74LS inputs. Find the largest \(n\), and state which state limits it.
LOW state: the four standard inputs take \(4 \times 1.6 = 6.4\ \text{mA}\) of the 8 mA budget, leaving 1.6 mA, so \(n \le 1.6/0.4 = 4\). HIGH state: the four standard inputs take \(4 \times 40 = 160\ \mu\text{A}\) of the 400 µA budget, leaving 240 µA, so \(n \le 240/20 = 12\). The LOW state limits, and \(n = 4\).
3. Why does a Schottky-clamped transistor switch off faster than a saturated one, and what does the clamp cost?
A saturated transistor stores excess minority carriers in its base; those carriers must be removed before the collector current can fall, adding a storage time of 10–20 ns. The Schottky diode from base to collector conducts at about 0.4 V and diverts surplus base drive to the collector, holding the base–collector forward bias below the level at which significant charge is stored, so the device stays in the active region. A Schottky junction is majority-carrier and stores nothing itself. The cost is that \(V_{CE}\) is held at \(0.7 - 0.4 = 0.3\ \text{V}\) rather than 0.2 V, so \(V_{OL(\max)}\) rises from 0.4 V to 0.5 V and the LOW noise margin falls from 0.4 V to 0.3 V.
4. Six open-collector outputs are wired together and drive eight 74LS inputs from 5 V. Each output leaks 250 µA and sinks 16 mA at 0.4 V. Find the range of pull-up resistor for \(V_{OH} \ge 2.7\ \text{V}\).
HIGH state: the resistor must supply \(6 \times 250\ \mu\text{A} + 8 \times 20\ \mu\text{A} = 1.5 + 0.16 = 1.66\ \text{mA}\), so \(R_{p(\max)} = (5-2.7)/1.66\ \text{mA} = 1.39\ \text{k}\Omega\). LOW state: one output must sink the resistor current plus \(8 \times 0.4 = 3.2\ \text{mA}\) from the inputs, so \(R_{p(\min)} = (5-0.4)/(16-3.2)\ \text{mA} = 4.6/12.8\ \text{mA} = 359\ \Omega\). Any value from about 360 Ω to 1.39 kΩ will do; 1 kΩ is the obvious standard choice, and note how much narrower the window has become now that there are more outputs leaking and more inputs to feed.
5. Explain what bus contention is, why it is more serious than a mere logic error, and how a design normally prevents it.
Bus contention occurs when two tri-state drivers on the same line are enabled at once in opposite states. The HIGH driver’s emitter follower and the LOW driver’s saturated pull-down form a path from \(V_{CC}\) to ground limited only by the 130 Ω series resistor, so tens of milliamps flow. The bus voltage settles somewhere in the forbidden band, so every receiver reads an undefined level; worse, the current far exceeds the output ratings and repeated contention degrades or destroys the drivers, so the fault is permanent rather than transient. The standard prevention is to generate all the enables from one decoder, which by construction asserts only one output at a time, instead of from independent signals that could overlap.