By the end of this chapter you should be able to:
- Explain, in terms of the gate–source voltages of the two devices, why a CMOS inverter draws no static supply current in either logic state.
- Identify the five regions of the CMOS inverter transfer characteristic and calculate the switching threshold from the device transconductance ratio.
- Construct CMOS NAND and NOR gates at transistor level and explain the sizing penalty that makes NOR the worse structure.
- Explain why a transmission gate needs both an n-channel and a p-channel device, and state the consequence of using only one.
- Derive \(P = CV^{2}f\) from the charge delivered per switching cycle and apply it to a stated gate count, load and clock frequency.
- Describe the latch-up mechanism, the purpose of the input protection network, and the correct treatment of an unused CMOS input.
Complementary MOS logic was patented by Frank Wanlass in 1963, the year before TTL appeared, and for twenty years it was the slow, fragile alternative that engineers used only when a battery had to last. Then two things happened. Feature sizes shrank until CMOS was as fast as bipolar logic, and circuits grew large enough that the milliwatt per gate of TTL became a thermal impossibility — a million-gate chip in 74LS would dissipate two kilowatts. Every processor, memory and programmable device you will meet after Chapter 27 is CMOS, and the reason is contained in one property of the circuit in Figure 14.1.
This chapter builds the family from that circuit. It shows why the static current is essentially zero and what “essentially” is hiding, why the dissipation nevertheless rises in direct proportion to clock frequency, why a CMOS NOR is a worse gate than a CMOS NAND, and why the two rules a lab demonstrator will shout at you — never leave an input floating, never apply a signal before the supply — follow from the physics rather than from superstition.
1 The Complementary Pair and Zero Static Current
The whole family rests on pairing two enhancement-mode MOSFETs whose thresholds have opposite signs. An n-channel device conducts when its gate is at least \(V_{Tn}\) — typically 0.7 to 1.5 V in a 5 V process — above its source; a p-channel device conducts when its gate is at least \(|V_{Tp}|\) below its source. In the inverter of Figure 14.1 the p-channel source is tied to \(V_{DD}\) and the n-channel source to ground, and the two gates are joined.
Work through the two input states. With \(V_{in} = 0\), the n-channel device has \(V_{GS} = 0\) and is off, while the p-channel device has \(V_{GS} = 0 - 5 = -5\ \text{V}\) and is fully on; the output is pulled to \(V_{DD}\). With \(V_{in} = V_{DD}\) the roles exchange exactly. In each case one device is off, and a series pair with one member off carries no current. There is no resistor anywhere in the circuit, and therefore no path from the supply to ground in either stable state.
That is the property TTL cannot have. A TTL gate must hold a transistor in saturation to produce a LOW, and holding it there costs base and collector current for as long as the LOW lasts. A CMOS gate holds its state with a charge on a capacitor — the gate capacitance of whatever it drives — and charge, once placed, costs nothing to keep.
The 74HC00 data sheet specifies \(I_{CC} \le 20\ \mu\text{A}\) for the whole package at 25 °C, which is 25 µW per gate at 5 V, against 2 mW for a 74LS gate — a factor of eighty. But leakage roughly doubles for every 10 °C rise, so the same part at 85 °C leaks about sixty times more. In a small circuit this never matters; in a battery-backed memory holding data for five years it is the only thing that matters.
Two further consequences follow immediately, and both distinguish CMOS from TTL in the laboratory. First, the output swings rail to rail: with no resistive drop and no junction in the path, \(V_{OH}\) is \(V_{DD}\) less the ohmic drop in the conducting channel, which for a lightly loaded 74HC output is a few tens of millivolts. The data sheet guarantees 4.4 V at 4 mA and 4.9 V at 20 µA. Second, because the gate terminal is the plate of a capacitor over an oxide layer, the DC input current is a leakage of about 1 µA, so the DC fan-out is in the thousands and Chapter 12’s capacitive limit is the one that binds.
2 The Inverter Transfer Characteristic and Its Regions
Sweeping \(V_{in}\) from 0 to \(V_{DD}\) and plotting \(V_{out}\) gives the curve analysed in Chapter 12. For CMOS it divides into five regions rather than three, because each device passes through cut-off, saturation and the triode region in turn:
- Region 1, \(V_{in} < V_{Tn}\): the n-device is cut off, the p-device is in triode. \(V_{out} = V_{DD}\) exactly, and no current flows.
- Region 2: the n-device enters saturation while the p-device stays in triode. The output begins to fall and a small current starts to flow through both devices.
- Region 3: both devices are saturated. Both behave as current sources, the incremental output resistance is very high, and the gain is at its maximum — this is the near-vertical part of the curve and the whole transition happens within about 200 mV of input.
- Region 4: the p-device saturates while the n-device enters triode; the output continues to fall towards ground.
- Region 5, \(V_{in} > V_{DD} - |V_{Tp}|\): the p-device is cut off. \(V_{out} = 0\) exactly, and again no current flows.
The current through the pair is zero at both ends and peaks in region 3. Sketched against \(V_{in}\) it is a single narrow pulse centred on the switching threshold, and it is the origin of the short-circuit component of dynamic power discussed later.
The switching threshold \(V_M\) is the input voltage at which \(V_{out} = V_{in}\), the middle of region 3. Setting the two saturation currents equal, with \(k = \mu C_{ox}W/L\) for each device,
With matched devices, \(k_p = k_n\) and \(|V_{Tp}| = V_{Tn}\), this collapses to \(V_M = V_{DD}/2 = 2.5\ \text{V}\) — the symmetrical threshold that gives CMOS its equal noise margins. If instead the p-device is left the same width as the n-device, \(k_p/k_n = 0.4\) and \(V_M\) falls to 2.16 V, moving the threshold and unbalancing the margins.
Matching \(k_p\) to \(k_n\) is not automatic, because hole mobility in silicon is roughly 2.5 times lower than electron mobility. To equalise them the p-channel device must be made about 2.5 times wider than the n-channel device, and that is exactly how a real CMOS inverter is drawn on the mask. It is the reason a CMOS cell is not symmetrical on a die even though its schematic is.
The threshold at \(V_{DD}/2\) is also why the CMOS input specification is quoted as fractions of the supply — \(V_{IH} = 0.7V_{DD}\) and \(V_{IL} = 0.3V_{DD}\) — rather than as fixed voltages. At 5 V that gives 3.5 V and 1.5 V, and margins of 0.90 V and 1.17 V. Chapter 15 shows what happens when a TTL output, which knows nothing about \(V_{DD}\), has to satisfy a 3.5 V requirement.
3 Series and Parallel: Building NAND and NOR
Every static CMOS gate is built to one rule. The pull-down network of n-channel devices connects the output to ground for exactly those input combinations that should give a 0; the pull-up network of p-channel devices is its dual, connecting the output to \(V_{DD}\) for every other combination. Series in one network becomes parallel in the other. The two networks are complementary, so exactly one of them conducts for any input pattern, and the zero-static-current property of the inverter carries over to gates of any complexity.
For a NAND, the output must be LOW only when A and B are both HIGH, so the pull-down is two n-devices in series; its dual, the pull-up, is two p-devices in parallel. For a NOR, the output must be LOW when A or B is HIGH, so the pull-down is two n-devices in parallel and the pull-up is two p-devices in series. Both use four transistors, and a schematic capture tool would call them equally expensive. They are not.
Take the inverter as the unit: an n-device of width \(W\) and a p-device of width \(2.5W\), a total of 3.5 units, giving equal rise and fall. Now build each gate so that its worst-case pull-up and pull-down resistances match the inverter’s, which is what an equal-delay library demands. Two devices in series have twice the resistance of one, so each must be made twice as wide to compensate.
| Gate | Pull-down (n) | Pull-up (p) | Total width | Relative to inverter |
|---|---|---|---|---|
| Inverter | 1 device, \(W\) | 1 device, \(2.5W\) | 3.5\(W\) | 1.00 |
| 2-input NAND | 2 in series, \(2W\) each | 2 in parallel, \(2.5W\) each | 9\(W\) | 2.57 |
| 2-input NOR | 2 in parallel, \(W\) each | 2 in series, \(5W\) each | 12\(W\) | 3.43 |
The NOR needs a third more transistor width than the NAND for the same speed, and the reason is that its series stack falls in the pull-up network, where the devices were already 2.5 times too wide to begin with. Series \(\times\) weak is the expensive combination; series \(\times\) strong is the cheap one.
If the widths are not adjusted and every device is left at inverter size, a 2-input NOR has a worst-case pull-up resistance five times that of the inverter, against twice for the NAND’s pull-down. Chapter 10 showed that NAND and NOR are both universal, so the choice is free at the algebra level — and CMOS silicon settles it in favour of NAND. This is why synthesis tools map to NAND-dominant netlists.
The same argument limits fan-in. A four-input NAND has four n-devices in series, and because each internal node between them carries its own capacitance, the delay of a series chain of \(n\) devices grows roughly as \(n(n+1)/2\) rather than as \(n\): a factor of 3 for two inputs and 10 for four. Practical libraries stop at four inputs and build an eight-input function as a tree of two NANDs and a NOR, which is faster than the single wide gate despite having two levels.
4 The Transmission Gate
Static CMOS as described so far can only build inverting functions with the output driven from a rail. There is a second circuit element the technology offers almost free: a switch that connects two nodes without amplifying, buffering or inverting.
A single n-channel device makes a poor switch. Passing a HIGH through it, the source terminal rises with the signal, so \(V_{GS}\) shrinks; when the output reaches \(V_{DD} - V_{Tn}\) the device turns itself off, and the HIGH it delivers is a threshold short of the rail. A single p-channel device has the mirror problem and cannot pass a good LOW. Putting the two in parallel, with complementary gate drives, gives a transmission gate in which whichever device is failing, the other one is working.
The on-resistance is the parallel combination of the two channel resistances, and because they vary oppositely with input level the total is nearly constant across the whole range. A 74HC4066 analogue switch specifies about 50 Ω at \(V_{DD} = 5\ \text{V}\), rising to about 80 Ω at 4.5 V — the resistance depends strongly on supply, because that is what sets the gate overdrive.
A 74HC4066 with \(R_{on} = 50\ \Omega\) drives a node of 50 pF. Find the time constant and the 10–90 % rise time.
Fast enough to be invisible next to a 7 ns gate delay — but note that a transmission gate does not regenerate. Two in series give \(4\tau\) on the same node and a chain of them degrades both the edge rate and the logic level, so a buffer must be inserted every two or three stages.
The transmission gate is worth this attention because it is the cheapest multiplexer in existence. Two of them with complementary controls make a 2-to-1 selector out of four transistors, where a gate-level implementation from Chapter 19 needs three gates and a dozen. The same pair, with the output fed back to the input, is the storage element inside a CMOS D latch (Chapter 21), and an array of them is the switch matrix that routes signals inside an FPGA (Chapter 28). It also passes analogue signals, which is what makes CMOS analogue multiplexers and switched-capacitor filters possible — a static logic gate cannot do that at all.
5 Dynamic Power and the Effect of Supply Scaling
If a CMOS gate draws no static current, where does the heat in a working chip come from? Follow the charge on the load capacitance through one complete cycle.
On the LOW-to-HIGH output transition, the p-device connects \(C_L\) to \(V_{DD}\) and the supply delivers a charge \(Q = C_LV_{DD}\), so it does work \(C_LV_{DD}^{2}\). Half of that, \(\tfrac{1}{2}C_LV_{DD}^{2}\), ends up stored in the capacitor; the other half is dissipated in the resistance of the p-channel. On the HIGH-to-LOW transition the capacitor discharges through the n-channel and the stored half is dissipated there. So a full cycle takes \(C_LV_{DD}^{2}\) joules from the supply, and every joule of it becomes heat:
Two results are worth noticing. The energy per transition does not depend on how fast the transition is or on the on-resistance of the devices — only on the charge moved. And exactly half the energy is wasted no matter how good the transistors are, which is a fundamental limit of switching a capacitor between two rails.
Data sheets fold the gate’s own internal switching charge, and the short-circuit current that flows while both devices conduct in region 3, into a single equivalent power dissipation capacitance \(C_{PD}\). For the 74HC00 this is 22 pF per gate, so the working expression is \(P = (C_{PD} + C_L)V_{DD}^{2}f\).
Twenty 74HC gates each drive about 30 pF of track and input capacitance from a 5 V supply with a clock of 8 MHz. On average half the gates change state on each clock edge.
The quiescent dissipation of the same twenty gates is \(20 \times 25\ \mu\text{W} = 0.5\ \text{mW}\). Switching has multiplied the power by 120. Repeat the calculation at 3.3 V:
A saving of 56 % for no change whatever to the logic. The factor is \((3.3/5)^{2} = 0.436\), and it is the single most effective power reduction available to a digital designer.
That saving is not free, and the table below sets out what it costs. Delay in a MOSFET circuit scales roughly as \(V_{DD}/(V_{DD}-V_T)^{2}\), because lowering the supply reduces the current available to charge the load faster than it reduces the voltage swing that must be traversed. And the noise margin, being a fixed fraction of the supply, falls in direct proportion.
| \(V_{DD}\) | Dynamic power (relative) | Delay (relative, \(V_T = 0.7\ \text{V}\)) | \(NM_H = NM_L\) on the 70/30 rule |
|---|---|---|---|
| 5.0 V | 1.00 | 1.00 | 1.40 V |
| 3.3 V | 0.44 | 1.81 | 0.89 V |
| 2.5 V | 0.25 | 2.85 | 0.65 V |
| 1.8 V | 0.13 | 5.50 | 0.44 V |
Halving the supply from 5 V to 2.5 V therefore buys a factor of four in power at a cost of nearly three in speed and more than two in noise immunity. Real processes recover the speed by reducing \(V_T\) along with \(V_{DD}\) — which raises subthreshold leakage, and so returns the static power that CMOS was chosen to avoid. The whole of modern low-power design lives inside that circle.
Loading matters as much as frequency. Chapter 12 extracted an output resistance of 248 Ω for a 74HC00 from its data-sheet delays, giving 0.171 ns per picofarad of load: 7 ns at 15 pF, 21.6 ns at 100 pF. Since \(C_L\) appears in the delay expression and in the power expression alike, shortening a heavily loaded net improves both at once.
6 Latch-Up, Input Protection and Floating Inputs
Making n-channel and p-channel devices on the same die means putting one of them in a well of opposite doping. The result is four alternating layers — the p+ source of the p-device, the n-well, the p-substrate and the n+ source of the n-device — and those four layers form two parasitic bipolar transistors, a lateral pnp and a vertical npn, cross-coupled so that each supplies the other’s base current. That is a silicon-controlled rectifier sitting between \(V_{DD}\) and ground in every CMOS cell ever fabricated.
Normally the parasitic SCR is off, held there by the fact that neither parasitic transistor has any base drive. Latch-up is what happens when something injects enough current into the substrate or the well to develop about 0.7 V across the spreading resistance and turn one of them on. The pair then latches: each holds the other on, the path from supply to ground becomes a short circuit limited only by the power supply, and the only remedy is to remove the supply. If the supply can deliver an ampere, the part is destroyed in milliseconds.
The spreading resistance of the n-well between the well contact and the base of the parasitic pnp is about 1 kΩ. Find the injected current that will turn the parasitic transistor on.
Under a milliamp. A signal applied to an input while the supply is off, a hot-plugged connector, or an inductive kick from a relay coil on the same board all supply far more than that. This is why the rule is not “be careful” but “apply \(V_{DD}\) first and remove it last”.
The current usually arrives through an input or output pin, so every CMOS input carries a protection network: a diode to \(V_{DD}\), a diode to ground and a series resistance of a few hundred ohms to a few kilohms. Any input driven above \(V_{DD} + 0.5\ \text{V}\) or below \(-0.5\ \text{V}\) is clamped by a diode, and the data sheet limits the current through that diode — 20 mA for the 74HC family. Where a signal may exceed the rail, an external series resistor is the standard fix: a 5 V-powered 74HC input accidentally driven to 10 V through 1 kΩ passes \((10 - 5 - 0.7)/1\ \text{k}\Omega = 4.3\ \text{mA}\), comfortably inside the limit, where a direct connection would pass whatever the source could deliver.
Chapter 13 made this a matter of noise immunity for TTL, where a floating input behaves as a HIGH. For CMOS it is a matter of survival. A floating gate is an insulated plate with no DC path anywhere; stray charge and capacitive coupling drift it to an arbitrary voltage, and if that voltage lands near \(V_{DD}/2\) both transistors conduct at once. The gate then sits in region 3 of its transfer characteristic — a high-gain linear amplifier — and it will draw milliamps, oscillate at several megahertz, couple that oscillation into its neighbours, and heat up. Every unused input, including inputs of gates in the package that the design does not use at all, must be tied to \(V_{DD}\) or to ground as the logic requires. Unlike TTL, the connection is made directly: no series resistor is needed, because a CMOS input draws no current, and none is wanted, because the resistor would only re-create a high-impedance node.
Modern processes have made latch-up far less likely — guard rings, epitaxial substrates with a low-resistance layer beneath the wells, and generous well contacts all reduce the spreading resistances that make it possible. It has not been made impossible, and every one of the layout defences works by lowering \(R_{\text{well}}\) and \(R_{\text{sub}}\) so that far more injected current is needed to reach the same 0.7 V. The board-level defences are unchanged: sequence the supplies, series-limit any signal that could arrive first, and decouple properly.
7 Summary and Key Results
| Property | Origin | Value or expression |
|---|---|---|
| Static current | Reverse-biased junction leakage only | \(I_{CC} \le 20\ \mu\text{A}\) per 74HC00 package; 25 µW/gate |
| Output levels | No resistor and no junction in the conducting path | Rail to rail: 4.9 V at 20 µA, 4.4 V at 4 mA |
| Switching threshold | Equal saturation currents in the two devices | \(V_M = V_{DD}/2\) when \(k_p = k_n\), needing \(W_p \approx 2.5W_n\) |
| Noise margin | Thresholds at \(0.7V_{DD}\) and \(0.3V_{DD}\) | 0.90 V and 1.17 V at \(V_{DD} = 5\ \text{V}\) |
| NAND vs NOR | Series stack lands in the weaker network for NOR | 9\(W\) against 12\(W\) of transistor width for equal delay |
| Transmission gate | n and p devices in parallel cover each other's weak end | \(R_{on} \approx 50\ \Omega\) at 5 V; 5.5 ns rise into 50 pF |
| Dynamic power | Charge \(C V_{DD}\) moved from rail to ground each cycle | \(P = (C_{PD}+C_L)V_{DD}^{2}f\); 0.925 mW/gate at 1 MHz |
| Supply scaling | \(V_{DD}^{2}\) in power, \(V_{DD}/(V_{DD}-V_T)^2\) in delay | 5 V → 3.3 V: power ×0.44, delay ×1.81, margin ×0.64 |
| Latch-up | Parasitic pnp–npn SCR formed by well and substrate | Triggers at \(0.7\ \text{V}/R_{\text{well}} \approx 0.7\ \text{mA}\) |
8 Common Mistakes
The 25 µW per gate on the front of the data sheet is a quiescent figure. Worked Example 14.2 showed twenty gates rising from 0.5 mW at rest to 60 mW at 8 MHz — a factor of 120 — and Chapter 12 found the frequency above which 74HC dissipates more than 74LS to be only 2.16 MHz. A CMOS power figure without \(f\), \(V_{DD}\) and \(C_L\) attached to it is not an answer.
The gate is on the die and connected to the same supply whether the design uses it or not. Its floating input will drift towards \(V_{DD}/2\), put both transistors into conduction, and draw milliamps while oscillating and injecting noise into every other gate in the package. Tie every input of every gate, used or not, directly to a rail.
It passes a good LOW and a bad HIGH: the output stops at \(V_{DD} - V_{Tn}\), about 3.5 V on a 5 V supply. That level may still register as a HIGH at the next input, but it leaves the receiving inverter's p-channel device partly on, so the following stage draws static current for as long as the level is held — the one thing CMOS was chosen to avoid. Use the full transmission gate, or buffer the output of the pass device.
9 Chapter Review
1. Show why a CMOS inverter draws no static current in either logic state, and say what sets the current that it does draw.
With \(V_{in} = 0\) the n-channel device has \(V_{GS} = 0 < V_{Tn}\) and is cut off, so although the p-channel device is fully on there is no path to ground. With \(V_{in} = V_{DD}\) the p-channel device has \(V_{GS} = 0\) and is cut off, so although the n-channel device is on there is no path to the supply. In each case the series pair has one open member. The residual current is reverse-biased junction leakage — 20 µA maximum for a whole 74HC00 package at 25 °C — and it roughly doubles for every 10 °C rise in junction temperature.
2. A 2-input CMOS NAND and a 2-input CMOS NOR both use four transistors. Explain why the NAND is nevertheless the preferred structure, with numbers.
Taking an inverter as \(W\) of n-device and \(2.5W\) of p-device (the ratio needed to offset the 2.5-times lower hole mobility), a series pair must be twice as wide as a single device to keep the same resistance. The NAND's series stack is in the n network: \(2 \times 2W + 2 \times 2.5W = 9W\). The NOR's series stack is in the p network, whose devices were already 2.5 times oversized: \(2 \times W + 2 \times 5W = 12W\). The NOR therefore needs a third more transistor width, and correspondingly more area and input capacitance, for the same delay. Series stacking in the weak network is what costs.
3. A CMOS circuit of 5000 gates runs at 3.3 V and 25 MHz. Each switching gate drives 8 pF and a fifth of them change state per clock. Find the dynamic power. What would it be at 5 V?
\(P = N\alpha C V^2 f = 5000 \times 0.2 \times 8\times10^{-12} \times (3.3)^2 \times 25\times10^6\). The factor \(N\alpha C = 5000\times0.2\times8\ \text{pF} = 8\ \text{nF}\), so \(P = 8\times10^{-9} \times 10.89 \times 25\times10^{6} = 2.18\ \text{W}\). At 5 V the same expression gives \(8\times10^{-9}\times25\times25\times10^{6} = 5.0\ \text{W}\). The ratio is \((3.3/5)^2 = 0.436\), so the move to 3.3 V saves 2.8 W — the difference between a package that needs a heatsink and one that does not.
4. Why does a transmission gate need both device types, and what exactly goes wrong if only the n-channel device is used?
An n-channel device passing a rising signal has its source terminal following the output. As the output rises, \(V_{GS} = V_{DD} - V_{out}\) falls, and when \(V_{out}\) reaches \(V_{DD} - V_{Tn}\) the device turns itself off. It therefore delivers a HIGH that is one threshold short of the rail, about 3.5 V on a 5 V supply. That degraded HIGH is still above \(V_{IH}\), so the logic appears to work, but it leaves the p-channel device of the receiving inverter partly conducting, and the receiving gate then draws static current continuously. The p-channel device in parallel has the complementary weakness — it cannot pass a good LOW — so together they cover the whole range and the on-resistance is nearly flat.
5. Describe the latch-up mechanism and explain why applying an input signal before the supply is a specific way of triggering it.
The n-well and p-substrate needed to hold both device types create four alternating doped layers, which form a lateral pnp and a vertical npn cross-coupled so that each transistor's collector feeds the other's base — a parasitic SCR between \(V_{DD}\) and ground. It stays off while neither parasitic transistor has base drive. If injected current develops about 0.7 V across the well or substrate spreading resistance — only \(0.7\ \text{V}/1\ \text{k}\Omega = 0.7\ \text{mA}\) — one transistor turns on, the pair latches, and the resulting low-resistance path from supply to ground destroys the part unless the supply is removed. Applying a signal while \(V_{DD}\) is at 0 V forward-biases the input protection diode to the supply rail, which injects exactly this kind of current directly into the substrate, with nothing to limit it. Hence: supply first, signals afterwards, and a series resistor on any input that might arrive early.