By the end of this chapter you should be able to:
- State the four conditions that must hold at any interface between two logic families, and check them from data-sheet values.
- Explain why a 74LS output cannot drive a 74HC input directly, size the pull-up resistor that fixes it, and verify the choice against sink current and rise time.
- Calculate how many TTL inputs a given CMOS output can drive, and explain why a 4000B-series output can drive almost none.
- Explain what 74HCT changes relative to 74HC and quote the noise margins that result in each direction.
- Design a level shift between a 5 V and a 3.3 V rail in both directions, and state the limitations of a resistive divider.
- Describe the operation of an ECL current switch and explain why its negative supply, small swing and low output impedance all follow from the same design decision.
Chapters 13 and 14 each described a family that is internally consistent: every output in the 74LS catalogue satisfies every 74LS input, and the same is true within 74HC. Real boards are not internally consistent. A microcontroller runs at 3.3 V, the memory it addresses is 5 V CMOS, the level translator to the instrument bus is 74LS, and the clock recovery at the front end is ECL because nothing else was fast enough. At every boundary between two of those, somebody has to check that the output on one side can actually drive the input on the other.
The check is always the same four inequalities, and the failures are always one of a small number of patterns. This chapter states the conditions, works through the two classic 5 V cases in detail — TTL driving CMOS, where the voltage fails, and CMOS driving TTL, where the current fails — introduces the part that was designed specifically to make the problem go away, deals with the modern case of two different supply rails, and ends with ECL, whose negative supply and sub-volt swing make it the one family that will not talk to anything else without a translator.
1 The Four Conditions at Any Interface
Whenever the output of one device drives the inputs of \(n\) others, four inequalities must hold. Two are about voltage and two about current, and each pair has a HIGH-state member and a LOW-state member. Miss any one of them and the interface is broken, whatever the logic diagram says.
The voltage conditions are the ones a beginner checks and the current conditions are the ones that are forgotten, largely because they are satisfied automatically inside a family and so never come up until two families meet. The difference between the two sides of each inequality is the margin — noise margin for the voltage pair, spare drive for the current pair.
Three points make the check less mechanical than it looks. First, the conditions must hold in both directions of a bidirectional connection, and the two directions may need different remedies. Second, they must hold at the extremes of the specification, not at typical values: the reason a 74LS HIGH “measures 3.4 V so it must be fine” is not an argument is that \(V_{OH(\min)}\) is 2.7 V and some parts really do produce it. Third, the current conditions must be evaluated with the actual mixed load — the arithmetic of Worked Example 12.2, subtracting each dissimilar load before dividing.
There is a fifth consideration that is not an inequality but matters as much in practice: the edge rate. A CMOS input driven slowly through its transition region has both transistors conducting for the whole of the transit, which wastes power and, in a gate with any internal feedback, can produce multiple output transitions. Manufacturers specify a maximum input rise and fall time — typically 500 ns for 74HC at 5 V — and a passive pull-up that satisfies all four voltage and current conditions can still violate it.
2 TTL Driving CMOS and the Pull-Up That Fixes It
Take a 74LS00 driving four 74HC04 inputs, both on the same 5 V supply, and apply the four tests.
| Condition | Driver: 74LS | Receiver: 74HC | Result |
|---|---|---|---|
| \(V_{OH} \ge V_{IH}\) | 2.7 V | 3.5 V | fails by 0.8 V |
| \(V_{OL} \le V_{IL}\) | 0.5 V | 1.5 V | passes, 1.0 V to spare |
| \(I_{OH} \ge n I_{IH}\) | 400 µA | 4 × 1 µA = 4 µA | passes by a factor of 100 |
| \(I_{OL} \ge n I_{IL}\) | 8 mA | 4 × 1 µA = 4 µA | passes by a factor of 2000 |
Exactly one condition fails, and it fails for a reason traced in Chapter 13: a TTL totem-pole HIGH is the supply less an emitter–follower drop and a diode drop, so it cannot reach the rail. A CMOS input, meanwhile, wants \(0.7V_{DD}\). The two specifications were written on different assumptions and there is no operating point at which they meet.
The remedy is to add a resistor from the output node to \(V_{CC}\). In the LOW state it does nothing useful and simply adds current for the output transistor to sink. In the HIGH state, once the totem-pole’s emitter follower has lifted the node to about 3.5 V, that transistor turns itself off — its own \(V_{BE}\) has collapsed — and the resistor takes over, pulling the node the rest of the way to the rail against nothing but four microamps of CMOS input leakage.
A 74LS00 with \(I_{OL} = 8\ \text{mA}\) at \(V_{OL} = 0.5\ \text{V}\) drives four 74HC inputs, each 1 µA and about 5 pF, on a track contributing a further 15 pF. Find \(R_p\).
Lower bound — the LOW state. The resistor current is added to whatever else the output must sink. Allocating half the 8 mA budget to the resistor:
Upper bound — the rise time. The HIGH edge above 3.5 V is a passive RC into \(C = 4(5) + 15 = 35\ \text{pF}\). Requiring a 10–90 % rise no slower than 200 ns:
Choice. Take the standard 2.2 kΩ, and check it:
- LOW state: \(I_R = 4.5/2200 = 2.05\ \text{mA}\), a quarter of the 8 mA budget, leaving 5.95 mA for other TTL loads on the same node.
- HIGH state: \(V_{OH} = 5 - (2.2\ \text{k}\Omega)(4\ \mu\text{A}) = 4.99\ \text{V}\), giving \(NM_H = 4.99 - 3.5 = 1.49\ \text{V}\) where before there was none at all.
- Rise time: \(2.2 \times 2200 \times 35\ \text{pF} = 169\ \text{ns}\), inside the 500 ns the 74HC data sheet allows.
- Power: while the output is LOW the resistor dissipates \((4.5)^2/2200 = 9.2\ \text{mW}\), about five 74LS gates’ worth. This is the real cost of the fix, and it is why an interface of this kind is done once at a boundary rather than on every net.
An open-collector driver is the better choice when the CMOS is on a higher rail. A 7407 buffer, rated to 30 V and 40 mA, drives a 4000B input on a 15 V supply directly: with 5 loads, \(R_{p(\max)} = (15 - 10.5)/(250\ \mu\text{A} + 5\ \mu\text{A}) = 17.6\ \text{k}\Omega\) and \(R_{p(\min)} = 14.6/40\ \text{mA} = 365\ \Omega\); 4.7 kΩ sits sensibly inside that and gives \(V_{OH} = 13.8\ \text{V}\). The rise time is 414 ns into 40 pF, so this arrangement is for control signals, not clocks.
3 CMOS Driving TTL and the Current-Sinking Problem
Reverse the direction and the failing condition changes completely. A CMOS output swings rail to rail, so both voltage conditions pass with margin to spare: \(V_{OH} = 4.4\ \text{V}\) against the 2.0 V a TTL input needs, and \(V_{OL} = 0.33\ \text{V}\) against the 0.8 V it allows. The HIGH current condition passes too, because a TTL input in the HIGH state takes only tens of microamps.
What fails is the LOW-state current. A TTL input pushes 0.4 mA (74LS) or 1.6 mA (standard 74) back out of its pin, and the CMOS n-channel device has to swallow all of it while staying below 0.8 V.
| CMOS driver | \(I_{OL}\) | 74LS inputs (0.4 mA) | Standard 74 inputs (1.6 mA) |
|---|---|---|---|
| 4000B at 5 V | 0.51 mA | 1 | 0 — cannot drive even one |
| 4050B buffer at 5 V | 4 mA | 10 | 2 |
| 74HC / 74HCT | 4 mA | 10 | 2 |
| 74AC / 74ACT | 24 mA | 60 | 15 |
The first row is the one that catches people. The original 4000B series was designed for battery-powered instruments where nothing much was driven, and at 5 V its output transistors are tiny: 0.51 mA of guaranteed sink current is not enough for a single standard TTL input, and it is barely enough for one 74LS input. Connecting a 4011 to a 7400 and expecting it to work is a well-worn way of producing a circuit that reads a permanent HIGH.
No passive component will help a 4000B drive TTL, because nothing external can increase the output’s sink capability. The answer is a buffer — a 4050B non-inverting or 4049B inverting hex buffer, whose output devices are made eight times larger — or a change of family to 74HCT, which has the 4 mA output as standard. Adding a resistor here would only make the LOW level worse.
Note also that the 4000B family runs on anything from 3 V to 18 V, and if it is on a rail above 5 V its output HIGH will exceed the 5.5 V absolute maximum of a TTL input. In that direction the interface fails on a rating rather than on a logic condition, and the remedy is a 4049B or 4050B, which uniquely among CMOS parts tolerate input voltages above their own supply and so double as down-translators from a 15 V rail to a 5 V one.
4 74HCT: the Purpose-Built Bridge
Both of the problems above come from the same root: TTL thresholds are set by silicon junctions and sit at 0.8 V and 2.0 V regardless of supply, while CMOS thresholds are set at fractions of \(V_{DD}\) and sit at 1.5 V and 3.5 V. If a part could be built with CMOS outputs and TTL input thresholds, it would satisfy both worlds at once. That part is 74HCT, and the T stands for TTL-compatible.
The change is made in the silicon, not by adding circuitry: the p-channel device in the input inverter is made wider relative to the n-channel one, which pulls the switching threshold \(V_M\) down from 2.5 V towards about 1.4 V, and the specification is then written as \(V_{IH} = 2.0\ \text{V}\), \(V_{IL} = 0.8\ \text{V}\). Everything else — the rail-to-rail output, the microamp input current, the 4 mA drive, the \(CV^{2}f\) power — is unchanged from 74HC.
| Link | \(NM_H\) | \(NM_L\) | LOW-state fan-out | Verdict |
|---|---|---|---|---|
| 74LS → 74HC | 2.7 − 3.5 = −0.8 V | 1.5 − 0.5 = 1.0 V | — | Fails; needs a pull-up |
| 74LS → 74HCT | 2.7 − 2.0 = 0.7 V | 0.8 − 0.5 = 0.3 V | 8 mA / 1 µA ≈ 8000 | Direct connection |
| 74HCT → 74LS | 4.4 − 2.0 = 2.4 V | 0.8 − 0.33 = 0.47 V | 4 mA / 0.4 mA = 10 | Direct connection |
| 74HC → 74LS | 4.4 − 2.0 = 2.4 V | 0.8 − 0.33 = 0.47 V | 10 | Also fine — this direction never needed help |
Read the second row carefully, because it is what 74HCT costs. Its LOW noise margin against a 74LS driver is 0.3 V, exactly the same as 74LS driving 74LS, and far worse than the 1.17 V a pure 74HC input would have had. That is unavoidable: the moment a part accepts anything above 0.8 V as a LOW it has thrown away the margin that the \(0.3V_{DD}\) threshold gave it. 74HCT is the right part at a boundary and the wrong part everywhere else — a board of 74HCT throughout has TTL noise immunity with CMOS power consumption, which is half of each family’s advantage.
The practical arrangement is therefore to use 74HCT only where a TTL signal enters the CMOS part of the design, and 74HC beyond it. The same logic applies one generation later with 74ACT against 74AC, and again with the LVC and LVT families that bridge 3.3 V logic to 5 V systems.
5 Level Shifting Between Supply Voltages
Two devices on different supplies raise the same four questions with different numbers. The modern case is 3.3 V logic meeting 5 V logic, and as usual the two directions are not equally difficult.
3.3 V driving 5 V. A 3.3 V CMOS output produces about 3.0 V in the HIGH state. A 5 V 74HC input needs \(0.7 \times 5 = 3.5\ \text{V}\), so the connection fails — the same 0.5 V shortfall, from the same cause, as the TTL-to-CMOS case. A 5 V 74HCT input needs only 2.0 V, so it works directly with 1.0 V of margin. The cheapest level shift upward is therefore to choose an HCT-threshold receiver and connect the wire.
5 V driving 3.3 V. Here the difficulty is a rating rather than a level: 3.3 V a 5 V input would be clamped by the receiver’s protection diode to \(V_{DD} + 0.5 = 3.8\ \text{V}\), and the diode current has to go somewhere. Many 3.3 V parts are specified as 5 V-tolerant, meaning that the diode to \(V_{DD}\) has been omitted and the input can sit at 5 V safely; with such a part the wire is again enough. Otherwise the level must be reduced.
Design a divider for a slow control signal and state its limits. Take \(R_1\) in series and \(R_2\) to ground, with the receiving input drawing 1 µA and presenting 15 pF.
With \(R_1 = 1\ \text{k}\Omega\) and \(R_2 = 2\ \text{k}\Omega\):
Check it against the receiver: \(V_{IH} = 0.7 \times 3.3 = 2.31\ \text{V}\), so the HIGH margin is 1.02 V. The 3.33 V level is 0.03 V above the 3.3 V rail, which the protection diode absorbs at a few microamps — acceptable, though \(R_2 = 1.8\ \text{k}\Omega\) would avoid it.
Now the limits, which matter more than the ratio:
- Speed. The 667 Ω source drives 15 pF, giving a 10–90 % rise of \(2.2 \times 667 \times 15\ \text{pF} = 22\ \text{ns}\). Allowing ten time constants per bit period caps the signal at a few megahertz. A divider is for a reset or an enable, never for a clock or a bus.
- Power. Whenever the input is HIGH the chain draws \(5/3\ \text{k}\Omega = 1.67\ \text{mA}\) and dissipates 8.3 mW — continuously, and on every line so treated. On a battery-powered board this alone can exceed the logic’s own consumption.
- Direction. A divider works one way only. A bidirectional line needs an active translator: the standard circuit is a single small n-channel MOSFET with its gate on the lower rail, its source on the 3.3 V side and its drain on the 5 V side, with a pull-up on each side.
For anything fast or bidirectional the right answer is a purpose-built translator. Families such as 74LVC accept 5 V on their inputs while running from 3.3 V, and dual-supply devices take \(V_{CCA}\) and \(V_{CCB}\) and translate in both directions with proper drive at both ends. The lesson is the same one as 74HCT: the interface problem was solved once, in silicon, and reproducing it with discrete components is worth doing only for a signal that is slow and unidirectional.
6 ECL and a Comparison of the Families
Emitter-coupled logic is the odd one out in every respect, and every one of its peculiarities follows from a single decision: never let a transistor saturate. Chapter 13 showed that storage time is what limits TTL, and that a Schottky clamp reduces it. ECL avoids saturation entirely, by never switching a transistor fully on or fully off but instead steering a fixed current from one side of a differential pair to the other.
The consequences cascade. Because the transistors stay in the active region, the collector swing must be kept small — \(I_ER_C = 3.99\ \text{mA} \times 220\ \Omega = 0.88\ \text{V}\) — which gives a propagation delay of 2 ns but leaves only 145 mV of noise margin. Because the tail current flows whether the gate is switching or not, dissipation is a constant 25 mW per gate and independent of frequency, the opposite of CMOS. Because the outputs are emitter followers, their output impedance is about 7 Ω, which is exactly what is needed to drive a 50 Ω transmission line — and driving transmission lines properly is why ECL could be used at frequencies where other families were defeated by reflections.
The negative supply looks perverse until you see the reason. Putting \(V_{CC}\) at ground and \(V_{EE}\) at −5.2 V means the signal levels, −0.9 V and −1.75 V, are referenced to the ground plane rather than to the supply rail. Any noise on the 5.2 V supply is common to the collector resistors of both halves of the differential pair and cancels in the output; noise on ground would not cancel, and ground is the node an engineer can make quiet. With a 145 mV noise margin, that choice is not a refinement but a necessity.
Nothing about those levels is compatible with anything else, so ECL boundaries always use translators — the 10124 converts TTL to ECL and the 10125 converts ECL to TTL — and ECL sections of a board are laid out with a continuous ground plane, controlled-impedance traces and terminations of 50 Ω to a −2 V rail.
| Family | Supply | Levels (HIGH / LOW) | Worst \(NM\) | \(t_{pd}\) | Power/gate | Drives directly |
|---|---|---|---|---|---|---|
| 74 | +5 V | 2.4 / 0.4 V | 0.40 V | 9 ns | 10 mW | 74, 74LS, 74HCT |
| 74LS | +5 V | 2.7 / 0.5 V | 0.30 V | 9.5 ns | 2 mW | 74LS, 74HCT; 74HC only with a pull-up |
| 74HC | 2–6 V | 4.4 / 0.33 V | 0.90 V | 9 ns | 0.925 mW at 1 MHz | 74HC, 74HCT, 74LS (10 loads) |
| 74HCT | +5 V | 4.4 / 0.33 V | 0.47 V | 9 ns | 0.925 mW at 1 MHz | Everything on 5 V — the bridge part |
| 74AC | 2–6 V | 4.4 / 0.37 V | 0.90 V | 5 ns | 2 mW at 1 MHz | 74AC, 74HC, 74LS (60 loads) |
| 4000B | 3–18 V | \(V_{DD}\) / 0 V | \(0.3V_{DD}\) | 50 ns at 5 V | ≈ 0 | CMOS only; needs a 4050B to reach TTL |
| ECL 10K | −5.2 V | −0.9 / −1.75 V | 0.145 V | 2 ns | 25 mW | ECL only; 10124/10125 to translate |
The table is also a summary of the whole of Part 3. Read across any row and the trade-off of Chapter 12 is visible: the two fastest entries have the highest power and, in the ECL case, the worst noise margin; the lowest-power entry is the slowest; and the family with the best noise margin, 74HC at 0.90 V, is beaten on compatibility by its own variant that deliberately gives half of it away. From Chapter 16 onwards the logic diagrams return to abstract symbols — but every one of those symbols is a package with four numbers on its data sheet, and it is those numbers that decide whether the board works.
7 Summary and Key Results
| Interface | Condition violated | Remedy | Numbers |
|---|---|---|---|
| 74LS → 74HC, 5 V | \(V_{OH} = 2.7\ \text{V} < V_{IH} = 3.5\ \text{V}\) | Pull-up resistor to \(V_{CC}\) | \(1.13\ \text{k}\Omega \le R_p \le 2.60\ \text{k}\Omega\); use 2.2 kΩ |
| 5 V TTL → 15 V CMOS | Level and rail both wrong | Open-collector 7407 with pull-up to 15 V | \(365\ \Omega \le R_p \le 17.6\ \text{k}\Omega\); use 4.7 kΩ |
| 4000B → 74LS | \(I_{OL} = 0.51\ \text{mA}\) against 0.4 mA per input | 4050B/4049B buffer, or change to 74HCT | Fan-out 1 becomes 10 |
| 74HC → 74LS | None — this direction works | Connect directly | 10 LS loads; \(NM_L = 0.47\ \text{V}\) |
| 74LS → 74HCT | None — HCT has TTL thresholds | Connect directly | \(NM_H = 0.7\ \text{V}\), \(NM_L = 0.3\ \text{V}\) |
| 3.3 V → 5 V | \(3.0\ \text{V} < 3.5\ \text{V}\) for 74HC | Receive on 74HCT instead | 1.0 V of margin |
| 5 V → 3.3 V | Exceeds the receiver's rail | 5 V-tolerant input, divider, or translator | 1 kΩ/2 kΩ gives 3.33 V, 22 ns, 8.3 mW |
| Anything ↔ ECL | Negative rail, 0.85 V swing | 10124 and 10125 translators | Levels −0.9 V / −1.75 V; \(NM = 145\ \text{mV}\) |
8 Common Mistakes
Both classic 5 V failures are invisible to half the check. TTL driving CMOS passes both current conditions with a factor of a hundred to spare and still fails, because \(V_{OH}\) is 0.8 V short. CMOS driving TTL passes both voltage conditions with volts to spare and still fails, because a 4000B output cannot sink 1.6 mA. Evaluate all four inequalities every time; the one that fails tells you what component to add.
74HCT accepts anything above 2.0 V as a HIGH and anything below 0.8 V as a LOW, so its LOW noise margin against a 74LS driver is 0.30 V — TTL's own figure, not CMOS's 1.17 V. Use it at the boundary where a TTL signal actually arrives, and use 74HC for everything downstream, or the design pays CMOS prices for TTL noise immunity.
A 1 kΩ/2 kΩ divider presents 667 Ω to 15 pF of input capacitance, giving a 22 ns edge and an upper limit of a few megahertz — and it draws 1.67 mA continuously in the HIGH state while working in one direction only. It is a legitimate solution for a reset line or a jumper. On a clock it slows the edge until the receiving CMOS input spends its whole transition in the linear region, and on a bidirectional bus it does not work at all.
9 Chapter Review
1. List the four interface conditions and show, with data-sheet numbers, which one is violated when a 74LS output drives 74HC inputs on a common 5 V supply.
The conditions are \(V_{OH} \ge V_{IH}\), \(V_{OL} \le V_{IL}\), \(I_{OH} \ge nI_{IH}\) and \(I_{OL} \ge nI_{IL}\). For 74LS driving 74HC: \(V_{OH} = 2.7\ \text{V}\) against \(V_{IH} = 3.5\ \text{V}\) — violated by 0.8 V. \(V_{OL} = 0.5\ \text{V}\) against \(V_{IL} = 1.5\ \text{V}\) — passes with 1.0 V spare. \(I_{OH} = 400\ \mu\text{A}\) against a few microamps of CMOS input leakage, and \(I_{OL} = 8\ \text{mA}\) against the same — both pass by orders of magnitude. Only the HIGH voltage condition fails, which is why a single pull-up resistor is a complete fix.
2. A 74LS gate drives six 74HC inputs (1 µA, 5 pF each) plus 25 pF of track, on 5 V. The rise time must not exceed 150 ns and no more than 3 mA of the 8 mA sink budget may go to the resistor. Choose \(R_p\).
Lower bound from the LOW state: \(R_{p(\min)} = (5-0.5)/3\ \text{mA} = 1.5\ \text{k}\Omega\). Load capacitance \(C = 6 \times 5 + 25 = 55\ \text{pF}\), so the upper bound from the rise time is \(R_{p(\max)} = 150\ \text{ns}/(2.2 \times 55\ \text{pF}) = 1.24\ \text{k}\Omega\). The two bounds cross, so no single resistor satisfies both: either the rise-time budget must be relaxed to about 182 ns (which 2.2 kΩ would give: \(2.2 \times 1500 \times 55\ \text{pF} = 182\ \text{ns}\) at 1.5 kΩ) or more sink current must be allowed. Allowing 4 mA gives \(R_{p(\min)} = 1.13\ \text{k}\Omega\) and 1.2 kΩ then satisfies both at 145 ns and 3.75 mA. The point of the question is that the window can close, and when it does the answer is to change a budget, not to pick a value outside the bounds.
3. Why can a 4000B output at 5 V not drive a standard 7400 input, when its voltage levels are better than TTL's own in both states?
Because the failure is in current, not voltage. A standard TTL input in the LOW state forward-biases the emitter junction of its multi-emitter input transistor and pushes up to 1.6 mA out of the pin into whatever is driving it. A 4000B output at 5 V guarantees a sink capability of only 0.51 mA at its rated \(V_{OL}\); asked to absorb 1.6 mA it comes out of saturation and its output rises well above the 0.8 V that the TTL input requires, so the LOW is never recognised. Its \(V_{OH} = 4.95\ \text{V}\) and \(V_{OL} = 0.05\ \text{V}\) are irrelevant, because they are only guaranteed at negligible load. The fix is a 4050B buffer or a 74HCT part, both of which offer 4 mA.
4. What exactly does 74HCT change relative to 74HC, and what does the change cost?
It changes only the input threshold, by widening the p-channel device of the input inverter so that the switching point falls from about 2.5 V to about 1.4 V. The specification then reads \(V_{IH} = 2.0\ \text{V}\) and \(V_{IL} = 0.8\ \text{V}\) instead of 3.5 V and 1.5 V, which is exactly what a TTL driver can supply. Outputs, input current, drive capability and power are unchanged. The cost is noise immunity: driven from a 74LS output whose \(V_{OL}\) may be 0.5 V, the LOW margin is \(0.8 - 0.5 = 0.3\ \text{V}\) instead of the 1.17 V a 74HC input would have had — a fourfold reduction. It should therefore be used only at the boundary where TTL signals actually arrive.
5. Explain why ECL uses a negative supply with the positive rail at ground, given that the logic would work equally well on +5.2 V with the negative rail grounded.
The logic levels are developed across the collector resistors, which are returned to \(V_{CC}\). Putting \(V_{CC}\) at ground makes the output levels, −0.9 V and −1.75 V, referenced to the ground plane. Noise on the −5.2 V rail then appears at the tail of the differential pair, where it is common to both halves and cancels in the difference between the two collectors; noise on \(V_{CC}\) would appear directly in the output levels and would not cancel. Since ground is the node that can be made quiet with a solid plane, and since the noise margin is only 145 mV, referencing the signals to it is worth more than the inconvenience of a negative supply. Grounding the negative rail instead would put the whole logic swing on top of a noisy supply and consume the margin immediately.