Logic Family Characteristics

1 Logic Levels and the Transfer Characteristic

A data sheet quotes four voltages — \(V_{OH(\min)}\), \(V_{OL(\max)}\), \(V_{IH(\min)}\) and \(V_{IL(\max)}\) — and Chapter 1 took them as given. They are not arbitrary. All four are read off one measured curve: the voltage transfer characteristic, or VTC, obtained by sweeping the input of an inverter slowly from 0 V to \(V_{CC}\) and recording the output. Everything a gate does electrically at DC is contained in that curve.

The curve of Figure 12.1 has three regions. In region A the input is low enough that the pull-down device is off and the pull-up device is fully on, so the output sits at the supply rail and barely moves as the input changes: the gain \(|dV_{out}/dV_{in}|\) is close to zero. Region C is the mirror image, with the pull-down device on and the output near ground. Between them lies the transition region, where both devices conduct and the gate behaves as a high-gain inverting amplifier; a 74HC04 typically swings its output over the full 5 V for an input change of about 200 mV, a gain of roughly 25.

Where exactly does “LOW” stop and “HIGH” begin? The convention that every manufacturer follows is the unity-gain criterion. \(V_{IL}\) is the input voltage at the lower point where the slope of the VTC equals \(-1\), and \(V_{IH}\) is the input voltage at the upper such point. The reason is worth stating carefully, because it is the electrical statement of the regeneration property that Chapter 1 argued for in words.

Suppose an input is displaced from its ideal value by a small amount \(\Delta V_{in}\). The output is displaced by \(|A|\,\Delta V_{in}\), where \(A\) is the local slope. If \(|A| < 1\) the disturbance is smaller at the output than it was at the input, and after a few stages it has vanished. If \(|A| > 1\) the disturbance grows, and after a few stages the signal has been driven out of its band entirely. The unity-gain points are therefore the exact boundary between an input the gate can clean up and one it will amplify into an error, which is why they, and not any convenient round number, define the valid input bands.

The corresponding output levels follow at once. \(V_{OH}\) is the output measured at the \(V_{IL}\) point and \(V_{OL}\) the output measured at the \(V_{IH}\) point, both taken with the worst-case load current flowing, because loading a real output pulls it away from the rail. That last clause matters: a 74LS output guarantees \(V_{OL} \le 0.4\ \text{V}\) when sinking 4 mA but only \(V_{OL} \le 0.5\ \text{V}\) when sinking its full rated 8 mA. The published levels are the pessimistic ones.

Notice that the TTL thresholds are fixed by the physics of silicon junctions and do not scale with the supply, whereas the CMOS thresholds are a fixed fraction of \(V_{DD}\). That single difference is the source of almost every interfacing difficulty in Chapter 15.

2 Noise Margin Derived from the Transfer Curve

With the four levels defined, the noise margins follow as the vertical gaps in Figure 12.1 between what a driver guarantees and what a receiver demands:

Both are worst-case quantities: they combine the weakest output a driver may produce with the fussiest input a receiver may present, at the extremes of temperature and supply tolerance. A typical part does far better, which is why a marginal board often works on the bench and fails in a warm cabinet.

The asymmetry of 74LS deserves a second look, because it explains a class of laboratory faults. The 0.30 V LOW margin is measured with the output sinking its full 8 mA. Every LOW output on a board returns that current through the ground network, and if several outputs switch LOW together the inductance of a shared ground track lifts the local ground reference. A 300 mV bounce is entirely ordinary on a solderless breadboard. It consumes the whole LOW noise margin, and the symptom is a circuit that is logically correct and behaves erratically.

3 Fan-In and Fan-Out

Fan-in is simply the number of inputs a gate has. It is the cheaper of the two parameters, but it is not free. In TTL the inputs are the emitters of a single multi-emitter transistor, so extra inputs cost little area and almost no speed — which is why 8-input TTL NAND gates such as the 7430 exist. In CMOS an \(n\)-input NAND puts \(n\) transistors in series in the pull-down path, and the delay of a series chain of \(n\) equal devices grows roughly as \(n(n+1)/2\) once the internal node capacitances are counted. Going from a 2-input to a 4-input CMOS NAND multiplies that factor from 3 to 10. Practical CMOS libraries therefore stop at four inputs and build wider functions as a tree, a point Chapter 14 returns to.

Fan-out is the number of similar inputs one output can drive while still meeting its guaranteed output levels. It is a current question, and there are two of them, because the currents flow in opposite directions in the two states.

In the LOW state the driver sinks current out of every load input; in the HIGH state it sources current into them. Whichever ratio is smaller is the fan-out, and the result is truncated, never rounded up.

For CMOS the DC calculation is almost meaningless. A 74HC input draws at most 1 µA, and a 74HC output is rated at 4 mA, so \(N = 4000\). No board is built that way, because the real limit on a CMOS output is capacitive, not resistive. Every input adds about 5 pF, every centimetre of track another 0.5–1 pF, and the driver must charge all of it through its own on-resistance within the timing budget.

4 Propagation Delay and Its Two Components

Propagation delay is measured between the 50 % points of the input and output transitions, and a data sheet always gives two of them, because a gate is not symmetrical:

• \(t_{PHL}\) — delay from the input edge to the output going from HIGH to LOW;
• \(t_{PLH}\) — delay from the input edge to the output going from LOW to HIGH.

The quantity \(t_{pd}\) quoted in comparison tables is the average of the two. It is a convenient summary and it is the wrong number for a timing analysis, where the larger of the two must be applied at every stage of the critical path.

Why do they differ? In a TTL totem-pole output the LOW-going edge is produced by a transistor driven hard into saturation, which pulls the node down through a few tens of ohms; the HIGH-going edge is produced by an emitter follower in series with a 130 Ω resistor, so it is slower. A standard 7400 has \(t_{PLH} = 11\ \text{ns}\) against \(t_{PHL} = 7\ \text{ns}\), and the asymmetry is exactly this. In CMOS the p-channel pull-up has two to three times the on-resistance of an equally wide n-channel pull-down, so the rise is naturally slower unless the designer widens the p-device to compensate — which the 74HC library does, giving nearly equal edges.

The delay itself has two parts. There is an intrinsic component, set by carrier transit and internal node capacitance and independent of what is connected outside, and a load-dependent component, which is the time the output takes to drag the external capacitance through the switching threshold at its own output resistance:

The 0.69 is \(\ln 2\), the fraction of an RC exponential needed to reach the 50 % point. The practical consequence is that \(t_{pd}\) is a straight line against \(C_L\), whose slope reveals the output resistance the data sheet does not print.

Delays accumulate along a path, so a four-level combinational network in 74LS costs \(4 \times 9.5 = 38\ \text{ns}\) against \(4 \times 3.0 = 12\ \text{ns}\) in 74S. Chapter 16 shows how the ripple-carry adder turns this into an \(O(n)\) penalty and how carry-look-ahead removes it; Chapter 24 shows how the same delay sets the maximum clock frequency of a synchronous counter.

5 Static and Dynamic Power Dissipation

Power dissipation is quoted per gate, and it has two entirely different origins depending on the technology. Getting the distinction right is what makes the frequency dependence in Figure 12.3 sensible rather than surprising.

A bipolar gate draws current continuously, because its transistors are biased into conduction in at least one of the two states. The data sheet gives two supply currents for the whole package, \(I_{CCH}\) with all outputs HIGH and \(I_{CCL}\) with all outputs LOW, and the average is taken because a real circuit spends about half its time in each state:

For the 7400, \(I_{CCH} = 4\ \text{mA}\) and \(I_{CCL} = 12\ \text{mA}\) for four gates, giving \(5 \times 8 = 40\ \text{mW}\) per package, or 10 mW per gate. For the 74LS00, \(I_{CCH} = 0.8\ \text{mA}\) and \(I_{CCL} = 2.4\ \text{mA}\), giving 8 mW per package or 2 mW per gate — the fivefold saving that made LS the default 74-series part for twenty years. The current is drawn whether the gate is switching or not, so TTL power is almost flat with frequency; it rises only slightly at high frequency because of the totem-pole current spike analysed in Chapter 13.

A CMOS gate has no conducting path from \(V_{DD}\) to ground in either stable state, so its static dissipation is only leakage: the 74HC00 specifies \(I_{CC} \le 20\ \mu\text{A}\) for the package at 25 °C, which is 100 µW for four gates, or 25 µW per gate — four hundred times less than 74LS. Its power comes almost entirely from charging and discharging capacitance:

\(C_L\) is the external load and \(C_{PD}\) is the power dissipation capacitance, a data-sheet parameter that lumps the gate’s own internal switching charge and its through-current into an equivalent capacitance. For the 74HC00, \(C_{PD} = 22\ \text{pF}\) per gate. Chapter 14 derives this expression from first principles.

Two design consequences follow immediately. First, the \(V_{DD}^{2}\) term is the reason the industry moved from 5 V to 3.3 V and then lower: the same circuit at 3.3 V dissipates \((3.3/5)^2 = 0.436\) of its 5 V figure, a 56 % saving for no change in architecture. Second, because \(C_L\) appears directly, capacitance on a fast node costs power as well as delay; keeping a clock net short is a power optimisation, not only a timing one.

6 The Speed–Power Product and the Family Comparison

Speed and power pull against each other. Within one technology, making a gate faster means lowering the resistances in it so that the same capacitances charge sooner, and that raises the current in direct proportion. The product of the two is therefore nearly constant, and it is the natural figure of merit:

Milliwatts multiplied by nanoseconds give picojoules, so the speed–power product is an energy: roughly the energy the gate spends on one switching event. Lower is better, and a genuine technology improvement is one that lowers it.

Compare 74 with 74S. The Schottky family is three times as fast, 3 ns against 9 ns, and takes almost twice the power, 19 mW against 10 mW; the product falls from 90 pJ to 57 pJ, so Schottky clamping is a real improvement and not merely a different operating point. 74LS then keeps the standard family’s speed while cutting the power fivefold, giving 19 pJ, and 74ALS reaches 4.8 pJ. That progression is the history of bipolar logic in one column of numbers.

The CMOS rows carry two figures each, and that is the honest way to quote them. A static speed–power product of 0.23 pJ is real but describes a circuit doing nothing; the figure at a stated frequency is what a designer compares. Quoted at 1 MHz, 74HC at 8.3 pJ still beats 74LS at 19 pJ; quoted at 10 MHz it does not.

One caution about ECL, developed in Chapter 15. Its 0.145 V noise margin looks catastrophic beside CMOS’s 0.90 V until you notice that ECL signals are usually carried differentially on matched transmission lines, where interference appears as a common-mode voltage that the differential input rejects. The single-ended margin is the wrong measure for the way the family is actually used — a reminder that a specification number only means something alongside the practice it was written for.

7 Summary and Key Results

8 Common Mistakes

9 Chapter Review