By the end of this chapter you should be able to:
- State the characteristic table and characteristic equation of the SR, D, JK and T flip-flops, and derive each equation from its table with a K-map.
- Explain why a design procedure needs the excitation table rather than the characteristic table, and where the don't-care entries in an excitation table come from.
- Apply a five-step procedure to convert any one of the four flip-flop types into any other.
- Derive and draw the conversion logic for JK→D, JK→T, D→JK, D→T, SR→JK and T→D.
- Verify a conversion by substituting the derived input equations into the characteristic equation of the available flip-flop and recovering the target characteristic equation.
- Identify the conversions in which the forbidden or race-prone input combinations of the source flip-flop need checking, and show why the derived logic never produces them.
A laboratory drawer rarely contains the flip-flop a design asks for. A counter designed on paper with T flip-flops has to be built from the 74LS74 dual D packages that happen to be in stock; a sequence detector whose state equations came out neatly in JK form has to run on the D flip-flops that a programmable device offers, because a look-up table followed by a register is all the silicon provides. The question this chapter answers is therefore a practical one: given the flip-flop you have, what combinational logic placed in front of it will make it behave exactly like the flip-flop you wanted?
The answer is a short, mechanical procedure, and it rests on one idea. Chapter 21 described each flip-flop by a characteristic table, which answers the analysis question — given the inputs and the present state, what is the next state? Design asks the opposite question — given the present state and the next state I want, what inputs will get me there? Answering that means inverting the characteristic table, and the inverted table is called the excitation table. Once the excitation table of the available flip-flop is written down, every conversion in this chapter, and every synchronous counter in Chapters 23 and 24, and every state machine in Chapter 26, is a K-map problem of the kind Chapter 8 already solved.
1 Characteristic Tables and Characteristic Equations
Chapter 21 built four flip-flops and described each by a table of behaviour. Before anything can be converted into anything else, those four descriptions need to be in a single algebraic form, because the check at the end of every conversion is an algebraic identity rather than a rewiring diagram.
A characteristic table lists the next state \(Q^+\) — the value the output takes after the active clock edge — for every combination of the control inputs and the present state \(Q\). A characteristic equation is that table minimised into a Boolean expression for \(Q^+\). Both say the same thing; the equation is simply the form you can substitute into.
| Flip-flop | Inputs | Behaviour on the active edge | Characteristic equation |
|---|---|---|---|
| SR | \(S, R\) | 00 hold, 01 reset, 10 set, 11 forbidden | \(Q^+ = S + R'Q\), with \(SR = 0\) |
| D | \(D\) | the output follows the input | \(Q^+ = D\) |
| JK | \(J, K\) | 00 hold, 01 reset, 10 set, 11 toggle | \(Q^+ = JQ' + K'Q\) |
| T | \(T\) | 0 hold, 1 toggle | \(Q^+ = TQ' + T'Q = T \oplus Q\) |
The JK equation is worth deriving rather than quoting, because the derivation is the pattern every later minimisation in this chapter follows. Its characteristic table has eight rows, listed on the left of Figure 22.1. Treating \(J\), \(K\) and \(Q\) as the three map variables, \(Q^+ = 1\) in the rows \(JKQ = \) 001, 100, 101 and 110. On a three-variable map the cells 100 and 110 form a pair in which \(K\) changes, giving \(JQ'\); the cells 001 and 101 form a pair in which \(J\) changes, giving \(K'Q\). No larger group exists, both are essential, and so
Read it as a sentence: the output becomes 1 either because \(J\) asks it to and it was 0, or because it was already 1 and \(K\) is not asking it to clear.
The SR equation needs one extra remark. Its table has only six legal rows, since \(S = R = 1\) drives both outputs of the cross-coupled pair low and leaves the final state undefined. Those two rows are entered on the map as don't-cares, which is exactly what lets the minimisation reach the compact \(Q^+ = S + R'Q\) instead of the longer \(Q^+ = SR' + R'Q\). The condition \(SR = 0\) is not decoration: it is part of the specification, and any conversion that produces an SR flip-flop's drive signals has to be checked against it.
Notice how differently the four devices are specified. D and T are completely determined — one input, one bit of freedom, no forbidden states. SR forbids one combination. JK forbids nothing and instead gives the fourth combination a useful meaning. That difference is the whole reason the conversions in this chapter are not all equally cheap.
2 The Excitation Table: The Characteristic Table Inverted
Suppose a counter stage must go from \(Q = 0\) to \(Q^+ = 1\) on the next clock edge. The characteristic table cannot answer that directly: it is indexed by the inputs, and the inputs are precisely what is unknown. What is needed is a table indexed by the transition, listing the input values that cause it. That table is the excitation table, and it is obtained by sorting the rows of the characteristic table by the pair \((Q, Q^+)\) rather than by the inputs.
Every flip-flop has four possible transitions, so every excitation table has four rows. Figure 22.1 shows the sorting for the JK flip-flop. Its eight characteristic rows fall into four groups of two, and in each group one input takes both values while the transition stays the same — so that input is unconstrained, and is entered as a don't-care.
| \(Q\) | \(Q^+\) | \(S\ R\) | \(J\ K\) | \(D\) | \(T\) | Transition |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 × | 0 × | 0 | 0 | stays reset |
| 0 | 1 | 1 0 | 1 × | 1 | 1 | sets |
| 1 | 0 | 0 1 | × 1 | 0 | 1 | clears |
| 1 | 1 | × 0 | × 0 | 1 | 0 | stays set |
Four features of this table repay attention, because they explain most of what happens later.
- The D column is simply a copy of the \(Q^+\) column. A D flip-flop is told the answer, so there is never any freedom and never a don't-care.
- The T column is \(Q \oplus Q^+\): toggle when the bits differ, hold when they agree. This single line is why T flip-flops make counters so easy — a counter bit toggles exactly when the count says it should change.
- The JK column has four don't-cares out of eight entries. That is the highest proportion of any flip-flop, and it is what makes JK-based counter design produce such small equations in Chapter 24.
- The SR column has two don't-cares, one fewer than JK. The missing freedom is the \(S = R = 1\) row of the characteristic table, which was forbidden and therefore contributed no second option to the set and clear transitions.
The direction of reading matters more than it may appear. A characteristic table is a function: each input combination has exactly one next state. An excitation table is the inverse of that function, and an inverse need not be single-valued. Where two inputs map to one transition, the inverse maps that transition to a set of inputs, and the don't-care is the compact way of writing “any member of the set will do”. Chapter 8 showed that don't-cares make groups larger and expressions smaller; here they arrive for free, as a by-product of running the table backwards.
In a design problem the required sequence of states is known and the inputs are unknown. Only a table indexed by \((Q, Q^+)\) can be looked up. Inverting the characteristic table produces that index, and produces the don't-cares that make the resulting logic cheap.
3 A Five-Step Conversion Procedure
Every conversion in this chapter is the same problem. One flip-flop is physically present — call it the available flip-flop — and its inputs are the signals that must be generated. The behaviour required at the terminals is that of some other flip-flop, the target, whose inputs are the signals available from outside. Between the two sits a block of combinational logic whose inputs are the target's inputs together with the present state \(Q\), fed back from the flip-flop's own output, and whose outputs drive the available flip-flop.
The presence of \(Q\) in that list is the point most often missed. The excitation table is indexed by the present state as well as by the required next state, so the conversion logic is in general a function of \(Q\) and cannot be built from the external inputs alone. Only when the required inputs happen to be independent of \(Q\) does the feedback path disappear, and Section 4 shows the two cases where that happens.
- Draw the conversion table. Its rows are every combination of the target flip-flop's inputs with the present state \(Q\) — four rows for a single-input target, eight for a two-input target.
- Fill in \(Q^+\) from the characteristic equation of the target. This column states what the converted device must do.
- Fill in the required inputs of the available flip-flop by looking up each \((Q, Q^+)\) pair in its excitation table, entering the don't-cares as they stand.
- Minimise each required input on a K-map whose variables are the target inputs and \(Q\), using the don't-cares.
- Draw the circuit and verify algebraically. Substitute the derived expressions into the characteristic equation of the available flip-flop; the result must reduce to the characteristic equation of the target.
Step 5 is not optional politeness. A conversion table can be filled in correctly and a K-map read wrongly, and the resulting circuit will misbehave only in the one state the error touches — which on a breadboard means a counter that works for six counts and then jumps. Substituting the expressions back takes two lines of algebra and settles the matter completely.
4 Converting a JK Flip-Flop to D and to T
The JK flip-flop is the most useful thing to have in the drawer, because it has no forbidden combination and its excitation table is the one richest in don't-cares. Both conversions from it cost either one inverter or nothing at all.
The target is a D flip-flop, so \(Q^+ = D\). Two variables, \(D\) and \(Q\), give four rows.
| \(D\) | \(Q\) | \(Q^+ = D\) | \(J\) | \(K\) |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | × |
| 0 | 1 | 0 | × | 1 |
| 1 | 0 | 1 | 1 | × |
| 1 | 1 | 1 | × | 0 |
On the two-variable map for \(J\) the single 1 lies at \(DQ = \) 10 and the two don't-cares lie at 01 and 11. Taking the don't-care at 11 as 1 makes a pair covering the whole \(D = 1\) column, so \(J = D\). For \(K\) the single 1 is at 01 with don't-cares at 00 and 10; taking the one at 00 gives the whole \(D = 0\) column, so \(K = D'\).
Verification: substitute into \(Q^+ = JQ' + K'Q\), giving \(Q^+ = DQ' + (D')'Q = DQ' + DQ = D(Q' + Q) = D\), which is the D characteristic equation. The circuit is one inverter, drawn in Figure 22.2(a).
The target is a T flip-flop, so \(Q^+ = T \oplus Q\).
| \(T\) | \(Q\) | \(Q^+ = T \oplus Q\) | \(J\) | \(K\) |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | × |
| 0 | 1 | 1 | × | 0 |
| 1 | 0 | 1 | 1 | × |
| 1 | 1 | 0 | × | 1 |
For \(J\) the 1 sits at \(TQ = \) 10 with don't-cares at 01 and 11; the pair down the \(T = 1\) column gives \(J = T\). For \(K\) the 1 sits at 11 with don't-cares at 00 and 10; the same column gives \(K = T\). So the entire conversion is a wire:
Verification: \(Q^+ = TQ' + T'Q = T \oplus Q\), as required. Tying \(J\) and \(K\) together removes the set and reset conditions from the flip-flop's repertoire and leaves only hold and toggle — which is the definition of a T flip-flop. The special case \(T = 1\), obtained by tying \(J\) and \(K\) to logic 1, is the divide-by-two stage that Chapter 23 builds its ripple counter from.
This is why the 74LS76 dual JK package is the one to reach for when a design calls for mixed flip-flop types: a JK is a D for the price of an inverter, a T for nothing, and an SR by simply never applying \(J = K = 1\).
5 Converting a D Flip-Flop to JK and to T
Conversion in the other direction is more expensive, and for a reason that Section 3 predicted. The D flip-flop's excitation table contains no don't-cares, so nothing helps the minimisation, and the D input has to be told the complete answer on every clock edge — including the answer “stay where you are”, which a D flip-flop cannot express except by being fed its own output.
The target is a JK flip-flop, so the conversion table has three variables, \(J\), \(K\) and \(Q\), and eight rows. Because \(D = Q^+\) exactly, the required-input column is a copy of the next-state column.
| \(J\) | \(K\) | \(Q\) | \(Q^+ = JQ' + K'Q\) | \(D\) |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 |
| 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 1 | 1 |
| 1 | 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 0 | 0 |
The 1s of \(D\) are at \(JKQ = \) 001, 100, 101 and 110, with no don't-cares anywhere. On a three-variable map, cells 100 and 110 pair with \(K\) changing to give \(JQ'\), and cells 001 and 101 pair with \(J\) changing to give \(K'Q\). Both are essential prime implicants and together they cover all four 1s:
The result is exactly the JK characteristic equation, which is no accident: since \(D = Q^+\), the conversion logic for a D flip-flop is always a direct implementation of the target's characteristic equation. The circuit needs two AND gates, one OR gate and one inverter, and both \(Q\) and \(Q'\) must be routed back from the flip-flop outputs, as in Figure 22.3.
Verification is immediate: \(Q^+ = D = JQ' + K'Q\).
With \(Q^+ = T \oplus Q\) and \(D = Q^+\), the four-row table gives \(D = 1\) at \(TQ = \) 01 and 10, and \(D = 0\) at 00 and 11, with no don't-cares. Neither pair of 1s is adjacent, so no grouping is possible and the minimal sum keeps both minterms:
One two-input XOR gate, with \(Q\) fed back to it. This is the standard way of building a toggle stage out of the D flip-flops inside an FPGA, and it is worth noting what it costs compared with the JK version: an XOR gate and a feedback track, against a piece of wire. On the other hand it costs nothing that the process does not already provide, which is why every synchronous counter synthesised into a programmable device looks like this.
6 SR to JK, and T to D
Two conversions remain: one the classic examination question, one that completes the set.
This is the conversion that turns the flip-flop with a forbidden state into the flip-flop with none. The target is JK, so \(Q^+ = JQ' + K'Q\); the available device is SR, whose excitation table supplies two don't-cares.
| \(J\) | \(K\) | \(Q\) | \(Q^+\) | \(S\) | \(R\) |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | × |
| 0 | 0 | 1 | 1 | × | 0 |
| 0 | 1 | 0 | 0 | 0 | × |
| 0 | 1 | 1 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 1 | × | 0 |
| 1 | 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 |
For \(S\) the 1s are at \(JKQ = \) 100 and 110, and the don't-cares at 001 and 101. The two 1s form a pair with \(K\) changing, giving \(JQ'\); neither don't-care is adjacent to that pair in a way that would enlarge it without swallowing a 0, so no bigger group exists. For \(R\) the 1s are at 011 and 111 with don't-cares at 000 and 010, and the two 1s pair with \(J\) changing to give \(KQ\).
Two AND gates and the two feedback paths. Verification uses the SR characteristic equation \(Q^+ = S + R'Q\):
which is the JK characteristic equation. The forbidden condition also has to be checked, and it checks out for a structural reason rather than by luck: \(SR = JQ' \cdot KQ = JK(Q'Q) = 0\) for every input, because \(Q\) and \(Q'\) can never both be 1. The feedback that the excitation table forced into the equations is precisely what protects the SR flip-flop from its own forbidden state — and it is also what converts \(J = K = 1\) into an alternating set and reset, which is the toggle.
The target is a D flip-flop, so \(Q^+ = D\), and the available T flip-flop needs \(T = Q \oplus Q^+\). Substituting gives the answer at once, but the table is worth writing to see it:
| \(D\) | \(Q\) | \(Q^+ = D\) | \(T\) | Comment |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | already correct, hold |
| 0 | 1 | 0 | 1 | wrong value, toggle |
| 1 | 0 | 1 | 1 | wrong value, toggle |
| 1 | 1 | 1 | 0 | already correct, hold |
Verification: \(Q^+ = T \oplus Q = (D \oplus Q) \oplus Q = D\), since XOR is associative and \(Q \oplus Q = 0\). The comment column says what the gate is doing: a T flip-flop only knows how to change or not change, so the conversion logic must compare the wanted value with the present one and toggle when they disagree. An XOR gate is a one-bit disagreement detector, which is why the same gate appears here, in the D→T conversion, and in the sum output of the half adder of Chapter 16.
The pattern across all six conversions is now visible. Converting to a flip-flop with many don't-cares is cheap, because the minimisation has room to work; converting from one is cheap only when the available device is at least as expressive as the target. JK is the most expressive of the four, D the least — and everything else follows.
7 Conversions That Need Extra Care
The five-step procedure is mechanical, and a mechanical procedure applied without thought will produce circuits that pass the algebra and fail on the bench. Four conversions deserve a second look.
Anything to JK, and the race-around problem. Chapter 21 showed that a level-triggered master–slave JK with \(J = K = 1\) toggles repeatedly while the clock is high if the pulse lasts longer than the internal propagation delay, so the final state is unpredictable. Every conversion in this chapter has a feedback path from \(Q\) into the input logic, which is exactly the arrangement that race-around exploits. The conversions are valid only for edge-triggered flip-flops, in which \(Q\) is sampled at one instant and the output changes after it. Build the JK→T conversion of Figure 22.2(b) from a transparent latch and it will oscillate.
SR to JK, and the forbidden state. A careless reading of the JK table says “\(J = K = 1\) means toggle, and an SR flip-flop toggles when both inputs are asserted”, which leads to \(S = J\), \(R = K\) and a circuit that enters the forbidden state whenever the toggle is asked for. The correct equations \(S = JQ'\) and \(R = KQ\) avoid it because the \(Q\) and \(Q'\) terms are mutually exclusive, so at most one of \(S\) and \(R\) is ever high. Always test a derived SR drive pair by forming the product \(SR\) and confirming it is identically zero.
D to anything, and setup time. The conversion logic sits in the data path, so its propagation delay is subtracted from the time available between one clock edge and the next. If the flip-flop needs a setup time \(t_{su}\), the flip-flop's own delay is \(t_{pd}\) and the conversion logic contributes \(t_{logic}\), the clock period must satisfy
A converted flip-flop is always slower than a native one. The AND–OR structure of the D→JK conversion is two levels deep, so at 9 ns per level it costs 18 ns of the period, and 27 ns if the inverter that forms \(K'\) must sit in series ahead of the AND gate rather than being supplied ready-made.
Asynchronous inputs are not converted. The preset and clear pins of the available package act directly on the latch and bypass every gate placed in front of it. A converted flip-flop therefore keeps the asynchronous behaviour of the device it is built from, not of the device it imitates, and any reset logic must be designed against the real part. Chapter 23 makes heavy use of that clear pin, and Chapter 24 explains why relying on it is a habit worth losing.
After deriving the input equations, substitute them into the characteristic equation of the available flip-flop and simplify. If the result is not literally the characteristic equation of the target, something is wrong — usually a don't-care read as a 1 in a group that also needed it as a 0. For SR sources, add the second test \(SR = 0\). For conversions with feedback, sketch the two-state cycle by hand: start at \(Q = 0\), apply each input combination, and confirm the state sequence matches the target's table.
8 Summary and Key Results
| Item | Result | Cost or consequence |
|---|---|---|
| SR characteristic equation | \(Q^+ = S + R'Q\), valid only where \(SR = 0\) | The forbidden row becomes a don't-care on the map |
| JK characteristic equation | \(Q^+ = JQ' + K'Q\) | No forbidden state; four don't-cares in its excitation table |
| D and T characteristic equations | \(Q^+ = D\); \(Q^+ = T \oplus Q\) | Fully determined, so no don't-cares and no freedom to exploit |
| Excitation entries | D column \(= Q^+\); T column \(= Q \oplus Q^+\) | T toggles exactly when the required bit changes |
| JK → D and JK → T | \(J = D,\ K = D'\); \(J = K = T\) | One inverter, and nothing at all |
| D → JK and D → T | \(D = JQ' + K'Q\); \(D = T \oplus Q\) | Three gates plus an inverter, and one XOR; both need feedback of \(Q\) |
| SR → JK and T → D | \(S = JQ',\ R = KQ\); \(T = D \oplus Q\) | Two AND gates; one XOR. \(SR = 0\) holds automatically |
| Timing penalty | \(T_{clk} \ge t_{pd} + t_{logic} + t_{su}\) | A converted flip-flop always clocks more slowly than a native one |
9 Common Mistakes
The characteristic table is indexed by the inputs, which in a design problem are the unknowns. Looking up \(J = 0, K = 0\) to find out how to make a flip-flop go from 1 to 0 is answering a question nobody asked. Sort the rows by \((Q, Q^+)\) first; the don't-cares that appear when you do are not sloppiness but genuine freedom, and discarding them by entering 0s instead produces logic that works and costs more gates than it should.
It looks reasonable — set is set, reset is reset — and it fails the moment \(J = K = 1\) is applied, because that drives the SR flip-flop into its forbidden condition instead of toggling it. The excitation table produces \(S = JQ'\) and \(R = KQ\), in which the feedback terms make \(S\) and \(R\) mutually exclusive. Check any SR drive pair by forming \(SR\) and confirming it is identically zero.
Only JK→D and JK→T come out independent of the present state; every other conversion in this chapter needs \(Q\), \(Q'\) or both routed back from the flip-flop output into the input gates. Omitting the feedback gives a circuit whose next state ignores the current one — which is a combinational circuit with a register on the end, not the flip-flop that was asked for. The feedback also means the conversion is only safe with an edge-triggered device.
10 Chapter Review
1. Derive the excitation table of the JK flip-flop from its characteristic table, and explain where each don't-care comes from.
Sort the eight characteristic rows by the pair \((Q, Q^+)\). The rows \(JKQ = \)
000and010both give \(Q^+ = 0\) from \(Q = 0\), and they differ only in \(K\), so the 0→0 transition needs \(J = 0\) with \(K\) free. Rows100and110both give \(Q^+ = 1\) from \(Q = 0\) and differ only in \(K\), so 0→1 needs \(J = 1\), \(K\) free. Rows011and111give \(Q^+ = 0\) from \(Q = 1\) and differ only in \(J\), so 1→0 needs \(K = 1\), \(J\) free. Rows001and101give \(Q^+ = 1\) from \(Q = 1\) and differ only in \(J\), so 1→1 needs \(K = 0\), \(J\) free. Every don't-care is a pair of characteristic rows that produce the same transition; the input that differs between them has no influence and is therefore unconstrained.2. Convert a JK flip-flop into a D flip-flop and verify the result algebraically. Why is the same conversion in the opposite direction so much more expensive?
The conversion table has four rows in \(D\) and \(Q\); the required inputs are \(J = 0, K = \times\); \(J = \times, K = 1\); \(J = 1, K = \times\); \(J = \times, K = 0\) for \(DQ = \)
00,01,10,11. Using the don't-cares, \(J = D\) and \(K = D'\). Substituting into \(Q^+ = JQ' + K'Q\) gives \(DQ' + DQ = D\). The reverse conversion, D to JK, is dearer for two reasons: the D excitation table contains no don't-cares at all, so the K-map has nothing to exploit, and the target JK behaviour includes a hold condition that a D flip-flop can only achieve by being fed its own output. The result, \(D = JQ' + K'Q\), needs two AND gates, an OR gate, an inverter and two feedback paths against the single inverter of the JK→D conversion.3. A student wires an SR flip-flop with \(S = J\) and \(R = K\) and reports that it works for three of the four input combinations. Explain, and give the correct equations.
Three of the four combinations do work: \(JK = \) 00 gives \(SR = \) 00, which holds; 01 gives 01, which resets; 10 gives 10, which sets. The fourth, \(J = K = 1\), gives \(S = R = 1\), the SR flip-flop's forbidden condition, in which both gate outputs go to the same level and the state reached when the inputs are removed depends on which gate is faster. A JK flip-flop is required to toggle there. The excitation-table derivation gives \(S = JQ'\) and \(R = KQ\); with \(J = K = 1\) these become \(S = Q'\) and \(R = Q\), so exactly one of them is asserted and the flip-flop is driven to the opposite state — a toggle. The product \(SR = JQ' \cdot KQ = 0\) identically, so the forbidden state can never be reached.
4. Convert a T flip-flop into a JK flip-flop. Derive the equation, verify it, and comment on the gate count.
The conversion table has variables \(J\), \(K\), \(Q\), and \(Q^+ = JQ' + K'Q\). The T excitation entry is \(T = Q \oplus Q^+\), so \(T = 1\) exactly where present and next state differ: at \(JKQ = \)
011,100,110and111. Grouping110with100gives \(JQ'\), and011with111gives \(KQ\), so \(T = JQ' + KQ\), two AND gates and an OR gate. Verification: \(Q^+ = T \oplus Q\). For \(Q = 0\), \(T = J\) and \(Q^+ = J\), which matches \(JQ' + K'Q = J\); for \(Q = 1\), \(T = K\) and \(Q^+ = K'\), which matches \(JQ' + K'Q = K'\). Three gates plus feedback — more than the SR→JK conversion needs, because the T flip-flop cannot set or reset directly and must be told, in every state, whether the required value differs from the present one.5. A synchronous circuit runs from a 25 MHz clock. Its flip-flops have \(t_{pd} = 12\) ns and \(t_{su} = 5\) ns, and each gate level costs 9 ns. Can a JK flip-flop converted from a D flip-flop be used in it?
A 25 MHz clock has a period of 40 ns. The conversion logic \(D = JQ' + K'Q\) is an AND level followed by an OR level, so if the complement \(K'\) is already available then \(t_{logic} = 2 \times 9 = 18\) ns and the requirement \(T_{clk} \ge t_{pd} + t_{logic} + t_{su} = 12 + 18 + 5 = 35\) ns fits inside 40 ns with 5 ns of margin. If \(K'\) has to be produced by an inverter in series with the AND gate, the path is three levels, \(t_{logic} = 27\) ns, and \(T_{clk} \ge 44\) ns — which does not fit, so the circuit would fail intermittently. Either way a native JK flip-flop needs only \(12 + 5 = 17\) ns and would run to 58.8 MHz, so the conversion costs at least half the available speed.