By the end of this chapter you should be able to:
- Explain why a T flip-flop with \(T = 1\) is a divide-by-two circuit, and why a chain of \(n\) of them counts in binary.
- Draw a ripple up counter and its timing diagram, and mark on that diagram the cumulative delay between the clock edge and the last output edge.
- Convert a ripple up counter into a down counter, and state the two ways of doing it.
- Design a modulus-\(N\) counter by decoding the state \(N\) with a NAND gate driving the asynchronous clear, and work out the width of the partial state that results.
- Identify the transient states a ripple counter passes through during a multiple-bit transition, and predict which decoder outputs will glitch.
- Calculate the maximum operating frequency of an \(n\)-stage ripple counter from the flip-flop propagation delay, and say when a ripple counter is and is not an acceptable choice.
A counter is a register whose contents advance by one every time a clock pulse arrives, and it is the most common sequential circuit in any digital system: it measures time, divides frequency, addresses memory in sequence, and keeps track of how many of anything have happened. Chapter 22 produced the component this chapter needs — a T flip-flop, obtained from whatever device is in the drawer by tying \(J\) and \(K\) together, or by an XOR round a D flip-flop.
There are two ways to make a chain of such stages count. In the first, the system clock reaches only the least significant stage and every other stage is clocked by its neighbour, so a change spreads along the chain like a row of falling dominoes. That is the asynchronous or ripple counter, and it needs no design procedure at all — you wire it and it counts. This chapter builds it, works out what its outputs actually do during the microseconds between counts, and shows that the ripple has consequences serious enough to force the alternative of Chapter 24, in which every flip-flop is clocked at the same instant.
1 The T Flip-Flop as a Divide-by-Two Stage
Set \(T = 1\) on a T flip-flop and its characteristic equation \(Q^+ = T \oplus Q\) becomes \(Q^+ = Q'\): the output inverts on every active clock edge and does nothing in between. Two clock edges are therefore needed to return \(Q\) to where it started, so one complete cycle of \(Q\) spans two complete cycles of the clock.
A toggle stage is a divide-by-two circuit. It also produces a square wave with an exact 50 % duty cycle whatever the duty cycle of the clock, because the output changes only on one edge and therefore spends exactly one clock period high and one low.
Chapter 22 gave three ways to obtain the stage. A JK flip-flop with \(J = K = 1\) is the cheapest — two pins tied to \(V_{CC}\), no gates. A D flip-flop needs its own \(Q'\) returned to its \(D\) input, since \(D = T \oplus Q\) with \(T = 1\) reduces to \(D = Q'\). A dedicated T flip-flop simply has its input tied high. All three behave identically, and the rest of this chapter draws them as JK stages with both inputs at 1.
Now cascade them. Suppose stage 0 is clocked by the system clock and stage 1 is clocked by \(Q_0\). Stage 0 divides by two, so \(Q_0\) has frequency \(f/2\); stage 1 divides that again, so \(Q_1\) has frequency \(f/4\). In general the \(i\)-th stage of the chain produces \(f/2^{i+1}\), and \(n\) stages have \(2^n\) distinct output patterns before repeating.
That the patterns are the binary numbers in order is not a coincidence but a restatement of what binary counting is. In the sequence 0, 1, 2, 3, … the least significant bit changes on every step; the next bit changes on every step where the bit below it goes from 1 to 0, that is, whenever the bit below it falls; the next changes when the one below it falls; and so on. “Toggle when the stage below you falls” is exactly the wiring rule of Figure 23.1, and it is the whole design. A ripple counter is the one sequential circuit in this course that needs no state table, no excitation table and no K-map — which is precisely why it is worth understanding what you lose by taking that shortcut.
2 The Ripple Up Counter and Its Timing Diagram
Figure 23.1 shows the four-stage version. The external clock is connected to the first flip-flop only. Every other clock input is driven by the \(Q\) output of the stage to its left, and every flip-flop is negative-edge-triggered, indicated by the bubble on the clock input.
The choice of edge and the choice of output are linked, and getting the combination wrong gives a counter that counts the wrong way. With negative-edge triggering, stage \(i+1\) toggles when \(Q_i\) falls, which is exactly the up-counting rule derived above. Take the same chain, keep the negative-edge flip-flops, but drive each clock from \(Q'\) instead of \(Q\), and stage \(i+1\) now toggles when \(Q_i\) rises — which is the down-counting rule of the next section.
Figure 23.2 draws one complete cycle with the flip-flop delay exaggerated so that it is visible. Two things should be read off it. The first is the frequency division: \(Q_0\) has half the clock frequency, \(Q_1\) a quarter, \(Q_2\) an eighth, \(Q_3\) a sixteenth, and taken together as the word \(Q_3Q_2Q_1Q_0\) they run through 0000 to 1111 and back to 0000.
The second is the staircase of edges. An output edge cannot occur until the edge that caused it has occurred, so each stage's transition is displaced one flip-flop propagation delay \(t_{pd}\) further to the right than the one before it. Where only \(Q_0\) changes — the even-to-odd counts — the word is correct after \(t_{pd}\). Where the carry runs the whole length of the chain, as at 7 → 8 and 15 → 0, the last edge does not arrive until \(4t_{pd}\). For a 74LS-series flip-flop with \(t_{pd} = 12\) ns that is 48 ns of uncertainty after every eighth clock edge.
The stages do not change together. Stage \(i\) changes at \((i+1)t_{pd}\) after the clock edge, if it changes at all, so a full carry through an \(n\)-stage counter takes \(n\,t_{pd}\). Everything else in this chapter — the glitches, the frequency limit, the unsuitability for decoding — follows from that single sentence.
3 Counting Down
Counting down means running the sequence 15, 14, 13, … and the bit rule changes accordingly. In a descending binary sequence, bit \(i+1\) changes whenever bit \(i\) goes from 0 to 1: going from 0100 to 0011, the least significant bit rises from 0 to 1 and drags a change out of every bit above it. So a down counter is a chain in which each stage toggles when the stage below it rises rather than falls.
Two wirings produce that, and both appear in practice.
- Keep negative-edge flip-flops and clock each stage from \(Q'\). When \(Q_i\) rises, \(Q'_i\) falls, and a falling edge is what the next stage responds to. The counter's outputs are still taken from the \(Q\) pins, so the reading is a proper binary count — only the clock routing has changed.
- Keep the \(Q\) connections and use positive-edge flip-flops. Then stage \(i+1\) responds to the rising edge of \(Q_i\) directly. This is what a 74LS93 does not do and a 74LS169 does; with 74-series parts the first method is usually the practical one, since the \(Q'\) pins are already brought out.
A common third suggestion — leave the counter alone and read the \(Q'\) outputs — counts down but does not count from where you expect. If the \(Q\) outputs read 3 (0011) then the \(Q'\) outputs read 12 (1100), so the complemented outputs run 15, 14, 13, … while the true outputs run 0, 1, 2, … That is a genuine down count, and it is free, but the two counts are related by \(Q' = 15 - Q\) rather than by a reset to a common starting point. It is fine for frequency division and misleading for anything that has to start at a known value.
An up–down ripple counter can be built by putting a two-to-one multiplexer between each stage, selecting \(Q_i\) or \(Q'_i\) as the clock for stage \(i+1\) according to a direction input. It works, but the multiplexer's own delay is added to every stage, and switching direction can produce a clock edge on a stage that was not expecting one and so an extra count. Chapter 24 does the same job with mode-controlled gating on the \(J\) and \(K\) inputs, where the clock is never touched and the hazard does not arise.
4 Modulus-N Counters by Decoding and Clearing
An \(n\)-stage ripple counter naturally has a modulus of \(2^n\). Most applications need something else: a decade counter for a digital display, a divide-by-60 for a clock, a divide-by-12 for a duty cycle. The standard asynchronous answer is to let the counter start counting past the modulus and then throw it back to zero the instant it does, using the flip-flops' asynchronous clear inputs, which act on the latches directly and do not wait for a clock edge.
The procedure is short:
- Choose \(n\) so that \(2^n \ge N\). A modulus of 10 needs four stages, since \(2^3 = 8 < 10 \le 16 = 2^4\).
- Write \(N\) itself in binary. This is the first state the counter must not be allowed to keep — the counter is to display 0 to \(N-1\), so \(N\) is the intruder.
- Feed the outputs that are 1 in that pattern into a NAND gate. Its output is low only in that state.
- Connect the NAND output to the active-low clear pin of every flip-flop.
Ten states need four flip-flops. The intruder is \(N = 10 = \) 1010, in which \(Q_3\) and \(Q_1\) are 1 and \(Q_2\) and \(Q_0\) are 0. The gate is therefore
Only two inputs are needed, not four, and the reason is worth stating because it is a common source of doubt. The gate must be low in state 1010 and high in states 0000 to 1001, and it does not matter what it does in 1011 to 1111 because an up counter starting from zero reaches 1010 before any of them. Checking the ten legal states: \(Q_3 = 1\) only in 1000 and 1001, and in neither of those is \(Q_1 = 1\). So \(Q_3 \cdot Q_1\) is 0 throughout the wanted count and 1 in state 1010, which is all that is required.
The count sequence becomes 0000, 0001, … 1001, and then, on the tenth clock edge, the counter begins to move to 1010 — and gets there. \(Q_0\) falls 12 ns after the clock edge; that fall clocks stage 1, so \(Q_1\) rises at 24 ns; the counter is now genuinely in state 1010. The NAND gate, with a propagation delay of about 10 ns, pulls the clear line low at 34 ns, and the flip-flops respond after their clear-to-output delay of about 12 ns, so the counter reaches 0000 at 46 ns. State 1010 therefore exists on the pins for
and \(Q_1\) carries a 22 ns spike that a seven-segment decoder connected to the outputs will attempt to display.
This is the well-known weakness of reset-based modulus control: the counter passes through the state it is supposed to skip. For a display driven from a decoder the spike is far too short to see, and the 7490 and its successors were used in millions of instruments on exactly that basis. For anything that samples the counter outputs — a microprocessor read, an edge-triggered load, another counter cascaded behind this one — the spike is a real state and can be captured.
The width of the reset pulse causes the second problem. The clear line goes low, the flip-flops clear, and the moment \(Q_1\) goes to 0 the NAND output returns high and removes the clear. The reset pulse is therefore self-terminating and only as long as the clear-to-output delay, which for slower parts in the chain may not be long enough to clear all of them reliably. The standard fix is to latch the reset: use the NAND output to set an SR latch whose output holds the clear line low until the next clock edge arrives. Counters such as the 7490 sidestep the issue by dividing the chain into a divide-by-two and a divide-by-five section that are internally arranged never to produce the intermediate state at all.
5 Decoding Glitches
Section 2 established that the stages change one after another. The consequence for anything connected to the outputs is more serious than a delay, because the intermediate patterns are themselves valid counts.
Follow the transition from 7 to 8 in a four-stage counter, drawn to scale in Figure 23.3. The clock falls at \(t = 0\). At 12 ns \(Q_0\) falls, and the word is 0110 — count 6. That fall clocks stage 1, so at 24 ns \(Q_1\) falls and the word is 0100 — count 4. That fall clocks stage 2, so at 36 ns \(Q_2\) falls and the word is 0000 — count 0. Only at 48 ns does \(Q_3\) rise and the word become the intended 1000.
A decoder gate watching for count 6 sees its condition satisfied for 12 ns; so does a gate watching for 4; so does a gate watching for 0. None of those counts occurred. They are decoding glitches, and they are produced by the counter itself, not by noise, not by a hazard in the decoder, and not by anything a redundant prime implicant of Chapter 11 can remove. Enumerating every transition of the four-stage counter gives the complete list:
| Transition | Intermediate patterns, in order | Decoder outputs that glitch |
|---|---|---|
| 1 → 2 | 0000 | 0 |
| 3 → 4 | 0010, 0000 | 2, 0 |
| 5 → 6 | 0100 | 4 |
| 7 → 8 | 0110, 0100, 0000 | 6, 4, 0 |
| 9 → 10 | 1000 | 8 |
| 11 → 12 | 1010, 1000 | 10, 8 |
| 13 → 14 | 1100 | 12 |
| 15 → 0 | 1110, 1100, 1000 | 14, 12, 8 |
Every even count is falsely decoded at some point in the cycle, and count 0 is falsely decoded three times per cycle in addition to the once it is genuinely reached. The pattern is easy to remember: during a carry the counter descends through the numbers obtained by clearing the low bits of the old count one at a time, so the intermediate patterns are always numerically smaller than both the count being left and the count being reached.
The glitch is one \(t_{pd}\) wide regardless of the clock frequency, so its relative size shrinks as the clock slows: at 1 MHz a 12 ns spike is 1.2 % of the period, at 10 MHz it is 12 %. That is why a ripple counter driving a display works and a ripple counter driving a state machine does not. If the decoded output goes anywhere that responds to a short pulse — a clock input, a latch enable, a memory write strobe, an interrupt line — the circuit will fail intermittently in a way that is very hard to find on a bench, because the fault is 12 ns wide and appears once every eight clocks.
Two partial remedies exist. Strobing the decoder gates with a signal that is asserted only after the counter has settled suppresses the glitch at the cost of an extra input on every gate and a strobe generator. Gray-coded counting, in which only one bit changes per count, removes the problem at source but no longer produces a binary output. Neither is as satisfactory as clocking every stage together, which is what Chapter 24 does.
6 Maximum Operating Frequency, and Where Ripple Counters Belong
Two separate limits bound the clock frequency of a ripple counter, and which of them bites depends on what the outputs are used for.
The first is the toggle rate of the first flip-flop. Stage 0 sees the full clock and must complete a transition before the next edge, so \(f_{clk} \le f_{tog}\), where \(f_{tog}\) is the maximum toggle frequency quoted in the data sheet — about 30 MHz for a 74LS73. Stages further down the chain see progressively lower frequencies and never limit anything.
The second, and usually the binding one, is the requirement that the whole word be valid before the next clock edge disturbs it. The last stage settles \(n\,t_{pd}\) after the edge, so
The limit falls off as \(1/n\): every stage added to a ripple counter makes it slower, which is the opposite of what happens in the synchronous counter of Chapter 24.
Flip-flops with \(t_{pd} = 12\) ns are used to build ripple counters whose outputs are decoded. Find the maximum clock frequency for four, six and eight stages.
| Stages \(n\) | Modulus | Settling time \(n\,t_{pd}\) | \(f_{max} = 1/(n\,t_{pd})\) |
|---|---|---|---|
| 3 | 8 | 36 ns | 27.78 MHz |
| 4 | 16 | 48 ns | 20.83 MHz |
| 6 | 64 | 72 ns | 13.89 MHz |
| 8 | 256 | 96 ns | 10.42 MHz |
For the four-stage counter, \(4 \times 12 = 48\) ns and \(f_{max} = 1/48\text{ ns} = 20.83\) MHz, which is below the 30 MHz toggle limit, so the ripple is the binding constraint. It is the binding constraint for every counter in the table, and the eight-stage counter has lost two-thirds of the speed of the three-stage one purely by being longer.
If the outputs are not decoded — the counter is used only as a frequency divider, and nothing looks at the intermediate bits — the settling requirement disappears and only the toggle rate matters. The same four-stage chain would then run to 30 MHz. It is worth being explicit about which of the two situations a design is in, because the answer differs by a factor of nearly two.
Where does that leave the ripple counter? It has real advantages: the fewest possible components for a given modulus, no steering logic at all, and the lowest power, since most of the chain switches rarely. As a frequency divider — a 32.768 kHz crystal reduced to 1 Hz by fifteen cascaded stages, the classic wristwatch divider — nothing beats it, because only the final output is used and nobody cares what the intermediate bits do.
It is the wrong choice as soon as the count value itself matters at a defined instant. Decoded outputs glitch; a modulus set by asynchronous clear passes through the forbidden state; the maximum frequency degrades with every stage; and the outputs cannot be sampled by another clocked circuit without a settling delay that has to be budgeted by hand. Chapter 24 removes all four problems at once by connecting the system clock to every flip-flop and using combinational logic on the \(J\) and \(K\) inputs to decide which stages toggle — at the cost of that logic, and of a design procedure that needs the excitation tables of Chapter 22.
7 Summary and Key Results
| Item | Result | Consequence |
|---|---|---|
| Toggle stage | \(T = 1\) gives \(Q^+ = Q'\), so \(f_Q = f_{clk}/2\) | \(n\) stages give \(f/2, f/4, \ldots, f/2^n\) and a modulus of \(2^n\) |
| Up counter wiring | Negative-edge stages, each clocked from the previous \(Q\) | Stage \(i+1\) toggles when \(Q_i\) falls, which is the binary carry rule |
| Down counter wiring | Same chain, each clocked from the previous \(Q'\) | Stage \(i+1\) toggles when \(Q_i\) rises |
| Settling time | Stage \(i\) changes at \((i+1)t_{pd}\); full carry takes \(n\,t_{pd}\) | 48 ns for four stages at \(t_{pd} = 12\) ns |
| Modulus \(N\) | NAND the outputs that are 1 in the binary word \(N\), drive \(\overline{CLR}\) | Mod-10 needs \((Q_3Q_1)'\); state 1010 exists for \(t_{NAND} + t_{CLR} = 22\) ns |
| Decoding glitches | Intermediate patterns during a carry are valid counts | Every even count is falsely decoded once per cycle; count 0 three times |
| Maximum frequency | \(f_{max} = 1/(n\,t_{pd})\) if the outputs are decoded | 20.83 MHz for four stages, 10.42 MHz for eight, at \(t_{pd} = 12\) ns |
| Proper use | Frequency division, where only the last output is read | Not for decoded outputs, sampled outputs or cascading into clocked logic |
8 Common Mistakes
The timing diagram of Figure 23.2 is usually drawn with vertical edges, and the vertical edges are a lie of convenience. Stage \(i\) cannot change until stage \(i-1\) has, so a four-bit carry takes four flip-flop delays. Any calculation that treats a ripple counter's output word as valid immediately after the clock edge — a maximum-frequency estimate, a setup-time budget for the next stage, a decoder timing check — will be optimistic by a factor of \(n\).
A pulse on a decoder output that should never have gone high looks exactly like the static hazard of Chapter 11, and students duly go looking for a redundant prime implicant to add. There is nothing wrong with the decoder. Its inputs really did take the value it responded to, for one flip-flop delay, because the counter passed through that state. No amount of work on the decoder's algebra will help; either strobe it after the counter has settled, or use a synchronous counter.
For a mod-10 counter the gate is \((Q_3Q_1)'\), not \((Q_3Q_2'Q_1Q_0')'\): the counter arrives at 1010 from below, so no earlier state can satisfy \(Q_3Q_1\), and the extra inputs cost a wider gate for nothing. The opposite error is worse — decoding \(Q_3\) alone would reset the counter at 1000 and give a modulus of 8. Always list the states from 0 to \(N-1\) and check that the chosen product is 0 in every one of them.
9 Chapter Review
1. A four-stage ripple up counter is built from flip-flops with \(t_{pd} = 12\) ns. Draw the sequence of output words during the transition from count 11 to count 12 and give the time of each change.
Count 11 is
1011and count 12 is1100, so the two low bits fall and \(Q_2\) rises. At \(t = 12\) ns \(Q_0\) falls and the word is1010, which decodes as 10. That fall clocks stage 1, so at \(t = 24\) ns \(Q_1\) falls and the word is1000, which decodes as 8. That fall clocks stage 2, so at \(t = 36\) ns \(Q_2\) rises and the word becomes the intended1100. \(Q_3\) does not change, because \(Q_2\) rose rather than fell, so the ripple stops there and the settling time for this particular transition is 36 ns rather than the worst-case 48 ns. Decoder outputs for counts 10 and 8 each carry a 12 ns glitch.2. Design a mod-6 ripple counter and state the sequence it produces, including any state it passes through briefly.
Six states need three flip-flops, since \(2^2 = 4 < 6 \le 8\). The intruder is \(N = 6 = \)
110, in which \(Q_2\) and \(Q_1\) are 1, so the reset gate is \(\overline{CLR} = (Q_2 \cdot Q_1)'\) driving the clear pin of all three flip-flops. Checking the wanted states 000 to 101: \(Q_2Q_1 = 1\) in none of them, since \(Q_2 = 1\) only in 100 and 101 where \(Q_1 = 0\). The sequence is 000, 001, 010, 011, 100, 101 and then back to 000. It does pass through 110: on the sixth clock edge \(Q_0\) falls, \(Q_1\) rises 12 ns later and the counter is momentarily in 110, which lasts \(t_{NAND} + t_{CLR} \approx 22\) ns before the clear takes effect. The counter is therefore a divide-by-six, but \(Q_2\) is not a symmetrical square wave and the outputs must not be sampled asynchronously.3. Why does a ripple counter's maximum frequency fall as stages are added, when the extra stages run more and more slowly?
The extra stages do run more slowly — stage \(i\) toggles at \(f/2^{i+1}\) — so they are never in danger of being clocked too fast themselves. The limit is not about the stages keeping up; it is about the output word being complete. A carry that propagates the whole length of the chain takes \(n\,t_{pd}\), and until it has finished, the outputs spell a number that is not the count. If the count has to be valid before the next clock edge, then \(T_{clk} \ge n\,t_{pd}\) and \(f_{max} = 1/(n\,t_{pd})\), which falls as \(1/n\). If the outputs are never read — pure frequency division — the requirement disappears and the only limit is the toggle rate of the first flip-flop, which does not depend on \(n\) at all.
4. A three-bit ripple counter drives a 3-to-8 decoder whose outputs are used as timing strobes. List every false strobe produced in one cycle and give its width, taking \(t_{pd} = 12\) ns.
The transitions with more than one bit changing are 1 → 2, 3 → 4, 5 → 6 and 7 → 0. At 1 → 2 the word passes through
000, falsely striking output 0. At 3 → 4 it passes through010then000, striking outputs 2 and 0. At 5 → 6 it passes through100, striking output 4. At 7 → 0 it passes through110then100, striking outputs 6 and 4. That is six false strobes per cycle of eight counts, each one flip-flop delay wide, so 12 ns, plus the decoder's own delay which shifts them but does not shorten them. Output 0 is struck twice falsely in addition to its one genuine assertion. Using these outputs as strobes is therefore unusable as it stands: either gate every decoder output with a strobe that is asserted only after \(3t_{pd} = 36\) ns has elapsed, or replace the counter with the synchronous version of Chapter 24.5. A 32.768 kHz crystal oscillator must be reduced to a 1 Hz tick. How many ripple stages are needed, and is the ripple delay a problem?
Each stage divides by two, so \(n\) stages divide by \(2^n\). Since \(32768 = 2^{15}\), fifteen stages give \(32768/32768 = 1\) Hz exactly, which is why that crystal frequency was chosen. The ripple delay is not a problem here, for two separate reasons. First, only the fifteenth output is used; nobody decodes the intermediate bits, so the transient patterns during a carry are invisible. Second, the worst-case settling time is \(15 \times 12 = 180\) ns against a clock period of \(1/32768\) s = 30.5 µs, so the ripple occupies about 0.6 % of one period and the frequency limit \(f_{max} = 1/180\text{ ns} = 5.6\) MHz is some 170 times higher than the clock. This is the application the ripple counter is genuinely best at: maximum division for minimum hardware and minimum power.