By the end of this chapter you should be able to:
- Explain why distributing the clock to every stage makes the output word valid one flip-flop delay after the clock edge, whatever the number of stages.
- Carry out the four-step synchronous design procedure: state table, excitation table, K-map per flip-flop input, circuit.
- Design a synchronous mod-8 up counter with JK flip-flops and justify the resulting \(J = K = \) carry rule.
- Design a counter for an arbitrary non-binary sequence, treating the unused states as don't-cares.
- Add mode control to obtain an up–down counter, and explain why gating the \(J\) and \(K\) inputs is safer than switching the clock.
- Test a completed design for self-starting behaviour by computing the next state of every unused state, and repair a design that locks out.
- Compare the maximum frequency of a synchronous counter with that of the ripple counter of Chapter 23, for both parallel-carry and serial-carry structures.
Chapter 23 built a counter out of nothing but toggle stages and a chain of clock connections, and then spent most of its length explaining what that chain costs: outputs that arrive one after another rather than together, decoder outputs that pulse on counts the circuit never reached, a modulus set by racing the flip-flops back to zero, and a maximum frequency that falls as \(1/n\). All four faults have one cause, and it is the same cause: only the first flip-flop is clocked by the clock.
The remedy is to connect the system clock to every flip-flop in the counter and use combinational logic on the \(J\) and \(K\) inputs to decide which stages should change at the coming edge. Nothing then propagates: the decision is computed during the clock period and acted on simultaneously. The price is that decision logic, and a design procedure to produce it — which is where the excitation tables of Chapter 22 earn their place. The same procedure will produce any counting sequence you care to specify, in binary order or not, and it generalises without change into the state-machine design of Chapter 26.
1 Clocking Every Stage Together
Take the four-stage counter through the transition from 7 to 8 once more. In the ripple version of Chapter 23, \(Q_0\) fell at 12 ns, its fall clocked stage 1 so that \(Q_1\) fell at 24 ns, and so on down the chain until \(Q_3\) rose at 48 ns. Now connect all four clock inputs to the same wire. Every flip-flop is triggered at \(t = 0\); every flip-flop that has been told to change does so after one propagation delay; and at \(t = 12\) ns the word is 1000.
Three consequences follow immediately, and they are worth stating before any design work begins.
- The settling time is one flip-flop delay, independent of \(n\). Adding stages does not slow a synchronous counter down. It may add a level of gating, which is a smaller cost and one that can be designed away.
- There are no transient states, so decoded outputs do not glitch. All the outputs move at once, so the word never takes a value that is not a count. The false strobes tabulated in Chapter 23 simply do not occur, and the decoder outputs are usable as strobes.
- The modulus does not need an asynchronous clear. The sequence is whatever the input logic says it is, so a mod-10 counter goes from 1001 to 0000 because it was designed to, not because it was thrown back after briefly reaching 1010.
The flip-flops must now be told individually whether to change, since they no longer find out by being clocked. For a binary up count the rule is the one every carry rule in this course is built on: bit \(i\) changes exactly when every bit below it is 1. A stage that must change toggles, and a JK flip-flop toggles when \(J = K = 1\), so
A single AND gate per stage. The next section derives the same result formally, because for any sequence other than a plain binary count there is no rule to guess at and the procedure is all there is.
2 The Synchronous Design Procedure
The procedure below produces the input equations for any counter, of any modulus, following any sequence of states, using any flip-flop type. It is the counter case of the state-machine synthesis of Chapter 26, and is worth learning in this simpler setting first.
- Fix the number of flip-flops. A counter with \(M\) states needs \(n\) flip-flops where \(2^n \ge M\). If \(2^n > M\) there are unused states, and Section 6 explains what to do about them.
- Write the state table. One row per present state, giving the next state. For a counter the state is the count itself, so no state assignment is needed — the assignment is handed to you by the specification.
- Extend it to an excitation table. For each flip-flop, look up the pair \((Q_i, Q_i^+)\) in the excitation table of Chapter 22 and write down the required inputs, don't-cares included. A design with \(n\) JK flip-flops produces \(2n\) columns.
- Minimise each column on its own K-map. The map variables are the present-state bits \(Q_{n-1} \ldots Q_0\), together with any mode inputs. Rows for unused states are entered as don't-cares in every column.
- Draw the circuit, then check it. Substitute the derived equations back and compute the next state of every one of the \(2^n\) states, not just the wanted ones.
Step 5 is where most of the marks are lost and most of the laboratory time is spent. The wanted states will be right if the algebra was right; the unused states are governed by whatever the don't-cares happened to become during minimisation, and nobody chose that. Section 6 is entirely about the consequences.
Which flip-flop to use is a genuine choice. JK gives the most don't-cares and therefore usually the smallest logic, and it is the standard choice for hand design. T flip-flops are natural for counters because the T column of the excitation table is \(Q \oplus Q^+\) — toggle when the bit must change — and for a binary up counter the T equations are identical to the JK ones. D flip-flops give no don't-cares at all and larger equations, but they are what a programmable device actually contains, so every synthesised counter ends up in D form whatever it was designed in.
3 A Synchronous Mod-8 Up Counter
Eight states need three flip-flops, and every one of the eight patterns is used, so there are no don't-cares from unused states. The state table is the binary count, and the excitation entries come from the JK row of the Chapter 22 table: 0→0 needs \(J = 0, K = \times\); 0→1 needs \(J = 1, K = \times\); 1→0 needs \(J = \times, K = 1\); 1→1 needs \(J = \times, K = 0\).
| \(Q_2Q_1Q_0\) | \(Q_2^+Q_1^+Q_0^+\) | \(J_2\ K_2\) | \(J_1\ K_1\) | \(J_0\ K_0\) |
|---|---|---|---|---|
| 0 0 0 | 0 0 1 | 0 × | 0 × | 1 × |
| 0 0 1 | 0 1 0 | 0 × | 1 × | × 1 |
| 0 1 0 | 0 1 1 | 0 × | × 0 | 1 × |
| 0 1 1 | 1 0 0 | 1 × | × 1 | × 1 |
| 1 0 0 | 1 0 1 | × 0 | 0 × | 1 × |
| 1 0 1 | 1 1 0 | × 0 | 1 × | × 1 |
| 1 1 0 | 1 1 1 | × 0 | × 0 | 1 × |
| 1 1 1 | 0 0 0 | × 1 | × 1 | × 1 |
Six maps follow, each in the three variables \(Q_2, Q_1, Q_0\). Taking them in turn:
- \(J_0\) has 1s in the four rows with \(Q_0 = 0\) and don't-cares in the other four, so the whole map can be grouped: \(J_0 = 1\). The same argument gives \(K_0 = 1\).
- \(J_1\) has a single 1 at
001and a second at101, with don't-cares wherever \(Q_1 = 1\). The pair 001 and 101 groups with the don't-cares at 011 and 111 into the four cells with \(Q_0 = 1\), giving \(J_1 = Q_0\), and identically \(K_1 = Q_0\). - \(J_2\) has a single 1 at
011and don't-cares at every state with \(Q_2 = 1\). Grouping it with the don't-cares at111gives the pair \(Q_1Q_0\), and no larger legal group exists because001and010are genuine 0s. So \(J_2 = Q_1Q_0\), and \(K_2 = Q_1Q_0\) by the same reasoning on its own map.
Verify by running the equations round the cycle. From 011: \(J_0 = K_0 = 1\) toggles \(Q_0\) to 0; \(J_1 = K_1 = Q_0 = 1\) toggles \(Q_1\) to 0; \(J_2 = K_2 = Q_1Q_0 = 1\) toggles \(Q_2\) to 1, giving 100 = 4 as required. Every stage read the old values of the lower bits, because all are sampled at the same edge — the property an edge-triggered flip-flop provides and a transparent latch does not.
The whole counter is three flip-flops and one two-input AND gate, drawn in Figure 24.1. A four-bit version adds \(J_3 = K_3 = Q_2Q_1Q_0\), one three-input AND.
Stage \(i\) of a synchronous binary up counter toggles when, and only when, every stage below it holds a 1. Reversing the sense — \(J_i = K_i = Q'_{i-1}\cdots Q'_0\) — gives a down counter, because in a descending count a bit changes when every bit below it is 0.
4 A Counter with a Non-Binary Sequence
The procedure does not care whether the sequence is a binary count. Any list of states in any order can be specified, and the K-maps will produce the logic that walks through them.
Design a synchronous counter with JK flip-flops that repeats the sequence
Six states, so three flip-flops, and two patterns — 010 and 101 — are never used. Note that exactly one bit changes at each step; this is the Johnson or twisted-ring sequence that Chapter 25 obtains from a shift register, and it is being produced here by a counter designed from first principles.
| \(Q_2Q_1Q_0\) | \(Q_2^+Q_1^+Q_0^+\) | \(J_2\ K_2\) | \(J_1\ K_1\) | \(J_0\ K_0\) |
|---|---|---|---|---|
| 0 0 0 | 0 0 1 | 0 × | 0 × | 1 × |
| 0 0 1 | 0 1 1 | 0 × | 1 × | × 0 |
| 0 1 0 | unused — all six entries × | |||
| 0 1 1 | 1 1 1 | 1 × | × 0 | × 0 |
| 1 0 0 | 0 0 0 | × 1 | 0 × | 0 × |
| 1 0 1 | unused — all six entries × | |||
| 1 1 0 | 1 0 0 | × 0 | × 1 | 0 × |
| 1 1 1 | 1 1 0 | × 0 | × 0 | × 1 |
Each map now has five don't-cares out of eight cells — three from the JK excitation table and two from the unused states — so the groupings are large. For \(J_2\) the only 1 is at 011, the 0s are at 000 and 001, and everything else is free; the largest legal group containing 011 and no 0 is the four cells with \(Q_1 = 1\), giving \(J_2 = Q_1\). For \(K_2\) the only 1 is at 100 and the 0s are at 110 and 111, so the four cells with \(Q_1 = 0\) give \(K_2 = Q_1'\). Working the other four maps the same way:
Six wires and no gates at all: each stage copies its neighbour, and the last copies the complement of the first. That is the twisted ring, fallen out of a K-map rather than asserted.
Checking the wanted states: from 011, \(J_2 = Q_1 = 1\) and \(K_2 = 0\) so \(Q_2\) sets; \(J_1 = Q_0 = 1\), \(K_1 = Q_0' = 0\) so \(Q_1\) stays 1; \(J_0 = Q_2' = 1\), \(K_0 = Q_2 = 0\) so \(Q_0\) stays 1. Next state 111, as specified. The other five states check the same way. What has not been checked is the two unused states, and that omission is the subject of Section 6.
Notice how much the unused states bought: every one of the six equations came out as a single literal, where the mod-8 counter of Example 24.1 needed an AND gate. That is the usual pattern — spare patterns become don't-cares and don't-cares shrink the logic. They are not free, though, and Section 6 is the bill.
5 Up–Down Counters with Mode Control
A counter that must run in both directions needs a mode input, conventionally \(M\), with \(M = 1\) selecting up and \(M = 0\) selecting down. The design procedure absorbs it without modification: \(M\) simply becomes another map variable, so a three-bit up–down counter is minimised on four-variable maps in \(M, Q_2, Q_1, Q_0\) with sixteen rows.
Section 3 already gives the two halves of the answer. Counting up, stage \(i\) toggles when every lower bit is 1; counting down, it toggles when every lower bit is 0. The mode input selects between the two conditions, so for a three-bit counter
Working the four-variable maps out in full gives exactly these expressions and nothing smaller, so the intuitive answer and the formal one agree. Each stage costs two AND gates and an OR gate, plus one inverter for \(M'\) shared by the whole counter.
Two simplifications are worth noticing. The middle equation is \(M\,Q_0 + M'\,Q_0' = (M \oplus Q_0)'\), a single XNOR gate. The top one factors as \((M \oplus Q_1)'(M \oplus Q_0)'\), two XNORs and an AND — check it on all eight combinations if it looks like a coincidence. Written that way the pattern is clear: a stage toggles when every lower bit agrees with the direction bit.
It is tempting to build an up–down counter by switching the clock instead — a multiplexer choosing \(Q_i\) or \(Q'_i\) as the next stage's clock, as suggested for the ripple counter in Chapter 23. Do not. Anything that switches a clock line can generate an edge at the instant of switching, and that edge is indistinguishable from a real clock pulse, so changing direction can insert or lose a count. Gating \(J\) and \(K\) leaves the clock alone: the mode input has until the next clock edge to settle, and if it changes at some awkward moment the worst that happens is that the counter counts in the old direction for one more edge.
The other standard control inputs follow the same rule. A synchronous enable is ANDed into every \(J\) and \(K\) so that \(EN = 0\) makes every stage hold; a synchronous load steers a parallel input in by \(J_i = LD \cdot P_i + LD' \cdot(\text{count logic})\). All of them act through the data inputs. One clock, distributed to everything and gated by nothing, is what makes a synchronous design analysable at all.
6 Unused States, Self-Starting and Lock-Out
A counter of modulus \(M\) built from \(n\) flip-flops has \(2^n - M\) unused states, entered as don't-cares so that the equations come out smaller. But the flip-flops are real and the unused patterns are reachable: a noisy power-up or a momentarily violated setup time can leave the counter in one of them. What happens next was decided by the minimisation, not by the designer, and it has to be checked.
A design is self-starting if every unused state leads, in a finite number of clock edges, into the wanted sequence. If instead the unused states lead only to one another, the counter is trapped in a cycle it can never leave. That is lock-out, and the only cure once the equipment is built is to switch it off and on again — with no guarantee that it will come up in a wanted state the second time either.
The design of Example 24.2 gave \(J_2 = Q_1\), \(K_2 = Q_1'\), \(J_1 = Q_0\), \(K_1 = Q_0'\), \(J_0 = Q_2'\), \(K_0 = Q_2\). Apply these to the two unused states.
State 010 (\(Q_2 = 0, Q_1 = 1, Q_0 = 0\)). \(J_2 = Q_1 = 1\) and \(K_2 = Q_1' = 0\), so \(Q_2\) is set to 1. \(J_1 = Q_0 = 0\) and \(K_1 = Q_0' = 1\), so \(Q_1\) is cleared to 0. \(J_0 = Q_2' = 1\) and \(K_0 = Q_2 = 0\), so \(Q_0\) is set to 1. The next state is 101.
State 101 (\(Q_2 = 1, Q_1 = 0, Q_0 = 1\)). \(J_2 = 0\), \(K_2 = 1\), so \(Q_2\) clears. \(J_1 = Q_0 = 1\), \(K_1 = 0\), so \(Q_1\) sets. \(J_0 = Q_2' = 0\), \(K_0 = Q_2 = 1\), so \(Q_0\) clears. The next state is 010.
| Present state | \(J_2 K_2\) | \(J_1 K_1\) | \(J_0 K_0\) | Next state | Verdict |
|---|---|---|---|---|---|
010 | 1 0 | 0 1 | 1 0 | 101 | another unused state |
101 | 0 1 | 1 0 | 0 1 | 010 | back where it started |
The two unused states form a closed loop of length two. A counter that finds itself in either of them will alternate between them for ever, producing a perfectly steady output that is not the sequence anyone asked for. The design is not self-starting; it locks out.
The repair is to stop treating the unused states as don't-cares and specify their next states instead. The safest specification is to send every unused state to the start of the sequence, but that is more constraint than is needed and it costs gates. It is enough to break the loop at one point: force 010 to go to a state that is in the wanted ring, and 101 will then fall into the ring through 010 one edge later.
Redo the minimisation of Example 24.2 with one row changed: 010 now has the specified next state 011. State 101 is left as a don't-care. The excitation entries for the new row are \(Q_2: 0 \to 0\) so \(J_2 = 0, K_2 = \times\); \(Q_1: 1 \to 1\) so \(J_1 = \times, K_1 = 0\); \(Q_0: 0 \to 1\) so \(J_0 = 1, K_0 = \times\). Re-minimising the six maps with those entries in place gives
Two two-input AND gates where there were none, which is the price. Now enumerate all eight states with the new equations:
| Present | \(J_2 K_2\) | \(J_1 K_1\) | \(J_0 K_0\) | Next | |
|---|---|---|---|---|---|
000 | 0 1 | 0 0 | 1 0 | 001 | wanted |
001 | 0 1 | 1 0 | 1 0 | 011 | wanted |
010 | 0 0 | 0 0 | 1 0 | 011 | unused → ring |
011 | 1 0 | 1 0 | 1 0 | 111 | wanted |
100 | 0 1 | 0 1 | 0 1 | 000 | wanted |
101 | 0 1 | 1 0 | 0 1 | 010 | unused → unused → ring |
110 | 0 0 | 0 1 | 0 1 | 100 | wanted |
111 | 1 0 | 1 0 | 0 1 | 110 | wanted |
The six wanted transitions are unchanged, 010 joins the ring at 011 on the next edge, and 101 reaches 010 and then the ring, so the counter recovers from any starting state within two clock edges. The design is self-starting.
Not every design with unused states locks out. On a mod-5 counter (states 000 to 100, minimised with 101, 110 and 111 as don't-cares) the equations are \(J_2 = Q_1Q_0\), \(K_2 = 1\), \(J_1 = K_1 = Q_0\), \(J_0 = Q_2'\), \(K_0 = 1\); tracing the three unused states through those equations gives 101 → 010, 110 → 010 and 111 → 000, so all three enter the count on the very next edge — self-starting, but by luck rather than by design. The check takes a few minutes and must always be made.
7 Maximum Frequency Compared with the Ripple Counter
The clock period of a synchronous counter has to accommodate three things in series: the flip-flops must produce new outputs, the input logic must compute the next set of \(J\) and \(K\) values from them, and those values must be stable for the setup time before the next edge arrives.
Compare this with \(f_{max} = 1/(n\,t_{pd})\) for the ripple counter of Chapter 23. The number of stages has vanished from the expression — provided \(t_{logic}\) can be kept to a single gate level.
Whether it can depends on how the carry is distributed, and there are two standard arrangements.
- Parallel carry. Each stage has its own AND gate taking all the lower outputs directly, so \(J_3 = Q_2Q_1Q_0\) is one three-input gate and \(J_7\) is one seven-input gate. \(t_{logic}\) is one gate delay whatever \(n\) is, so \(f_{max}\) does not degrade at all. The cost is gates of increasing width, which eventually run out of fan-in.
- Serial or ripple carry. Each stage ANDs the previous stage's enable with the previous output, \(E_{i+1} = E_i \cdot Q_i\), so every gate has two inputs but the enable signal passes through \(n-2\) of them. \(t_{logic} = (n-2)t_g\), and \(f_{max}\) does fall with \(n\) — though the counter is still synchronous, so the outputs still change together and nothing glitches.
Take \(t_{pd} = 12\) ns, \(t_{su} = 5\) ns and a gate delay \(t_g = 9\) ns — the same numbers used for the ripple counter in Chapter 23.
| \(n\) | Ripple, \(n\,t_{pd}\) | Synchronous, serial carry | Synchronous, parallel carry |
|---|---|---|---|
| 4 | 48 ns → 20.83 MHz | 35 ns → 28.57 MHz | 26 ns → 38.46 MHz |
| 8 | 96 ns → 10.42 MHz | 71 ns → 14.08 MHz | 26 ns → 38.46 MHz |
| 16 | 192 ns → 5.21 MHz | 143 ns → 6.99 MHz | 26 ns → 38.46 MHz |
For the parallel-carry column, \(t_{pd} + t_{logic} + t_{su} = 12 + 9 + 5 = 26\) ns and \(f_{max} = 1/26\text{ ns} = 38.46\) MHz for every \(n\). For the serial-carry column with \(n = 8\), \(t_{logic} = 6 \times 9 = 54\) ns, so \(T_{clk} \ge 12 + 54 + 5 = 71\) ns and \(f_{max} = 14.08\) MHz. The four-bit parallel-carry counter is 1.85 times faster than the four-bit ripple counter, and the sixteen-bit one is 7.4 times faster — the advantage grows with the width, which is the point.
The figures understate the difference: the ripple counter's 48 ns is time during which its outputs are actively wrong, while the synchronous counter's 26 ns is time during which its outputs are correct and have merely not changed yet.
The bargain is now clear. A ripple counter costs \(n\) flip-flops and no gates; a synchronous counter costs \(n\) flip-flops, \(n-2\) AND gates and a clock distributed to \(n\) loads. In exchange the outputs change together, decoded outputs can be used as strobes, the modulus is chosen by design rather than by resetting, control inputs are added without touching the clock, and the maximum frequency stops depending on the width. Every 74-series counter worth using at speed — the 74161, 74163, 74191 — is synchronous. Chapter 25 takes the shift register down the same road, and Chapter 26 generalises the procedure of Section 2 to machines whose next state depends on inputs as well as on where they are.
8 Summary and Key Results
| Item | Result | Consequence |
|---|---|---|
| Clock distribution | One clock to every flip-flop; nothing gates it | The word is valid \(t_{pd}\) after the edge, whatever \(n\) is |
| Design procedure | State table → excitation table → K-map per input → circuit | Works for any sequence and any flip-flop type |
| Binary up counter | \(J_i = K_i = Q_{i-1}\cdots Q_0\), with \(J_0 = K_0 = 1\) | One AND gate per stage; complement the terms for a down counter |
| Non-binary sequence | Unused states enter every map as don't-cares | Smaller equations — the six-state Johnson sequence needs no gates at all |
| Up–down control | \(J_1 = K_1 = MQ_0 + M'Q_0'\); \(J_2 = K_2 = MQ_1Q_0 + M'Q_1'Q_0'\) | Gate the data inputs, never the clock |
| Self-starting check | Compute the next state of every unused pattern | A closed loop among unused states is lock-out; the counter never recovers |
| Lock-out repair | Specify just enough unused transitions to break every stray loop | Two AND gates fixed the six-state counter; sending all unused states to 000 costs more |
| Maximum frequency | \(f_{max} = 1/(t_{pd} + t_{logic} + t_{su})\) | 38.46 MHz with parallel carry at any width, against 20.83 MHz for a four-stage ripple counter |
9 Common Mistakes
The don't-cares make the equations smaller, and the minimisation then assigns each of them a value that nobody chose. Sometimes the result is self-starting and sometimes it is a closed loop among the unused states that the counter can never leave. The check costs a few minutes: substitute the finished equations into every unused pattern and follow where it goes. A design that has not had this check is not finished.
In the mod-8 counter, \(J_2 = Q_1Q_0\) uses the values of \(Q_1\) and \(Q_0\) as they stood before the clock edge, not after it. Students working through state 011 sometimes toggle \(Q_0\) to 0 first and then conclude that \(J_2 = 0\), which gives 000 instead of 100. All the inputs are sampled at the same instant. This is exactly the property that makes an edge-triggered flip-flop necessary and a transparent latch useless here.
Multiplexing \(Q\) and \(Q'\) into a clock input, or ANDing an enable signal into the clock line, produces an edge at the moment of switching that is indistinguishable from a clock pulse, and the counter gains or loses a count. Every control input belongs on \(J\) and \(K\): direction by selecting \(Q_i\) or \(Q'_i\) in the product terms, enable by ANDing into every \(J\) and \(K\). One clock, ungated, is the whole basis of synchronous design.
10 Chapter Review
1. Design a synchronous mod-5 counter (states 000 to 100) with JK flip-flops, and determine whether it is self-starting.
The state table is 000→001→010→011→100→000, with 101, 110 and 111 unused and entered as don't-cares in every column. Taking the JK excitation entries and minimising the six maps gives \(J_2 = Q_1Q_0\), \(K_2 = 1\), \(J_1 = K_1 = Q_0\), \(J_0 = Q_2'\), \(K_0 = 1\). Note that \(J_0\) is \(Q_2'\) rather than 1: the count must go from 100 to 000 rather than to 101, so \(Q_0\) must not set when \(Q_2\) is 1. Testing the unused states: from
101, \(J_2 = 0, K_2 = 1\) clears \(Q_2\); \(J_1 = K_1 = 1\) toggles \(Q_1\) to 1; \(J_0 = 0, K_0 = 1\) clears \(Q_0\), giving010. From110: \(K_2 = 1\) clears \(Q_2\), \(J_1 = K_1 = Q_0 = 0\) holds \(Q_1\) at 1, \(K_0 = 1\) holds \(Q_0\) at 0, giving010. From111: \(Q_2\) clears, \(Q_1\) toggles to 0, \(Q_0\) clears, giving000. All three unused states enter the count on the next edge, so the design is self-starting.2. Explain why a synchronous counter's maximum frequency does not fall as stages are added, when a ripple counter's does.
In a ripple counter the carry is communicated by clock edges travelling down the chain, so the last stage cannot change until \(n\) flip-flop delays have elapsed and \(f_{max} = 1/(n\,t_{pd})\). In a synchronous counter the carry condition — every lower bit is 1 — is computed by combinational logic from the outputs as they already stand, during the clock period when nothing is changing. The critical path is one flip-flop delay, then the logic that computes the next \(J\) and \(K\) values, then the setup time, so \(f_{max} = 1/(t_{pd} + t_{logic} + t_{su})\). With parallel carry each stage has its own single AND gate on the lower outputs, so \(t_{logic}\) is one gate delay however wide the counter is and \(n\) does not appear at all. With serial carry the enable passes through \(n-2\) two-input gates and the frequency does fall, but the counter is still glitch-free because the outputs still change together.
3. A three-bit counter is required to produce 0, 2, 3, 6, 7, 5, 1, 4 and repeat. How many flip-flops are needed, how many unused states are there, and what does the design procedure require that the mod-8 binary design did not?
Eight distinct states need three flip-flops, and since \(2^3 = 8\) exactly, there are no unused states and no don't-cares from that source — the only don't-cares available are the ones the JK excitation table supplies. The procedure is otherwise identical: write the eight rows of the state table in the specified order (000→010, 010→011, 011→110, 110→111, 111→101, 101→001, 001→100, 100→000), fill in the six excitation columns, and minimise six three-variable maps. What the mod-8 binary design got for free was structure: its carry rule gave \(J_i = K_i = Q_{i-1}\cdots Q_0\) with one gate per stage. An arbitrary sequence has no such rule, the six maps have no pattern to them, and the equations will generally need two or three product terms each. There is also nothing to check for self-starting, because every state is a wanted state.
4. Derive the \(J\) and \(K\) equations for a three-bit synchronous down counter, and show that they are consistent with the up–down equations of Section 5.
In a descending binary count, bit \(i\) changes when every bit below it is 0: going from 100 to 011, \(Q_0\) changes on every edge, \(Q_1\) changes when \(Q_0 = 0\), and \(Q_2\) changes when \(Q_1 = Q_0 = 0\). Since a stage that changes must toggle, \(J_0 = K_0 = 1\), \(J_1 = K_1 = Q_0'\) and \(J_2 = K_2 = Q_1'Q_0'\). Substituting \(M = 0\) into the up–down equations \(J_1 = K_1 = MQ_0 + M'Q_0'\) and \(J_2 = K_2 = MQ_1Q_0 + M'Q_1'Q_0'\) kills the first product term in each and leaves \(Q_0'\) and \(Q_1'Q_0'\), which is exactly this result; substituting \(M = 1\) leaves \(Q_0\) and \(Q_1Q_0\), the up counter of Example 24.1. The mode input simply selects which of the two conditions is presented to the toggle inputs.
5. A four-bit synchronous counter is built from flip-flops with \(t_{pd} = 14\) ns and \(t_{su} = 6\) ns, using AND gates of 8 ns delay in a parallel-carry arrangement. Find the maximum clock frequency, and compare it with a ripple counter using the same flip-flops.
With parallel carry the longest path is one flip-flop delay, one gate delay and the setup time: \(T_{clk} \ge 14 + 8 + 6 = 28\) ns, so \(f_{max} = 1/28\text{ ns} = 35.7\) MHz. The four-stage ripple counter made from the same flip-flops needs \(4 \times 14 = 56\) ns for a full carry, giving \(f_{max} = 1/56\text{ ns} = 17.9\) MHz — almost exactly half. Widening both to eight bits leaves the synchronous figure at 35.7 MHz, since the only change is a wider AND gate on the top stage, while the ripple figure falls to \(1/(8 \times 14\text{ ns}) = 8.9\) MHz. The synchronous counter is also usable at its stated frequency, whereas the ripple counter's outputs are wrong for the whole 56 ns and would produce false decodes throughout.