By the end of this chapter you should be able to:
- Analyse the cross-coupled NOR latch, obtain its state table, and explain precisely why \(S = R = 1\) is forbidden.
- Relate the NAND \(\overline{S}\,\overline{R}\) latch to the NOR latch by De Morgan's theorems, and use it to debounce a switch.
- Explain what a gated latch adds, why the D latch eliminates the forbidden input, and what the transparency problem is.
- Describe the race-around condition in a level-triggered JK flip-flop and state the condition under which it occurs.
- Explain master-slave construction and edge triggering, including how a narrow trigger pulse is generated.
- Write the characteristic table and characteristic equation of the SR, D, JK and T flip-flops, and derive one from another.
- Define setup time, hold time and clock-to-Q delay from a timing diagram, and use them to find the maximum clock frequency of a synchronous circuit.
Everything designed so far in this course has had the same property: connect the inputs, wait for the gates to settle, and the outputs are determined. A combinational circuit has no history. It cannot count, because counting means knowing what the last number was; it cannot hold the result of a calculation while the next one is performed; it cannot even remember that a button was pressed once the button is released. Half of digital electronics is therefore still missing, and this chapter supplies it.
The missing ingredient is feedback. Take two gates and connect each one's output to the other's input, and the circuit is no longer a function of its inputs alone: it has two self-consistent states, and which of them it occupies depends on what happened to it earlier. From that one arrangement come the latch, the flip-flop, and with them the counters, registers and state machines of the rest of Part 5. The chapter builds the sequence — SR latch, gated latch, JK flip-flop, master-slave, edge-triggered flip-flop — as a series of repairs, each fixing a defect exposed by the one before, and ends with the timing parameters that decide whether a synchronous circuit works at all.
1 Feedback, Bistability and the NOR Latch
Start with a NOR gate and recall its one useful asymmetry: a NOR output is 1 only when every input is 0, so a single 1 on any input forces the output low, and a gate with all inputs at 0 is free to go high. Now take two of them and cross-couple: the output of each becomes an input of the other. Calling the outputs \(Q\) and \(\overline{Q}\), and the remaining free inputs \(R\) and \(S\), the circuit is described by two simultaneous equations:
These are not a definition of \(Q\) in terms of the inputs — \(Q\) appears on both sides. They are a pair of conditions that the circuit's voltages must satisfy, and the question to ask of them is not \"what is \(Q\)?\" but \"which combinations of \(Q\) and \(\overline{Q}\) are consistent?\"
Test the four input combinations by substitution. With \(S = R = 0\), try \(Q = 0\): then \(\overline{Q} = (0 + 0)' = 1\), and feeding that back, \(Q = (0 + 1)' = 0\) — consistent. Now try \(Q = 1\): then \(\overline{Q} = (0+1)' = 0\) and \(Q = (0+0)' = 1\) — also consistent. Two states satisfy the same equations, so the algebra genuinely does not determine the output. The circuit is bistable, and which state it sits in is decided by its past.
With \(S = 0\), \(R = 1\) the upper gate has a 1 on an input, so \(Q = 0\) regardless of feedback, and then \(\overline{Q} = 1\): a single consistent state, and the latch is reset. With \(S = 1\), \(R = 0\) the argument mirrors and the latch is set to \(Q = 1\). In both cases removing the input afterwards returns the circuit to the \(S = R = 0\) case, which holds whatever state it has been left in. That is memory: an input pulse leaves a permanent trace.
The fourth combination, \(S = R = 1\), is the one every examination asks about. Both gates have a 1 on an input, so both outputs are forced to 0. There is nothing indeterminate about that: \(Q = \overline{Q} = 0\), definitely and measurably. Two separate things are wrong with it.
- The outputs are no longer complementary. Every circuit downstream has been designed on the assumption that \(\overline{Q}\) is the inverse of \(Q\), and that assumption has quietly failed. A flip-flop whose two outputs read 0 and 0 is not in either of its states.
- Worse is what happens on release. Take \(S\) and \(R\) back to 0 at the same instant, and both gates now see 0 on both inputs, so both begin to rise towards 1. As soon as one of them gets there it forces the other back down, and the winner is decided by which gate is faster — by a fabrication tolerance, a temperature difference, a difference in load capacitance of a fraction of a picofarad. The final state is not undefined but unpredictable, which is worse, because it will be repeatable on the bench and different on the next board.
Each gate inverts, so going round the loop twice restores the sense of the signal: any disturbance that starts \(Q\) rising is amplified by the loop until \(Q\) is hard against the supply rail, where it holds itself. The same regeneration that makes the latch stable in each of its two states is what makes the transition between them so fast, and what makes the forbidden release so unpredictable.
2 The NAND Latch and Switch Debouncing
Cross-coupling two NAND gates instead of two NOR gates gives a latch that behaves the same way but is driven by active-low inputs, conventionally written \(\overline{S}\) and \(\overline{R}\). This is not a different circuit so much as the same circuit read through De Morgan's theorems: Chapter 6 showed that a NAND is an OR gate with inverted inputs, so a cross-coupled NAND pair is a cross-coupled OR pair driven by complemented inputs, and every entry in the table moves accordingly.
| \(\overline{S}\) | \(\overline{R}\) | \(Q(t+1)\) | Meaning |
|---|---|---|---|
| 1 | 1 | \(Q(t)\) | hold — this is now the quiescent input |
| 0 | 1 | 1 | set |
| 1 | 0 | 0 | reset |
| 0 | 0 | 1 * | forbidden — both outputs go to 1 |
Two practical differences matter. The quiescent input is now 11 rather than 00, which suits TTL, where an unconnected input floats high; and the forbidden combination drives both outputs to 1 rather than to 0. The reason the NAND version is met more often is simply that most catalogue packages contain NAND gates, and that a mechanical switch naturally produces a logic 0 by connecting a pin to ground.
That last point leads to the classic application. Press any mechanical switch and its contacts do not close once: they bounce, making and breaking contact repeatedly for anything from a few hundred microseconds to about 10 ms before settling. To a human that is instant; to a counter clocked at 1 MHz it is up to 10 000 separate closures, and the counter records all of them.
Use a single-pole double-throw switch. Its common terminal goes to ground, and its two fixed contacts go to \(\overline{S}\) and \(\overline{R}\) of a NAND latch, each also tied to the supply through a pull-up resistor of a few kilohms so that an unconnected contact reads 1.
With the switch resting on the \(\overline{S}\) contact, \(\overline{S} = 0\) and \(\overline{R} = 1\), so \(Q = 1\). Throw the switch. The wiper leaves the \(\overline{S}\) contact, and for the whole of its flight both inputs are 1 — the hold condition — so \(Q\) stays at 1. The wiper then strikes the \(\overline{R}\) contact and bounces. The first contact drives \(\overline{R}\) to 0 and resets the latch to \(Q = 0\). Every subsequent bounce either repeats \(\overline{R} = 0\), which resets an already-reset latch and changes nothing, or lifts to \(\overline{R} = 1\), which is the hold condition and also changes nothing.
So the output makes exactly one clean transition per throw. Note what is being exploited: the latch is not filtering the bounce, it is ignoring repetitions, because a set command applied to a latch that is already set is idle. This is why the trick needs a changeover switch and does not work with a simple push-button, which would need an RC delay or a Schmitt trigger.
3 Gated Latches, Level Sensitivity and the Transparency Problem
A plain SR latch responds the moment its inputs change. In a system of any size that is useless, because the inputs to one latch are the outputs of other logic, which changes at different times as different signal paths settle. What is needed is a way of saying now: a control input that decides when the latch is allowed to pay attention.
The gated SR latch adds it in the obvious way. AND each of \(S\) and \(R\) with an enable input \(EN\) before they reach the latch. With \(EN = 0\) both internal inputs are 0, the latch is in its hold condition and nothing on \(S\) or \(R\) has any effect; with \(EN = 1\) the latch behaves exactly as before. The forbidden combination survives: \(S = R = EN = 1\) is still illegal.
The gated D latch removes it, and does so by construction rather than by instruction. Take a single data input \(D\), send it to \(S\), and send \(D'\) through an inverter to \(R\). Now \(S\) and \(R\) are always complementary, so \(S = R = 1\) cannot arise however the circuit is driven. The illegal state has not been forbidden; it has been made unreachable, which is a much better kind of engineering, and it is the reason the D latch and the D flip-flop are the storage elements used in practice.
The characteristic equation of the gated D latch. It is a multiplexer equation: with \(EN = 1\) the output takes \(D\), and with \(EN = 0\) it takes its own present value. A D latch is a 2-to-1 multiplexer with its output fed back to one of its data inputs, and that is exactly how it is built inside a CMOS standard cell.
Useful as it is, the gated latch has a defect that stops it being the general answer. While \(EN = 1\) the output does not merely sample \(D\) once — it follows \(D\) continuously, reproducing every change with only a gate delay. The latch is transparent, and this is what is meant by calling it level-sensitive: the enable defines a window of time, not an instant.
Now put two such latches in series and drive both enables from the same signal, which is exactly what a shift register does. While the enable is high the first latch follows its input and the second follows the first, so a change at the input of the chain runs straight through both stages. Nothing shifted by one place; the data raced through as far as the enable window allowed. How many stages it crosses depends on the width of the enable pulse and on the gate delays — a quantity no designer wants a circuit's function to depend on.
The requirement, then, is sharper than \"control when the latch listens\". The output must be allowed to change at one instant, and the input must be sampled at that same instant, so that no path can ever be open from the input of a chain to its output. The rest of the chapter is about achieving that.
4 The JK Flip-Flop and the Race-Around Condition
Before solving the timing problem, the logic problem is worth finishing. The D latch removed the forbidden input by throwing away one degree of freedom: there is now only one data input, and the useful \"do nothing\" and \"toggle\" behaviours are gone. The JK flip-flop keeps two inputs and removes the forbidden state a different way — by making the illegal combination impossible with feedback rather than with an inverter.
Take a clocked SR latch and generate its internal inputs as
Because \(Q\) and \(\overline{Q}\) are complements, at most one of the two terms \(J\overline{Q}\) and \(KQ\) can be 1 at any moment, so \(S\) and \(R\) can never both be 1 no matter what \(J\) and \(K\) are. The forbidden input has been engineered out, and the combination \(J = K = 1\) is free to be given a new and useful meaning.
That meaning falls out of the equations. With \(J = K = 1\) and \(Q = 0\), the term \(J\overline{Q}\) sets the latch; with \(Q = 1\), the term \(KQ\) resets it. Either way the output ends up as the complement of what it was: \(J = K = 1\) is a toggle command, and it is the operation on which every counter in Chapters 23 and 24 is built.
| \(J\) | \(K\) | \(Q(t)\) | \(Q(t+1)\) | Operation |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | no change |
| 0 | 0 | 1 | 1 | |
| 0 | 1 | 0 | 0 | reset |
| 0 | 1 | 1 | 0 | |
| 1 | 0 | 0 | 1 | set |
| 1 | 0 | 1 | 1 | |
| 1 | 1 | 0 | 1 | toggle |
| 1 | 1 | 1 | 0 |
And now the timing problem returns, sharper than before. Suppose the flip-flop is level-triggered, so the internal latch is live for the whole time the clock is high, and suppose \(J = K = 1\). The output toggles. But the toggled output is fed straight back to the gates that generated \(S\) and \(R\), so after one trip round the loop — two gate delays, say \(2t_{pd}\) — the flip-flop toggles again. And again. This is the race-around condition: while the clock is high the output oscillates with a period of about \(2t_{pd}\), and the state it happens to be in when the clock falls is decided by whether an odd or an even number of toggles fitted into the pulse.
The condition for correct operation is that the clock's high time must be shorter than the loop delay, \(t_w < 2t_{pd}\). With gates of \(t_{pd} = 10\) ns that means a high time under 20 ns, which at a 50 per cent duty cycle would require a clock above 25 MHz — and a slower clock makes matters worse, not better, because it widens the pulse. You cannot design your way out of race-around by adjusting the clock frequency; you have to change the structure of the flip-flop.
5 Master-Slave Construction and Edge Triggering
Two structural fixes exist, and both work by making sure that no signal path is ever open from the data input to the output.
The master-slave flip-flop puts two gated latches in series and drives their enables from complementary clocks. While \(CLK = 1\) the master is open and follows the data input, while the slave is closed and holds the previous value, so the output does not move. While \(CLK = 0\) the master is closed, holding whatever it last saw, and the slave is open and copies it. The output therefore changes once per clock cycle, at the falling edge, and there is never an instant when both latches are open — which is precisely the condition that race-around and transparency both violated.
Master-slave has a defect of its own, and it is worth knowing because it is the reason the technique was abandoned. The master is open for the whole high half of the clock, so a brief glitch on \(J\) during that time is captured by the master and duly passed to the output at the falling edge, even though the glitch had long gone before the edge arrived. This is ones catching, and it makes a master-slave JK sensitive to noise on its inputs in a way that is very hard to debug. Master-slave parts are described as pulse-triggered rather than edge-triggered for this reason.
The edge-triggered flip-flop attacks the problem directly by shrinking the window instead of splitting it in two. The clock is fed to a small network that produces a pulse only at the moment of a transition, and that pulse, rather than the clock itself, enables the storage element. Figure 21.3(b) shows the standard textbook version: the clock goes to one input of an AND gate directly and to the other through an odd number of inverters. Immediately after a rising edge the direct input is already 1 while the inverted, delayed input has not yet fallen, so the AND output is high — for exactly as long as the inverter chain takes to respond, three propagation delays, a few nanoseconds. After that the AND output falls and stays low until the next rising edge.
Because the sampling window is now a few nanoseconds rather than half a clock period, race-around cannot occur (the loop delay is longer than the window), ones catching cannot occur (there is almost no window in which to catch anything), and a chain of flip-flops shifts by exactly one place per clock. Commercial parts do not literally use an inverter chain — the 7474 positive-edge-triggered D flip-flop achieves the same effect with six NAND gates arranged so that the internal state is captured by the edge itself — but the principle is the one drawn here.
On a schematic the distinction is carried by the clock input. A small wedge on the clock pin means edge-triggered; a wedge with a bubble means the falling edge; no wedge means a level-sensitive latch. It is worth being pedantic about the vocabulary: latch for the level-sensitive device, flip-flop for the edge-triggered one. Data sheets keep that distinction, and choosing the wrong part gives a circuit that simulates correctly and fails on the board.
6 D, JK and T: Characteristic Tables and Equations
A characteristic table lists the next state \(Q(t+1)\) for every combination of present state and inputs, and a characteristic equation is that table minimised into a Boolean expression. The equation is the tool that makes the analysis of sequential circuits possible: substitute the expressions driving the flip-flop's inputs and you have the next state directly, which is how the counters of Chapter 24 and the state machines of Chapter 26 are analysed. (The reverse question — what inputs will produce a required transition — is answered by the excitation table, and that is Chapter 22.)
| Type | Inputs | Characteristic table | Characteristic equation |
|---|---|---|---|
| SR | \(S, R\) | 00: hold; 01: reset; 10: set; 11: not allowed | \(Q(t+1) = S + R'Q\), with \(SR = 0\) |
| D | \(D\) | 0: \(Q(t+1) = 0\); 1: \(Q(t+1) = 1\) | \(Q(t+1) = D\) |
| JK | \(J, K\) | 00: hold; 01: reset; 10: set; 11: toggle | \(Q(t+1) = J\overline{Q} + \overline{K}Q\) |
| T | \(T\) | 0: hold; 1: toggle | \(Q(t+1) = T\overline{Q} + \overline{T}Q = T \oplus Q\) |
The SR equation is read off its table. The next state is 1 when \(S = 1\), and also when the latch was already at 1 and is not being reset, giving \(S + R'Q\); the side condition \(SR = 0\) records that one row of the table has no legitimate entry. Because the equation is only valid where \(SR = 0\), the two rows with \(S = R = 1\) are don't-cares on the K-map, and it is those don't-cares that make the expression as short as it is.
The JK equation does not need a fresh minimisation, because the JK flip-flop is an SR latch with \(S = J\overline{Q}\) and \(R = KQ\). Substituting into the SR equation:
using De Morgan's theorem on \((KQ)'\), distributing, and then discarding \(\overline{Q}Q = 0\). Checking all eight rows: \(J=K=0\) gives \(Q(t+1) = \overline{K}Q = Q\), hold; \(J=0, K=1\) gives 0, reset; \(J=1, K=0\) gives \(\overline{Q} + Q = 1\), set; and \(J=K=1\) gives \(\overline{Q}\), toggle. The table is reproduced exactly.
The T flip-flop is a JK with its two inputs tied together, \(J = K = T\). Substituting gives \(Q(t+1) = T\overline{Q} + \overline{T}Q\), which is the definition of the exclusive-OR, so \(Q(t+1) = T \oplus Q\). It has exactly two behaviours — hold when \(T = 0\) and toggle when \(T = 1\) — and no other type is more convenient for building a binary counter, since counting in binary is toggling bit \(i\) whenever all the bits below it are 1.
A D flip-flop is likewise a JK with \(J = D\) and \(K = D'\): substituting gives \(Q(t+1) = D\overline{Q} + DQ = D\), independent of the present state, which is the whole point of the D type. These conversions between types, done systematically with excitation tables, are the subject of the next chapter.
7 Setup Time, Hold Time, Clock-to-Q Delay and the Asynchronous Inputs
An edge-triggered flip-flop is described as sampling its input \"at the clock edge\", but no physical circuit can sample at a mathematical instant. Internally, the edge opens a path for a few gate delays while a regenerative loop captures the input value, and the data must be present and settled while that happens. Three parameters describe the requirement, and every data sheet lists them.
- Setup time \(t_{su}\) — the interval before the active clock edge throughout which the data input must already be stable. Typically 2 to 20 ns.
- Hold time \(t_h\) — the interval after the active edge throughout which the data input must remain stable. Often quoted as 0 ns or even as a small negative number.
- Clock-to-Q delay \(t_{co}\) — the delay from the active edge to a valid new output. This is a propagation delay like any other, and it is the flip-flop's contribution to the delay of the loop it sits in.
What happens if the requirement is broken? The flip-flop may enter a metastable state, in which the internal loop is balanced almost exactly between its two stable points and the output sits at an invalid level part-way between the supply rails. Regeneration eventually resolves it, but the time taken has no upper bound: the closer the balance, the longer the resolution, and one can only quote a mean time between failures for a given probability of the output still being invalid after some interval. Any signal that arrives from outside the clock domain — a push-button, a signal from another board — must therefore be passed through two flip-flops in series before being used, the first to absorb the metastability and the second to give it a whole clock period to resolve.
The three parameters together fix how fast a synchronous circuit can be clocked. Data leaving one flip-flop must travel through the combinational logic between the stages and arrive at the next flip-flop's input in time to meet its setup requirement, so the clock period must satisfy
With \(t_{co} = 12\) ns, a worst-case combinational path of \(t_{comb} = 20\) ns and \(t_{su} = 5\) ns, the minimum period is 37 ns and the maximum clock frequency about 27 MHz. Every synchronous design in the remainder of this course is governed by this inequality, and the whole business of pipelining is the business of cutting \(t_{comb}\).
A setup violation is a speed problem: the data arrived too late, and lengthening the clock period fixes it. A hold violation is not, because it says the data changed too soon after the edge, and that has nothing to do with the period — slowing the clock down leaves it exactly as it was. Hold violations are cured by adding delay to the data path, or by clocking the two flip-flops from the same buffer so that their clock edges coincide. It is the reason clock skew is taken so seriously in board and chip layout.
Finally, most flip-flops carry asynchronous preset and clear inputs, usually active-low and drawn \(\overline{PRE}\) and \(\overline{CLR}\). These act directly on the internal latch and override both the clock and the data input, forcing \(Q\) to 1 or to 0 immediately. Their purpose is initialisation: at power-up a flip-flop settles into whichever state its own asymmetries favour, so every sequential system needs a reset pulse to put its state into something known — a counter that starts from an arbitrary value is a counter with a random first count. Three rules go with them. They must never be left floating, since a floating TTL input reads as a 1 only by luck and a CMOS one may read as anything. They must never be asserted together, for the same reason \(S = R = 1\) is forbidden on the underlying latch. And releasing one just before a clock edge has its own timing requirement — the recovery time — because the latch needs to settle before it is asked to capture anything.
8 Summary and Key Results
| Device or parameter | Behaviour | Why it matters |
|---|---|---|
| NOR SR latch | \(Q = (R + \overline{Q})'\), \(\overline{Q} = (S + Q)'\); two stable states when \(S=R=0\) | The first circuit whose output depends on its own past |
| \(S = R = 1\) | Both outputs go to 0, so they are no longer complements | Releasing both together starts a race whose winner is set by gate delays |
| NAND \(\overline{S}\,\overline{R}\) latch | The same circuit with active-low inputs; 11 is the hold condition | Debounces a changeover switch by ignoring repeated commands |
| Gated D latch | \(Q(t+1) = EN\!\cdot\!D + EN'\!\cdot\!Q\); \(S\) and \(R\) always complementary | The forbidden input is made unreachable, not merely prohibited |
| Transparency | While \(EN = 1\) the output follows \(D\) continuously | Data races through a chain of latches; the shift is not one place per pulse |
| Race-around | A level-triggered JK with \(J=K=1\) toggles every \(2t_{pd}\) while \(CLK = 1\) | Needs \(t_w < 2t_{pd}\), which a slower clock makes worse, not better |
| Master-slave / edge trigger | Two latches with opposite enables, or a trigger pulse a few nanoseconds wide | No path is ever open input to output; edge triggering also avoids ones catching |
| \(t_{su}\), \(t_h\), \(t_{co}\) | Data stable before and after the edge; delay from edge to valid \(Q\) | \(T_{clk} \ge t_{co} + t_{comb} + t_{su}\); a violation risks metastability |
9 Common Mistakes
It does nothing of the kind. Both NOR gates have a 1 on an input, so both outputs are 0 — a perfectly definite, measurable condition, and one you can see on an oscilloscope. Two things are wrong with it, and neither is indefiniteness: \(Q\) and \(\overline{Q}\) are no longer complements, and when the inputs are released together the state the latch falls into is decided by which gate happens to be faster. Write unpredictable on release, not undefined.
Race-around happens because the clock stays high for longer than the feedback loop takes to go round, so the output can toggle more than once per pulse. Reducing the clock frequency at a fixed duty cycle makes the high time longer and the problem worse. The same reasoning applies to hold-time violations, which are also immune to a slower clock. Both are cured by changing the structure — master-slave or edge triggering in the first case, added path delay or better clock distribution in the second.
A latch is level-sensitive: it is transparent for as long as its enable is active. A flip-flop is edge-triggered: it samples at one instant. Substituting one for the other in a shift register or a counter gives a circuit whose behaviour depends on pulse widths and gate delays, and which will often work on a slow bench clock and fail at speed. The schematic tells you which you have: a wedge on the clock input means edge-triggered.
10 Chapter Review
1. Analyse the cross-coupled NOR latch algebraically for all four input combinations, and explain in terms of gate delays why \(S = R = 1\) is forbidden.
The circuit is \(Q = (R + \overline{Q})'\) and \(\overline{Q} = (S + Q)'\). For \(S = R = 0\) both \((Q, \overline{Q}) = (0,1)\) and \((1,0)\) satisfy the two equations, so the circuit is bistable and holds its present state. For \(S = 0, R = 1\) the upper gate is forced low, giving \((0,1)\) as the only consistent solution — reset. For \(S = 1, R = 0\) the mirror argument gives \((1,0)\) — set. For \(S = R = 1\) both gates have a 1 on an input, so \(Q = \overline{Q} = 0\): definite, but not complementary, so the latch is in neither of its states. The real objection is what follows. Take both inputs to 0 simultaneously and both gates now see all-zero inputs and start to rise. Whichever reaches a logic 1 first drives the other back down and wins, and which that is depends on propagation delays differing by fractions of a nanosecond, on load capacitance and on temperature. The result is repeatable on one device and different on the next, which is why the input is prohibited rather than merely documented.
2. Derive the characteristic equation of the JK flip-flop from that of the SR latch, and verify it against all eight rows of the JK characteristic table.
The JK flip-flop is an SR latch driven by \(S = J\overline{Q}\) and \(R = KQ\), which can never both be 1 because \(Q\) and \(\overline{Q}\) are complements. The SR characteristic equation is \(Q(t+1) = S + R'Q\). Substituting, \(Q(t+1) = J\overline{Q} + (KQ)'Q\). By De Morgan, \((KQ)' = \overline{K} + \overline{Q}\), so \(Q(t+1) = J\overline{Q} + \overline{K}Q + \overline{Q}Q\), and since \(\overline{Q}Q = 0\) this reduces to \(Q(t+1) = J\overline{Q} + \overline{K}Q\). Checking: with \(J = K = 0\) it gives \(Q\) for both values of \(Q\) — hold. With \(J = 0, K = 1\) it gives \(0\) for both — reset. With \(J = 1, K = 0\) it gives \(\overline{Q} + Q = 1\) for both — set. With \(J = K = 1\) it gives \(\overline{Q}\) — toggle. All eight rows agree with the table.
3. A level-triggered JK flip-flop is built from gates whose propagation delay is 8 ns, and is clocked at 1 MHz with a 50 per cent duty cycle. With \(J = K = 1\), estimate how many times the output toggles during one clock pulse and state the design rule that avoids the problem.
The feedback loop runs from the output back through the input gates to the latch and out again, about two gate delays, so \(2t_{pd} = 16\) ns per toggle. At 1 MHz with a 50 per cent duty cycle the clock is high for \(500\ \mu\text{s}\), which is \(500 \times 10^{-6} / 16 \times 10^{-9} = 31\,250\) loop times, so the output toggles of the order of thirty thousand times during a single pulse. Whether it is left high or low when the clock falls depends on whether that count is odd or even, which no designer can predict. The rule for a level-triggered JK is \(t_w < 2t_{pd}\) — the clock pulse must be narrower than the loop delay, here under 16 ns — which is quite impractical to guarantee, and is why level-triggered JK flip-flops are not used. The practical answer is a master-slave or an edge-triggered part, in which the sampling window is made shorter than the loop delay by construction.
4. A synchronous circuit uses flip-flops with \(t_{co} = 12\) ns and \(t_{su} = 5\) ns, with a worst-case combinational path of 20 ns between stages. Find the maximum clock frequency. If the circuit instead fails a hold-time check, would raising the clock period help?
Data must leave one flip-flop, cross the logic and arrive at the next in time to be set up, so \(T_{clk} \ge t_{co} + t_{comb} + t_{su} = 12 + 20 + 5 = 37\) ns and the maximum clock frequency is \(1/37\ \text{ns} = 27.0\) MHz. Raising the clock period would not help a hold-time failure. A hold violation means the new data reached the second flip-flop's input too soon after the edge — before that flip-flop had finished capturing the old data — and that race is between two paths from the same clock edge, so it is unaffected by how long the period is. The cures are to lengthen the short data path with buffers, or to reduce the clock skew between the two flip-flops so that the second sees the edge no later than the first.
5. Explain what a gated D latch does that a gated SR latch does not, and why a chain of gated D latches driven by a common enable cannot be used as a shift register.
The gated SR latch still has the illegal input \(S = R = EN = 1\), which must be avoided by whatever drives it. The gated D latch feeds \(D\) to \(S\) and \(D'\) to \(R\) through an inverter, so the two internal inputs are always complementary and the illegal combination cannot be produced at all; the forbidden state is designed out rather than prohibited. Its characteristic equation is \(Q(t+1) = EN\cdot D + EN'\cdot Q\). It cannot be chained, though, because it is transparent: while \(EN = 1\) the output follows the input continuously, so the second latch in a chain follows the first while the first is following its own input. A change at the head of the chain propagates through as many stages as the enable pulse is wide enough to allow, which is a number set by gate delays rather than by the design. A shift register needs an element that samples at one instant and changes at that same instant, which is what a master-slave or edge-triggered flip-flop provides.