SMPS Design and Closed-Loop Control

The DC gain is the sensitivity of output to duty ratio:

Note it depends on the input voltage, not the output. A buck running from 30 V has 2 dB more loop gain than one running from 24, so the loop must be stable across the whole input range — the compensator is designed once and must hold everywhere.

The resonance, from the output filter:

A \(Q\) of 5.4 gives a 14 dB peak and a phase that swings through 180° within a decade. And unlike the Ćuk resonance of Set 21, this one is damped by the load — at light load \(R\) rises and \(Q\) rises with it, so the worst case is no load.

The ESR zero, which the capacitor introduces for free:

Above this frequency the capacitor's impedance is dominated by its resistance, so the output stops rolling off. A left-half-plane zero, which adds phase — genuinely helpful, and one of the few places where a parasitic works in the designer's favour.

Evaluate at the intended crossover. Well above resonance the double pole falls at 40 dB per decade:

So the plant is already close to unity gain at 20 kHz. The compensator needs to add only 2.4 dB there — almost nothing. The gain is not the problem.

The phase is the problem:

Fifteen degrees short of an inversion. Close the loop with a plain integrator — which contributes another \(-90^\circ\) — and the total is \(-256^\circ\): comfortably unstable. The compensator must supply phase, not gain.

Which compensator, and why:

A double pole needs roughly 90° of boost to recover a usable margin, and only Type III can deliver it. That is the whole reason voltage-mode buck converters use the more complicated network.

The placement strategy. Each element is put where it does a specific job:

The two zeros are placed at the resonance so that their phase lead is already fully developed by the time the loop reaches 20 kHz. Placing them at the crossover instead would give only half the boost, since a zero contributes 45° at its own frequency.

Phase contributed by the two zeros at 20 kHz:

Nearly the full 180° available, because 20 kHz is almost six times the zero frequency. This is why the zeros go below the crossover, not at it.

Phase lost to the two high-frequency poles:

Modest, because both poles sit well above the crossover. Note that the pole at 79.6 kHz gives back exactly the 14.1° the plant's ESR zero contributed — they cancel, which is the intent.

Total compensator phase:

A net phase lead of nearly 45°, despite containing an integrator. That is what Type III buys, and it is the reason two zeros are needed rather than one.

The phase margin:

Right in the target band. Below 45° the transient response rings; above 60° it is over-damped and slow. Fifty-nine degrees gives roughly a 5% overshoot to a step — the standard compromise.

Set the gain. The compensator must supply \(+2.4\) dB at 20 kHz to bring the loop to unity there:

Which sets the resistor ratio in the network; everything else was set by the pole and zero placement. The gain is genuinely the last step, as Problem 1 anticipated.

Check the corners. A compensator designed at one operating point must survive the others:

The last row is a real trap. Substituting a low-ESR ceramic for an electrolytic removes the helpful zero, and a loop designed to rely on it loses phase margin. The same substitution that damaged the Ćuk in Set 21 damages the compensation here — for the same reason, that the parasitic was doing useful work.

What current mode does. An inner loop terminates the switch on-time when the inductor current reaches a commanded peak. The inductor stops behaving like an inductor and starts behaving like a current source:

The inductor's pole is absorbed into the inner loop, so the outer voltage loop sees only the output capacitor working against the load.

The new plant:

A single pole at 663 Hz plus the same ESR zero at 79.6 kHz. At 20 kHz the phase is roughly \(-90^\circ+14^\circ = -76^\circ\), against \(-166^\circ\) in voltage mode — ninety degrees better, for free.

Which changes the compensator required:

Three genuine advantages beyond the simpler compensator. Input feedforward is inherent because a higher input makes the current ramp faster, terminating the pulse sooner without the outer loop doing anything — so line rejection is excellent. And the peak current is bounded by construction, which is the same argument the hysteresis controller of Set 17 made.

But there is a catch. Above 50% duty ratio, a perturbation in the inductor current grows rather than decaying from cycle to cycle:

The result is subharmonic oscillation — alternate wide and narrow pulses at \(f_s/2\). It is not a small-signal instability that the compensator can fix; it lives in the inner loop and must be cured there.

Compute the slopes at \(D = 0.7\), which needs an input of \(12/0.7 = 17.1\) V:

The slope compensation required:

An artificial ramp of at least this slope is subtracted from the current command each cycle. A common choice is \(S_e = 0.5S_f = 300\) kA/s, which gives margin at all duty ratios; setting \(S_e = S_f\) gives deadbeat response, where any perturbation is removed in a single cycle.

What slope compensation costs:

A large compensating ramp swamps the sensed current signal, so the inner loop stops being a current loop and the advantages fade — the pole reappears, line feedforward weakens, and current limiting becomes duty-dependent. The design target is the minimum ramp that guarantees stability at the maximum duty ratio, and no more.

Three things happen in sequence when the load steps up:

The instantaneous ESR step:

Unavoidable and instant — no loop can respond to it, because it is a resistive drop, not a charge deficit. The only remedy is a lower-ESR capacitor.

The loop-limited droop. The capacitor supplies the extra current for roughly one loop time constant:

Now the independent check. Even with an infinitely fast loop, the inductor current cannot rise instantly:

The charge deficit while the inductor catches up. This is a hard floor set by the power stage — no controller can beat it.

Which one governs?

The loop is the limitation, not the power stage — so increasing the bandwidth will genuinely help, down to the 133 mV floor. Had the slew figure been the larger, more bandwidth would have achieved nothing and the answer would have been a smaller inductor or a bigger capacitor.

Test the remedies:

Bandwidth and capacitance are interchangeable in the droop term — doubling either halves it. Bandwidth is usually cheaper, but it is limited to about \(f_s/10\), so beyond 20 kHz here the switching frequency would have to rise too.

The step down is worse. Removing load leaves the inductor delivering current with nowhere to put it:

Here the two slopes happen to be equal, because \(V_{in} = 2V_o\). At high input the rise is fast and the fall slow, so the overshoot on a load release exceeds the undershoot on a load application — and at low input the reverse. The worst-case transient is at the input extreme, not the nominal.

The problem. The output must be sensed on the secondary, where it is, and the duty ratio must be set on the primary, where the switch is — and the two are separated by a barrier that must withstand several kilovolts:

The standard answer places a TL431 shunt reference on the secondary, which does the error amplification and compensation, and drives an optocoupler LED whose transistor pulls on the primary controller's feedback pin.

The first difficulty is gain tolerance. An optocoupler's current transfer ratio — output current per input current — is specified over an enormous range:

Twelve decibels is a factor of four in crossover frequency. And it is worse than a tolerance: CTR falls with age and temperature, so a supply that is fast when new becomes slow after a few thousand hours — a well-known failure mode in which the transient response degrades without anything appearing to break.

How the design must accommodate it. The loop must be stable at maximum CTR and adequate at minimum:

So the design point is squeezed from both ends: stability is checked at one extreme and performance at the other, and the nominal design has to leave margin for both. In practice this costs about half the bandwidth that would otherwise be achievable.

The second difficulty is the optocoupler's own pole. The output transistor's collector capacitance works against the pull-up resistor:

Which caps the loop at a few kilohertz — roughly a sixth of the 20 kHz the non-isolated buck of Problem 2 achieved. Combined with the 12 dB of tolerance, an isolated supply is typically five to ten times slower than an equivalent non-isolated one.

What can be done about the pole:

Reducing the pull-up to 200 Ω moves the pole to 53 kHz but needs five times the LED current and gives a fifth of the gain, which the TL431 must then make up. A worthwhile trade in a fast supply and unnecessary in a slow one.

The alternatives:

Primary-side regulation, in which the controller infers the output from the flyback voltage on an auxiliary winding, eliminates the optocoupler entirely — and gives up tight regulation in return. It dominates the low-cost charger market for exactly that reason: a phone charger does not need ±1%.

The total loss allowance:

Five and a half watts to distribute across every component. That is the entire design constraint, and every choice in the adapter is a claim on part of it.

Allocate it, worst case at 90 V AC:

No single term dominates, which is the signature of a well-balanced design — and also of a design that is hard to improve, since halving any one term buys under 2% of the total. The adapter that reaches 94% does so by improving four things at once.

The input bridge is worth a second look. At low line the input current is high and the power factor is poor:

A capacitor-input rectifier at 65 W is just below the 75 W threshold where Set 10 concluded that PFC becomes mandatory — which is exactly why 65 W is such a common adapter rating. A watt of bridge loss is the price of not fitting the boost stage of Set 19.

Now the no-load requirement, which is a different problem entirely:

At no load the conduction terms vanish but the fixed ones do not:

All three are proportional to switching frequency — the same observation as Set 2, Problem 4. Running at 65 kHz with no load would burn well over a watt in switching alone, fifteen times the budget.

The answer is to switch less often. Burst mode delivers a short train of pulses and then sleeps:

The last row is one many designers miss. Safety standards require the X capacitor to discharge within a second of unplugging, and a permanent bleeder resistor doing that job burns 30 mW continuously — 40% of the entire no-load budget. Active discharge circuits that detect the unplug event exist purely to reclaim it.

The two operating points are almost different products:

A modern controller detects the load and reconfigures itself between them. The transition must be smooth in both directions, and handling it badly produces audible noise as the burst frequency passes through the acoustic range — the characteristic whine of a cheap adapter with nothing plugged in.