MOSFET and IGBT Losses and Gate-Drive Design

Why the plateau exists. Once the channel is carrying the full load current, further gate charge does not raise \(V_{gs}\) — it goes instead into the gate-drain capacitance as the drain voltage collapses. The gate sits at whatever \(V_{gs}\) supports the load current, and the drive current is diverted entirely into moving \(Q_{gd}\).

So the flat region of the gate-charge curve is not a pause; it is the whole voltage transition, and therefore where nearly all the switching loss occurs.

Turn-on drive current. The driver pushes against the plateau voltage through both resistances:

Turn-off is faster, and the reason is worth seeing. The driver is now at 0 V, so the voltage available to pull charge out is the plateau voltage itself:

Turn-off is 1.5 times faster than turn-on with the same resistor, because 6 V drives it rather than 4 V. This asymmetry is usually welcome — fast turn-off reduces loss — but it also means the device turns off before its complement is ready, which is what Problem 6's dead-time calculation has to accommodate.

Gate-drive power. Every cycle the full \(Q_g\) is moved from 0 to 10 V and back:

All of it dissipated — half in the driver's own output stage and half split between \(R_{g,ext}\) and the die's internal gate resistance. Note that it does not depend on \(R_g\) at all: a larger resistor makes switching slower without making the gate drive cheaper.

Average driver current, which is what the driver's supply must provide:

Twelve milliamps average, from a driver that must deliver 857 mA peak — a crest factor of 70. Gate drivers are specified by peak current for this reason, and the bypass capacitor next to the driver, not the supply, is what actually delivers those peaks.

Turn-on energy, with the current rise and the Miller voltage fall in series:

Turn-off energy, with the faster Miller time from Problem 1:

Compare with the 0.12 W of gate-drive power in Problem 1. The gate circuit spends a tenth of a watt to control forty — which is the entire point of a voltage-controlled device, and also why the gate circuit deserves careful design.

Now reduce the gate resistor. Every transition time is inversely proportional to the drive current, hence proportional to the total gate resistance:

A saving of 23.6 W from changing one resistor — and note that the internal \(2\ \Omega\) puts a floor on this. Even \(R_{g,ext} = 0\) would only reach \(2/7\) of the original, so the die itself limits how fast it can be driven.

What the speed costs. The Miller time is now \(35 \times 3/7 = 15\) ns, and the drain voltage covers the full link in that time:

Compare a thyristor's 200 V/µs rating from Set 4 — more than a hundred times slower. This is why the constraints that limit a fast MOSFET have nothing to do with the device itself.

The four things that \(dv/dt\) breaks:

None of these appear in the loss calculation, and all of them worsen as \(R_g\) falls. This is why a production design almost never uses the smallest gate resistor that works: the 23.6 W is real, and so is failing an EMC test.

The mechanism. The rising drain voltage of the off device drives a displacement current through \(C_{gd}\) into the gate node. The driver tries to sink it, but only through the gate-loop resistance, so a voltage develops:

Substitute:

Against a 4 V threshold at room temperature — a margin of 1 V, or 25%. That sounds survivable.

Now apply temperature. Threshold voltage falls with junction temperature at roughly −10 mV/°C:

The margin is gone entirely. The device will begin to conduct while its complement is already on, producing a shoot-through pulse limited only by the two channel resistances — and, being a partial turn-on, it happens in the linear region where the dissipation is at its worst.

The failure mode is self-reinforcing, which is what makes it dangerous. Shoot-through heats the die, a hotter die has a lower threshold, a lower threshold means more shoot-through. A converter that passes at 25 °C on the bench can fail an hour into a thermal soak.

It is also nearly invisible on an oscilloscope: probing the gate adds capacitance that damps the very effect being measured.

Remedy 1 — lower the gate-loop resistance. The induced voltage is directly proportional to it:

Effective, but it fights Problem 2: a lower turn-off resistance raises the \(dv/dt\) that the other device imposes. The two constraints are coupled around the bridge.

Remedy 2 — negative gate bias. Holding the off state at \(-5\) V instead of 0 V moves the starting point, not the excursion:

Margin of 5 V at any temperature, and no effect on switching speed. This is why IGBT and SiC drivers almost universally supply a negative off-state rail, and why it matters more as devices get faster.

The bounding case, for perspective. If the gate were left genuinely open, \(C_{gd}\) and \(C_{gs}\) would form a plain capacitive divider across the link:

Nearly ten volts — a hard turn-on. The driver's job in the off state is not to do nothing; it is to hold the gate down hard against exactly this divider, and the \(3\ \Omega\) is how well it manages.

Interval 1 — voltage rise at full current. The clamped inductive load holds the current at 100 A while the voltage ramps up, so the average product is half the peak:

Interval 2 — fast current fall at full voltage. The current falls linearly from 100 to 10 A, averaging 55 A:

Interval 3 — the tail. Only 10 A decaying to zero, averaging 5 A, but for five times as long and still at the full 600 V:

The tail's share:

Nineteen per cent of the turn-off loss from ten per cent of the current. The reason is purely that \(v\) is at its maximum for the whole of it — energy is the product, and a small current at 600 V for 500 ns beats a large one at a falling voltage.

Why the gate cannot fix it. An IGBT is a MOSFET driving a bipolar transistor. Removing the gate charge switches off the MOSFET part, which stops the base drive — but the minority carriers already injected into the drift region have to recombine, and no terminal has any access to them:

Reduce \(R_g\) to zero and intervals 1 and 2 shorten; interval 3 does not move. That is the structural difference from Problem 2, where every time scaled together.

The loss at frequency:

At only 5 kHz, from turn-off alone. Doubling to 10 kHz costs another 39 W with no benefit except a smaller filter. This is the ceiling that keeps IGBTs at a few kilohertz while the MOSFETs of Problem 2 run at hundreds — and the tail is why carrier-lifetime control, not gate drive, is where IGBT manufacturers spend their effort.

Conduction, MOSFET. A channel is a resistor, so it needs the mean square current, and it must be evaluated hot:

Conduction, IGBT. A saturated junction holds a roughly fixed voltage, so it needs the average:

The IGBT wins on conduction by 22 W, and the gap widens with current: the MOSFET term grows as \(I^2\) while the IGBT's grows as \(I\). At 60 A the MOSFET would dissipate 202 W against the IGBT's 57 W.

Switching, both:

A factor of 7.5 — almost all of it the tail current of Problem 4, which the SiC MOSFET does not have because it is a majority-carrier device.

Totals at the two frequencies:

The winner reverses between the two columns. At 1 kHz the IGBT dissipates a third less; at 20 kHz it dissipates more than twice as much.

The break-even frequency:

Which is a remarkably good description of where the industry actually divides. Motor drives and traction inverters, switching at 2 to 4 kHz, use IGBTs; solar inverters, on-board chargers and switch-mode supplies, switching at 20 to 100 kHz, have moved to SiC.

What shifts the crossover. The break-even is \(\Delta P_{cond}/\Delta E_{sw}\), so:

The last row matters most in practice. A drive that spends its life at 30% load has a conduction term nine times smaller, moving the crossover down towards a few hundred hertz — which is why the comparison must be made at the real duty cycle, not at nameplate rating.

Start from the \(dv/dt\) budget, since Problems 2 and 3 showed that is the binding constraint rather than loss:

Then the resistor follows:

Note that this design flow runs backwards from the constraint to the component. Picking \(R_g\) for minimum loss and checking \(dv/dt\) afterwards is the same calculation done in the order that produces rework.

Dead time. The outgoing device must be fully off before the incoming one starts, in the worst combination of tolerances:

Too little dead time gives shoot-through; too much gives body-diode conduction and, in a motor drive, output voltage distortion. The 43% margin here is normal.

What the dead time costs. During each of the two dead intervals per cycle, the load current freewheels through a body diode:

Small here, but it scales with \(f_s\) and with dead time. At 500 kHz with the same 100 ns it would be 2 W, which is why high-frequency designs invest in adaptive dead time that shrinks to the actual, rather than worst-case, delay.

The bootstrap capacitor must supply everything the high side consumes during one on-time, with only a small droop:

A factor of 7.6 of margin, which is standard practice: the bootstrap must also survive start-up, and it can only recharge while the low-side device is on, so a converter approaching 100% duty ratio starves it. That is the failure mode behind most "works at low duty, fails at high duty" bridge faults.

Total driver power, for both devices:

The design, assembled: