Chapter 5: Power BJT, MOSFET, IGBT, and Gate Drive Circuits — Power Electronics

Where this sits

Part 1 · Power Semiconductor Devices
Chapter 5 of 30 — the last device chapter

You should already know

Conduction and switching loss (Ch. 1), reverse recovery (Ch. 2), and why commutation was expensive (Ch. 4).

By the end you can

Choose between MOSFET and IGBT for a given current and frequency, compute total device loss, and design a gate drive.

Time

≈ 70 min reading · ≈ 60 min problems

i What you'll learn

What makes a device self-commutating, and how the three families divide the power–frequency plane between them.
The power BJT — current-driven, limited by \(\beta\), quasi-saturation and second breakdown, and why it is now historical.
The power MOSFET — \(R_{DS(on)}\), the intrinsic body diode, gate charge \(Q_G\), and the positive temperature coefficient that makes paralleling easy.
The IGBT — a MOS gate driving a bipolar output, its \(V_{CE(sat)}\), the tail current, and the latch-up mechanism behind it.
How to compute switching loss from datasheet energies: \( P_{sw} = (E_{on}+E_{off})f_s \).
Gate drive design — peak current from \(R_G\), drive power \(Q_GV_{GS}f_s\), negative bias, dead time, bootstrap supplies and desaturation protection.
Reading the safe operating area and closing the thermal chain to find \(T_j\).

Section 5-1

The Self-Commutating Switch

A fully controlled or self-commutating device turns off when its control terminal says so, with no help from the external circuit. That single property removes the commutation capacitor, the auxiliary thyristor, the resonant inductor and the associated losses — and with them, the frequency ceiling those components imposed. Everything in Parts 3 and 4 of this book, from choppers to PWM inverters, exists because these devices exist.

Three families matter. The power BJT came first and is now largely obsolete, but it explains the vocabulary the others inherited. The power MOSFET is a voltage-controlled majority-carrier device: extremely fast, easy to parallel, but its on-resistance grows steeply with rated voltage, which confines it to lower voltages. The IGBT grafts a MOSFET gate onto a bipolar output stage, keeping the easy drive while gaining the low conduction drop of minority-carrier injection — and it now occupies most of the middle of the power spectrum.

Each device owns a region — and SiC and GaN are moving the borders

→Why this one property changed the whole industry

Chapter 4 spent half its length on commutation circuits: a capacitor rated for full load current, usually an inductor, often an extra thyristor and diode, plus the losses and the frequency ceiling they imposed.

A self-commutating device deletes all of it. Not reduces — deletes. And the consequences cascade:

No commutation capacitor → no recharge interval → switching frequency can rise by two or three orders of magnitude.
Higher frequency → inductors and transformers shrink roughly as \(1/f_s\) → the converter becomes small enough to sit in a phone charger or a car.
Higher frequency also means the control loop can be fast, so output regulation and dynamic response improve.
Fewer components → fewer failure modes, lower cost, lighter weight.

Everything in Parts 3 and 4 of this book — every chopper, every PWM inverter, every SMPS — exists because a device arrived that could turn itself off. The thyristor did not become bad; it simply stopped being the only option.

Section recap. A self-commutating device turns off on command, removing the commutation hardware and the frequency ceiling it imposed. Three families divide the power–frequency plane: BJT (historical), MOSFET (low voltage, high frequency), IGBT (mid range).

Section 5-2

The Power BJT

◇Intuition · why "current-controlled" was fatal

Put a number on it and the commercial verdict is obvious.

A power BJT switching 100 A with \(\beta = 10\) needs 10 A of base current, continuously, for the entire conduction interval. Not at the transitions — throughout.

That base drive is itself a 10 A power supply. It needs its own heatsink, its own isolated source, its own protection.
Compare a MOSFET or IGBT gate: it is a capacitor. Steady-state current is zero, and the only energy cost is charging it at each transition — typically a fraction of a watt.

The analogy: a BJT is a tap you must keep pushing to hold open, and it pushes back hard. A MOS gate is a switch that clicks — it takes a small effort to change state, and none at all to stay there.

The BJT survives in this book for one reason: its vocabulary — saturation, storage time, second breakdown, safe operating area — was inherited wholesale by the IGBT. Learn the words here and they carry forward.

The power bipolar transistor is a current-controlled device: collector current flows only while base current is supplied, in the ratio \(I_C = \beta I_B\). For power devices \(\beta\) is small — often 5 to 20 — so switching 100 A demands a continuous base current of 5 to 20 A. That drive circuit is itself a substantial power converter, and it must supply current for the whole conduction interval, not just at the transitions.

Two further problems finished the device commercially. Quasi-saturation means that driving the base harder does not immediately reduce \(V_{CE}\), because the lightly doped collector drift region takes time to flood with carriers — and having flooded it, the stored charge must be removed again at turn-off, giving a long storage time of several microseconds. Worse, the BJT suffers second breakdown: local current filamentation creates a hot spot that draws yet more current, destroying the device at voltages and currents well inside its nominal ratings. Avoiding it forces a restrictive reverse-bias safe operating area and, usually, a snubber.

The Darlington configuration raises the effective gain to several hundred by cascading two transistors, but it adds a diode drop to \(V_{CE(sat)}\) and slows switching further. Power BJTs and Darlingtons appear in this book mainly because their vocabulary — saturation, storage time, second breakdown, SOA — carries directly into the IGBT.

Section recap. The BJT is current-driven with a low \(\beta\), so its base drive is itself a power converter. Quasi-saturation gives long storage times and second breakdown restricts its safe operating area. Commercially obsolete — but its vocabulary is the IGBT's.

Section 5-3

The Power MOSFET

The power MOSFET is built vertically: current flows from a source metallisation on the top surface, through a channel induced under the gate oxide, down through a lightly doped \(n^{-}\) drift region that holds off the blocking voltage, and out through the drain on the underside. It is a majority-carrier device — no minority-carrier injection, therefore no stored charge, therefore no reverse recovery and no tail current. That is the root of its speed.

Vertical DMOS — the drift region blocks the voltage and sets the on-resistance

→Why majority-carrier conduction makes it fast

This is the single sentence the whole section hangs on. In a MOSFET, current is carried only by majority carriers — electrons in an n-channel device drifting through the channel and the drift region.

There is no minority-carrier injection. Therefore:

No stored charge in the drift region. Compare the diode's "soaked sponge" in Chapter 2 — there is nothing to wring out here.
No reverse recovery in the channel, and no tail current at turn-off.
Turn-off is over as soon as the gate capacitance is discharged — nanoseconds, not microseconds.

But nothing is free. Conductivity modulation is exactly what let the diode and the IGBT achieve a low drop across a lightly doped, high-voltage drift region. Without it, the MOSFET's drift region is simply a resistor — and that resistor is the price of its speed. Hence the next paragraph.

Four properties follow from that structure, and they define how the device is used.

On-resistance. In conduction the MOSFET behaves as a pure resistance \(R_{DS(on)}\), so its drop falls to zero at zero current — an advantage the IGBT does not share at light load. But \(R_{DS(on)}\) scales roughly as \(V_{BR}^{2.5}\), so a 600 V device has vastly more resistance than a 100 V one of the same die area. This single scaling law is why silicon MOSFETs rarely compete above a few hundred volts.

Positive temperature coefficient. \(R_{DS(on)}\) typically doubles between 25 °C and 125 °C. That is a nuisance for loss calculations — always use the hot value — but a gift for reliability: a device that starts hogging current heats up, its resistance rises, and it sheds current to its neighbours. MOSFETs therefore parallel naturally, without the sharing resistors that diodes and thyristors need.

The body diode. The p-body and \(n^{-}\) drift form an unavoidable diode from source to drain. It is free — inverter legs need an antiparallel diode anyway — but it is a slow minority-carrier diode with substantial \(Q_{rr}\), so in hard-switched bridges it is often paralleled with a faster external device or avoided by the choice of topology.

Gate charge. The gate is a capacitor, so steady-state drive power is zero; all the drive energy goes into charging and discharging \(Q_G\) at each transition. This is the key number for drive design, and Section 5-6 turns it into watts.

!Common mistake

Using the datasheet's headline \(R_{DS(on)}\) in a loss calculation.

Wrong "The datasheet says 25 mΩ, so \(P = I^2(0.025)D\)."

Right The headline figure is at 25 °C. In service the junction sits at 100–125 °C, where \(R_{DS(on)}\) has roughly doubled.

Use the hot value and your conduction loss doubles — which changes the heatsink, which changes the enclosure. Designers who skip this find their prototype fine on the bench and thermally unstable in a hot cabinet.

Worse, it is a feedback loop: more loss → hotter → higher \(R_{DS(on)}\) → more loss. It settles at a stable point (unlike bipolar thermal runaway) but well above the naive prediction. The professional habit is to iterate once: assume \(T_j\), compute loss, compute the resulting \(T_j\), and repeat if the two disagree.

◇Intuition · the positive coefficient is a safety feature

That same temperature sensitivity is a nuisance for arithmetic and a gift for reliability — and the contrast with earlier devices is instructive:

Diode / BJT / IGBT — negative coefficient Hotter → lower drop → takes more current → hotter still. Runaway. Paralleling needs sharing resistors or matched modules.

MOSFET — positive coefficient Hotter → higher resistance → sheds current to its neighbours → cools. Self-correcting. Paralleling needs nothing at all.

Two devices in parallel, one running slightly hotter: in the first case the imbalance grows, in the second it shrinks. That is the difference between a positive and a negative feedback loop, and it is why you can simply bolt four MOSFETs side by side to get four times the current — a freedom Chapter 2 showed you never had with diodes.

Section recap. The MOSFET is a majority-carrier device: no stored charge, so no recovery and no tail — hence its speed. The price is a drift-region resistance scaling as \(V_{BR}^{2.5}\), which caps it near a few hundred volts. Its positive temperature coefficient makes paralleling trivial; its body diode is free but slow.

Section 5-4

The IGBT

The insulated gate bipolar transistor is the deliberate hybrid. Add a \(p^{+}\) layer to the drain side of a power MOSFET and that layer injects minority carriers into the drift region during conduction — conductivity modulation, which floods the high-resistance drift region with carriers and collapses its resistance. The result keeps the MOSFET's voltage-driven, near-zero-power gate while achieving a conduction drop of 1.5–2.5 V almost independent of the blocking voltage rating.

A MOS gate driving a bipolar output — plus a parasitic thyristor nobody wants

◇Intuition · a resistor versus a diode

If you remember one thing from this chapter, make it this. The two devices drop voltage in fundamentally different shapes:

MOSFET — behaves like a resistor \(V_{DS} = I\,R_{DS(on)}\). The drop is proportional to current, so it goes to zero at zero current — but it grows without limit as current rises.

IGBT — behaves like a diode plus a small resistor \(V_{CE} \approx V_{CE0} + I\,r\). There is a fixed offset of 1–2 V you pay even at tiny currents — but the slope beyond it is gentle.

Two straight lines with different intercepts and slopes must cross. Below the crossing the MOSFET wins; above it, the IGBT does. That crossing point — not brand loyalty or fashion — is what decides which device a converter uses.

Add switching loss and a second axis appears: the IGBT's tail current makes \(E_{off}\) large, so raising frequency pushes the decision back toward the MOSFET. The explorer below lets you find both boundaries yourself.

The hybrid inherits both parents' weaknesses. Because conduction now involves stored minority charge, turn-off is not clean: when the gate removes the MOSFET channel, the PNP section continues to conduct until its stored carriers recombine, producing the characteristic tail current — a slow decay of collector current at full collector voltage, and therefore a large contribution to \(E_{off}\). The tail is the main reason IGBTs are used below about 20–30 kHz while MOSFETs run at hundreds of kilohertz.

Look again at the equivalent circuit and notice the parasitic NPN drawn beside the PNP. Together they form exactly the four-layer regenerative structure of Chapter 3 — a parasitic thyristor. If enough current flows laterally through the body resistance to forward-bias that NPN, the pair latches and the gate loses control, precisely as in an SCR. Modern devices suppress this with heavy body doping and cell geometry, and the datasheet's maximum collector current is set partly by that latch-up threshold. A second consequence of the bipolar output is a negative temperature coefficient of \(V_{CE(sat)}\) at low current, so IGBTs — unlike MOSFETs — do not parallel themselves gracefully and are usually supplied as matched modules.

!Common mistake

"The IGBT's turn-off is finished when the gate voltage reaches zero."

The MOSFET half turns off in nanoseconds. The bipolar half does not get the message.

Removing the gate voltage collapses the MOS channel, so the electron current stops abruptly.
But the drift region is still flooded with minority carriers injected by the \(p^{+}\) collector layer — the same conductivity modulation that gave the low on-state drop.
There is no terminal connected to that region, so those carriers can only recombine in their own time. Nothing external can hurry them.
Meanwhile the collector voltage has already risen to the full rail. So you have a slowly decaying current at maximum voltage: the tail current.

The tail can last a microsecond and often contributes more to \(E_{off}\) than the nominal fall time does. It is the whole reason IGBTs are used below roughly 20–30 kHz while MOSFETs run at hundreds of kilohertz.

Notice the symmetry with Chapter 2: the diode's reverse recovery and the IGBT's tail current are the same physical phenomenon — stored minority charge that must recombine. Conductivity modulation gives a low conduction drop and charges for it at turn-off. That bargain appears everywhere in power semiconductors.

Property	Power BJT	Power MOSFET	IGBT	Thyristor (SCR)
Control	Current, continuous	Voltage, capacitive	Voltage, capacitive	Current pulse (on only)
Drive power	High	Very low	Very low	Low (pulse)
Turn-off	Commanded	Commanded	Commanded	Circuit only
On-state	\(V_{CE(sat)}\approx 1\!-\!2\) V	\(I\,R_{DS(on)}\)	\(V_{CE(sat)}\approx 1.5\!-\!2.5\) V	\(\approx 1\!-\!1.5\) V
Temp. coefficient	Negative	Positive — parallels easily	Mixed/negative	Negative
Typical \(f_s\)	Up to 5 kHz	50 kHz – 1 MHz	2 – 30 kHz	50 Hz – 1 kHz
Typical range	To 1 kV, 500 A	To 600 V, 200 A	To 6.5 kV, 3 kA	To 8 kV, 6 kA
Status	Obsolete	Dominant at low voltage	Dominant in mid range	Very high power only

Interactive · MOSFET or IGBT?

Two representative 600 V devices in a hard-switched leg at \(D = 0.5\). Move the load current and the switching frequency, and watch which device wins. These are illustrative figures chosen to show the shape of the trade-off, not a specific manufacturer's parts — but the behaviour is exactly what real datasheets give you.

Load current 30 A

Frequency \(f_s\) 20 kHz

MOSFET total—

IGBT total—

Winner—

Margin—

—

⚙What the explorer is telling you

Try these four settings and you will have reproduced most real-world device choices:

Try	Regime	Real example
10 A, 100 kHz	Low current, high frequency → MOSFET	Laptop adapter, server PSU, PFC front end
100 A, 5 kHz	High current, low frequency → IGBT	Industrial motor drive, welding inverter
60 A, 20 kHz	Near the crossover — genuinely contested	EV traction inverter, solar string inverter
100 A, 100 kHz	Both are bad	The gap SiC and GaN were invented to fill

That last row is the important one. When both silicon devices give unacceptable loss, the answer is not a cleverer circuit but a different semiconductor — which is exactly why wide-bandgap devices arrived where they did.

Section recap. The IGBT is a MOS gate on a bipolar output: easy to drive, low conduction drop almost independent of voltage rating, but burdened with a tail current at turn-off and a parasitic thyristor that sets its current limit. MOSFET drop rises with current; IGBT drop starts at an offset. They always cross.

Section 5-5

Switching Transitions and Losses

Chapter 1 established that an ideal switch is lossless because \(v\) and \(i\) are never simultaneously non-zero. A real transition violates that for a few tens or hundreds of nanoseconds, and the overlap is where switching energy is lost. In a hard-switched clamped-inductive circuit — the standard case, and the one datasheets measure — the two transitions are asymmetric.

The shaded overlap is the switching energy — and it is paid every cycle

At turn-on, the freewheeling diode cannot stop conducting until the switch has taken over the full load current, so the current rises to \(I_o\) while the voltage is still high, and only then does the voltage fall. The diode's reverse recovery current from Chapter 2 rides on top, which is why \(E_{on}\) is usually the larger of the two energies. At turn-off the order reverses: the voltage must rise to the rail before the diode can pick up the current, so the current falls at full voltage — and for an IGBT the tail current extends that overlap well beyond the nominal fall time.

🔑

Total device loss — the equation that sizes every heatsink in Parts 3 and 4

\[ P_{tot} = \underbrace{V_{CE(sat)}I_C D}_{\text{conduction (IGBT)}} \ \ \text{or}\ \ \underbrace{I^2R_{DS(on)}D}_{\text{conduction (MOSFET)}} \ +\ \underbrace{(E_{on}+E_{off})\,f_s}_{\text{switching}} \]

Datasheets quote \(E_{on}\) and \(E_{off}\) in millijoules at a stated voltage, current, temperature and gate resistance — scale roughly linearly with voltage and current, and re-check at the actual \(R_G\). Because the switching term is proportional to \(f_s\) and the conduction term is not, the two always cross somewhere, and that crossing sets the practical frequency limit for a given device.

!Common mistake

"I'll compute switching loss from \(t_r\) and \(t_f\) using \(P = \tfrac12 VI(t_r+t_f)f_s\)."

That formula from Chapter 1 is a teaching tool for showing proportionality. It is not how a real loss budget is built, and it under-predicts badly. It omits:

Diode reverse-recovery current riding on top of turn-on — often the single largest contributor to \(E_{on}\).
The IGBT tail current, which extends the turn-off overlap far beyond \(t_f\).
Output capacitance charge and discharge.
The fact that transitions are not linear ramps.

Use \(E_{on}\) and \(E_{off}\) from the datasheet instead. They are measured on a real clamped-inductive test circuit and include all of the above. Then check the four conditions they were measured at — voltage, current, junction temperature and gate resistance — and scale: roughly linearly with voltage and current, upward with temperature, and re-check if your \(R_G\) differs from theirs.

The rule of thumb worth carrying: use the physics formula to understand which way a change moves the loss; use datasheet energies to find out by how much.

Section recap. Turn-on and turn-off are asymmetric: at turn-on the current rises before the voltage falls (plus diode recovery); at turn-off the voltage rises before the current falls (plus the IGBT tail). Total loss is conduction plus \((E_{on}+E_{off})f_s\), and the two terms cross at the device's practical frequency limit.

Section 5-6

Gate Drive Design

A MOS gate draws no steady current, which tempts beginners into driving it from a logic pin. It is a capacitor of several nanofarads that must be charged and discharged in tens of nanoseconds — a peak current of amperes. The gate driver is a small, very fast power amplifier, and the quality of the switching waveform above is decided almost entirely by it.

Split gate resistors, and a bootstrap supply for the floating high-side device

🔑

The three numbers a gate driver must deliver

\[ I_{G(peak)} = \frac{V_{drive} - V_{plateau}}{R_G}, \qquad t_{sw} \approx \frac{Q_{GD}}{I_{G(peak)}}, \qquad P_{drive} = Q_G\,V_{GS}\,f_s \]

The gate resistor is the master control: it sets the peak current, hence the transition time, hence \(E_{on}\) and \(E_{off}\). Halving \(R_G\) roughly halves the switching loss — and roughly doubles the \(dv/dt\) and the EMI. That trade-off is the reason \(R_{on}\) and \(R_{off}\) are usually split, so turn-on can be slowed for EMI while turn-off stays fast for efficiency.

◇Intuition · \(R_G\) is the one knob that trades efficiency for EMI

Almost every gate-drive decision comes back to a single resistor, and it pulls two things in opposite directions:

Small \(R_G\) — fast Large peak gate current → short transition → low switching loss.
But: high \(dv/dt\) and \(di/dt\) → more EMI, more ringing, more stress on the opposite device, higher risk of \(dv/dt\)-induced false turn-on.

Large \(R_G\) — slow Gentle edges → quiet, well-behaved converter, easier EMC compliance.
But: long transitions → high switching loss → bigger heatsink, lower usable frequency.

The professional resolution is to stop treating it as one knob. Split it: a diode lets turn-on and turn-off see different resistors.

Turn-on slow (larger \(R_{on}\)) — turn-on is where diode reverse recovery generates the worst EMI, so slowing it buys a lot of quiet for a little loss.
Turn-off fast (smaller \(R_{off}\)) — turn-off is where the IGBT tail already costs you, and a fast pull-down also holds the gate firmly against \(dv/dt\) coupling.

Two components, and a design that would otherwise be an unhappy compromise becomes two good decisions.

1 Adequate drive voltage

15 V is standard for IGBTs and 10–12 V for MOSFETs. Under-driving leaves the device partly on — a linear resistor dissipating enormous power, the exact failure Chapter 1 warned against.

2 Low impedance and high peak current

Amperes for tens of nanoseconds. The driver must sit physically close to the device, with a tight gate loop, or the loop inductance will ring against the gate capacitance.

3 Negative off-state bias

Holding the gate at −5 to −8 V rather than 0 V prevents the \(dv/dt\) of the opposite device from coupling through \(C_{GD}\) and falsely turning this one on — the MOS version of the \(dv/dt\) problem of Chapter 3.

4 Dead time

In a bridge leg, both devices must be off for a brief interval between transitions. Too little and both conduct — shoot-through, a supply-to-ground short. Too much and the output waveform distorts.

5 Isolation and floating supply

The high-side emitter swings the full DC-link voltage every cycle. Its drive needs an isolated supply — a bootstrap capacitor recharged each time the low-side device conducts, or a separate isolated converter for full duty-cycle capability.

6 Protection

Desaturation detection watches \(V_{CE}\) while the device is on; an abnormally high value means a short circuit, and the driver responds with a soft turn-off to avoid a destructive \(L\,di/dt\) spike. Undervoltage lockout guards against partial drive.

!Common mistake

"The gate draws no current, so I can drive it straight from a microcontroller pin."

It draws no steady current. It is a capacitor of several nanofarads that must be charged in tens of nanoseconds — and \(i = C\,dv/dt\) does the rest of the argument for you.

Charging 5 nF to 15 V in 50 ns needs a peak current of \(I = C\Delta V/\Delta t = (5\times10^{-9})(15)/(50\times10^{-9}) = \) 1.5 A. A microcontroller pin supplies perhaps 20 mA.

What actually happens is worse than "it switches slowly". The device crawls through its linear region for microseconds on every transition, dissipating enormous power — precisely the linear-regulator failure Chapter 1 opened with. A 100 A IGBT driven from a logic pin will destroy itself in seconds, and the failure looks baffling because the circuit topology is perfectly correct.

Two more rules that follow from the same physics:

Put the driver physically next to the device. Gate-loop inductance rings against gate capacitance; a long gate lead turns a clean edge into an oscillation.
Use a negative off-state bias (−5 to −8 V) on IGBTs. Holding the gate at 0 V leaves it vulnerable to \(dv/dt\) coupling through \(C_{GD}\) when the opposite device switches — the MOS version of the Chapter 3 problem, and a cause of shoot-through that no amount of dead time will fix.

⚙Dead time: the cost of not trusting your components

In a bridge leg, the upper and lower devices must never conduct together — that is a direct short across the DC link, and it destroys both devices in microseconds. So the controller inserts dead time: a brief interval in which both gates are off.

It is pure insurance, and like all insurance it has a premium:

Too little dead time → shoot-through. Catastrophic, immediate.
Too much dead time → during that interval neither device controls the output; the load current freewheels through whichever diode it finds, so the actual output pulse width differs from the commanded one. This is dead-time distortion, and it introduces low-order harmonics into an inverter output that the modulation strategy never asked for.

Typical values are 1–3 µs for IGBTs and a few hundred nanoseconds for MOSFETs — set by the device's turn-off delay including the tail, plus driver propagation-delay mismatch, plus a margin.

This is why Chapter 18 spends time on dead-time compensation: the drive's control software deliberately lengthens or shortens pulses to cancel a distortion caused by a safety measure in the gate driver. Layers of a real system correcting for one another is entirely normal engineering.

Section recap. A gate driver is a small, very fast power amplifier: amperes of peak current for tens of nanoseconds, sited close to the device. \(R_G\) trades switching loss against EMI, and splitting it resolves the conflict. Drive power is \(Q_GV_{GS}f_s\). Negative bias, dead time, a bootstrap or isolated supply, and desaturation protection are all mandatory in a bridge leg.

Section 5-7

Safe Operating Area and Thermal Design

The safe operating area is the region of the \(v\!-\!i\) plane in which the device may operate without destruction, bounded by the current limit, the voltage limit, and a power-dissipation line that moves outward for shorter pulses. The forward-bias SOA applies during conduction and turn-on; the reverse-bias SOA applies during turn-off, when voltage and current are simultaneously large and the device is at its most vulnerable. A third, the short-circuit SOA, states how long an IGBT can survive a full-voltage fault — typically 10 µs, which is precisely the budget a desaturation protection circuit must work within.

Whatever the device, the thermal chain of Chapter 2 closes the design. Total loss flows through junction, case, interface and heatsink to ambient, and the accumulated temperature rise must leave \(T_j\) inside its rating with margin:

The thermal chain

\[ T_j = T_a + P_{tot}\left(R_{th(j-c)} + R_{th(c-s)} + R_{th(s-a)}\right) \]

→Why there are three different SOAs

They are not three versions of the same limit — they describe three genuinely different stresses:

SOA	Applies during	Why it is separate
Forward-bias	Conduction and turn-on	The gate is on and the device is controlling current. Limited by steady dissipation and by second breakdown in bipolar devices.
Reverse-bias	Turn-off	Voltage is rising toward the rail while current is still falling. The most vulnerable moment in the whole cycle, and the reason snubbers exist.
Short-circuit	A fault	Full rail voltage and many times rated current, simultaneously. Survivable for roughly 10 µs — and that is a hard budget, not a guideline.

That 10 µs is the specification the desaturation circuit is designed against. Work through the budget: detect the fault (a few hundred nanoseconds of blanking so normal turn-on is not mistaken for a fault), decide, then turn off softly — because turning off a fault current of several hundred amperes at full \(di/dt\) would generate an \(L\,di/dt\) spike that destroys the device just as surely as the fault would.

So a protection circuit must be fast enough to act inside 10 µs and gentle enough not to become the failure itself. That tension is what makes IGBT gate drivers a specialist product rather than a couple of transistors.

Design the heatsink backwards. The device rating fixes \(T_{j(max)}\), the environment fixes \(T_a\), and the circuit fixes \(P_{tot}\) — so the only free variable is \(R_{th(s-a)}\), and it is found by subtraction: \(R_{th(s-a)} = (T_{j(max)} - T_a)/P_{tot} - R_{th(j-c)} - R_{th(c-s)}\). Derate \(T_{j(max)}\) to about 80% of the rated value first; junction temperature is the single strongest determinant of semiconductor lifetime, and a device run at 125 °C will fail years before an identical one held at 100 °C.

Section recap. Three SOAs describe three stresses: forward-bias during conduction, reverse-bias during turn-off, short-circuit during a fault (about 10 µs — the desaturation budget). Then the thermal chain closes the design, and the only free variable is the heatsink: \(R_{th(s-a)} = (T_{j(max)}-T_a)/P_{tot} - R_{th(j-c)} - R_{th(c-s)}\).

Section 5-8

Worked Examples

1 MOSFET or IGBT? Find the crossover current

Problem. A MOSFET has \(R_{DS(on)} = 25\) mΩ at 25 °C, doubling at 125 °C. An IGBT has \(V_{CE(sat)} = 1.7\) V plus a slope resistance of 10 mΩ. At \(D = 0.5\), compare conduction losses at 5 A and 20 A, and find the current at which they are equal.

Solution. Use the hot value \(R_{DS(on)} = 50\) mΩ.

Working

\[ \text{At } 5\ \text{A}: \quad P_{FET} = (25)(0.05)(0.5) = 0.63\ \text{W}, \quad P_{IGBT} = \left[(1.7)(5) + (0.01)(25)\right](0.5) = 4.4\ \text{W} \]

\[ \text{At } 20\ \text{A}: \quad P_{FET} = (400)(0.05)(0.5) = 10\ \text{W}, \quad P_{IGBT} = \left[34 + 4\right](0.5) = 19\ \text{W} \]

\[ \text{Equal when } I R_{DS(on)} = V_{CE(sat)} + I r \;\Rightarrow\; I = \frac{1.7}{0.05 - 0.01} = 42.5\ \text{A} \]

Below 42.5 A the MOSFET conducts more efficiently; above it the IGBT wins, because the fixed 1.7 V is eventually cheaper than a resistance rising with the square of current. Note the shape of the answer: the MOSFET's advantage is greatest at light load, which matters enormously for equipment that spends most of its life part-loaded.

2 Total loss and junction temperature

Problem. An IGBT switching 400 V at 50 A has \(E_{on} = 1.2\) mJ, \(E_{off} = 0.9\) mJ, and \(V_{CE(sat)} = 2.0\) V at \(D = 0.45\). Find the total loss at 10 kHz and at 20 kHz.

Solution.

Working

\[ P_{cond} = V_{CE(sat)}I_CD = (2.0)(50)(0.45) = 45\ \text{W} \]

\[ P_{sw} = (E_{on}+E_{off})f_s = (2.1\times10^{-3})(10^{4}) = 21\ \text{W} \;\Rightarrow\; P_{tot} = 66\ \text{W} \]

\[ \text{At } 20\ \text{kHz}: \quad P_{sw} = 42\ \text{W} \;\Rightarrow\; P_{tot} = 87\ \text{W} \]

Doubling the frequency raises the total loss by a third — and the conduction term, which is the majority at 10 kHz, is untouched. This is the calculation that decides the switching frequency of every drive and inverter in Part 4.

3 Gate drive current, speed, and power

Problem. A MOSFET has \(Q_G = 120\) nC and \(Q_{GD} = 30\) nC, with a Miller plateau at 6 V. Driven from 15 V through \(R_G = 10\ \Omega\) at 100 kHz, find the peak gate current, the voltage transition time, and the drive power. Then repeat with \(R_G = 22\ \Omega\).

Solution.

Working

\[ I_{G(peak)} = \frac{15-6}{10} = 0.9\ \text{A}, \qquad t_{sw} \approx \frac{Q_{GD}}{I_{G}} = \frac{30\times10^{-9}}{0.9} = 33\ \text{ns} \]

\[ P_{drive} = Q_GV_{GS}f_s = (120\times10^{-9})(15)(10^{5}) = 0.18\ \text{W} \]

\[ \text{With } R_G = 22\ \Omega: \quad I_G = 0.41\ \text{A}, \quad t_{sw} \approx 73\ \text{ns} \]

The drive power is trivial, but the driver must source nearly an ampere for 33 ns — a logic output cannot. Raising \(R_G\) to 22 Ω more than doubles the transition time and therefore roughly doubles the switching energy, while halving the \(dv/dt\) seen by the rest of the circuit. That is the EMI-versus-efficiency dial in numbers.

4 Sizing a bootstrap capacitor

Problem. A high-side IGBT needs \(Q_G = 100\) nC per switching event. The driver's floating section draws 200 µA quiescent, and the longest on-time is 50 µs. The bootstrap voltage may droop by 0.5 V. Find \(C_{boot}\).

Solution. The capacitor must supply the gate charge plus the quiescent drain over the whole on-time:

Working

\[ Q_{tot} = Q_G + I_qt_{on} = 100\ \text{nC} + (200\times10^{-6})(50\times10^{-6}) = 100 + 10 = 110\ \text{nC} \]

\[ C_{boot} \ge \frac{Q_{tot}}{\Delta V} = \frac{110\times10^{-9}}{0.5} = 220\ \text{nF} \;\Rightarrow\; \text{specify } 1\ \mu\text{F} \]

The customary factor-of-five margin covers capacitor tolerance, temperature and the leakage of the bootstrap diode. Note the built-in limitation: the capacitor recharges only while the low-side device conducts, so a bootstrap supply cannot support 100% duty cycle — a full isolated supply is required for that.

5 Choosing the heatsink

Problem. The device of Example 2 at 10 kHz dissipates 66 W. It has \(R_{th(j-c)} = 0.35\) °C/W, an interface of 0.15 °C/W, and \(T_{j(max)} = 150\) °C. Ambient is 45 °C. Find the required heatsink resistance, first at full rating and then derated to \(T_j = 120\) °C.

Solution. Work backwards from the permitted rise:

Working

\[ R_{th(total)} = \frac{150-45}{66} = 1.59\ ^\circ\text{C/W} \;\Rightarrow\; R_{th(s-a)} = 1.59 - 0.35 - 0.15 = 1.09\ ^\circ\text{C/W} \]

\[ \text{Derated}: \quad R_{th(total)} = \frac{120-45}{66} = 1.14 \;\Rightarrow\; R_{th(s-a)} = 0.64\ ^\circ\text{C/W} \]

Buying 30 °C of margin has nearly halved the permissible heatsink resistance, which in practice means roughly twice the fin volume or the addition of a fan. Thermal margin is expensive — and it is almost always worth it, since junction temperature governs lifetime.

6 Paralleling and the temperature coefficient

Problem. Two MOSFETs share 60 A. Their on-resistances are 20 mΩ and 24 mΩ. Find the initial split, and explain what happens as they heat. Contrast with two paralleled IGBTs.

Solution. Equal voltage across both branches means current divides inversely with resistance:

Working

\[ \frac{I_1}{I_2} = \frac{R_2}{R_1} = \frac{24}{20} = 1.2, \qquad I_1 + I_2 = 60 \;\Rightarrow\; I_1 = 32.7\ \text{A},\ I_2 = 27.3\ \text{A} \]

The 20 mΩ device takes 20% more current and therefore dissipates more — but its \(R_{DS(on)}\) rises with temperature, raising its share of the voltage and pushing current back to its partner. The imbalance is self-correcting, which is why MOSFETs parallel without sharing resistors. Two IGBTs would behave the opposite way at light load, where \(V_{CE(sat)}\) falls with temperature, so they require matched devices, a shared heatsink, and symmetric layout — the same discipline Chapter 4 demanded of thyristor strings.

Review

Summary & Formula Sheet

✓ Self-commutating

The control terminal commands both transitions, so the commutation circuit of Chapter 4 disappears entirely.

✓ BJT

Current-driven with low \(\beta\), slow storage time, and second breakdown. Obsolete, but its vocabulary survives in the IGBT.

✓ MOSFET

Resistive on-state, no stored charge, positive tempco (parallels easily), intrinsic body diode. Dominant below ~200 V.

✓ IGBT

MOS gate, bipolar output. Low fixed \(V_{CE(sat)}\), but a tail current at turn-off and a latch-up threshold. Dominant 600 V–6.5 kV.

✓ Loss

\(P = \) conduction \(+\ (E_{on}+E_{off})f_s\). Only the second term scales with frequency, and their crossing fixes the practical \(f_s\).

✓ Gate drive

\(I_G = (V_{drive}-V_{plateau})/R_G\), \(P_{drive} = Q_GV_{GS}f_s\). Add negative bias, dead time, bootstrap or isolation, and desat protection.

Formula sheet · Chapter 5

MOSFET conduction lossuse the HOT \(R_{DS(on)}\)

\( P_{cond} = I^2 R_{DS(on)}\,D \)

IGBT conduction lossfixed offset plus slope

\( P_{cond} = \left(V_{CE0}I + r\,I^2\right)D \;\approx\; V_{CE(sat)}I\,D \)

Switching lossfrom datasheet energies, not from \(t_r,t_f\)

\( P_{sw} = \left(E_{on}+E_{off}\right)f_s \)

Total device losswhat sizes every heatsink in Parts 3–4

\( P_{tot} = P_{cond} + P_{sw} \)

MOSFET / IGBT crossoverconduction only; equal drops

\( I_{cross} \approx \dfrac{V_{CE0}}{R_{DS(on)} - r} \)

On-resistance scalingwhy silicon MOSFETs stop near 600 V

\( R_{DS(on)} \propto V_{BR}^{\,2.5} \)

Peak gate current\(R_G\) is the master control

\( I_{G(peak)} = \dfrac{V_{drive}-V_{plateau}}{R_G} \)

Transition time\(Q_{GD}\) = Miller plateau charge

\( t_{sw} \approx \dfrac{Q_{GD}}{I_{G(peak)}} \)

Gate drive powerall of it goes into the driver, not the device

\( P_{drive} = Q_G\,V_{GS}\,f_s \)

Thermal chainsolve backwards for the heatsink

\( T_j = T_a + P_{tot}\left(R_{th(j-c)}+R_{th(c-s)}+R_{th(s-a)}\right) \)

Required heatsinkthe only free variable

\( R_{th(s-a)} = \dfrac{T_{j(max)}-T_a}{P_{tot}} - R_{th(j-c)} - R_{th(c-s)} \)

Key terms

Self-commutating: Turns off on a control-terminal command, with no help from the external circuit. The property that made Parts 3 and 4 possible.
Quasi-saturation: In a BJT, the delay before the drift region floods with carriers. The stored charge then produces a long storage time at turn-off.
Second breakdown: Local current filamentation creating a hot spot that draws more current. Destroys bipolar devices inside their nominal ratings.
\(R_{DS(on)}\): MOSFET on-resistance. Scales as \(V_{BR}^{2.5}\) and roughly doubles from 25 °C to 125 °C — always use the hot value.
Body diode: The unavoidable p-body-to-drift diode in a MOSFET. Free antiparallel diode, but slow, with substantial \(Q_{rr}\).
Gate charge, \(Q_G\): Charge needed to switch the gate fully. Fixes drive power \(Q_GV_{GS}f_s\); the \(Q_{GD}\) portion fixes transition time.
Conductivity modulation: Minority-carrier injection flooding a lightly doped drift region, collapsing its resistance. Buys a low drop; charges for it at turn-off.
Tail current: The IGBT's slow current decay at turn-off while stored charge recombines, at full voltage. The main limit on IGBT frequency.
Latch-up: The IGBT's parasitic thyristor turning on, so the gate loses control — exactly the Chapter 3 mechanism. Sets the maximum collector current.
Dead time: Interval in a bridge leg with both devices off, preventing shoot-through. Costs output-waveform distortion (Ch. 18).
Desaturation protection: Monitoring \(V_{CE}\) during conduction to detect a short circuit and turn off softly, within the ~10 µs short-circuit SOA.
Bootstrap supply: A capacitor recharged through a diode each time the low-side device conducts, powering the floating high-side gate driver.

Self-assessment

Test Yourself

This chapter closes Part 1. If you can answer these six, you have the device knowledge the rest of the book assumes.

Chapter 5 · six questions answers hidden until you ask

An IGBT drops 1.9 V at 40 A. A MOSFET with 40 mΩ (hot) drops \(40 \times 0.04 = 1.6\) V at the same current. Below what current does the MOSFET win, and what happens above it?

Set the drops equal. Treating the IGBT as a fixed 1.9 V offset over this range and the MOSFET as purely resistive:

\(I \times 0.04 = 1.9 \;\Rightarrow\; I = 47.5\) A.

Below 47.5 A the MOSFET drops less, and the advantage grows as current falls — at 10 A it drops 0.4 V against the IGBT's 1.9 V, a factor of nearly five.
Above 47.5 A the IGBT wins, and the gap widens fast because the MOSFET's loss goes as \(I^2\) while the IGBT's is closer to linear.

The design consequence is about the load profile, not the peak. A drive that spends most of its life at 20% load should be sized on the MOSFET's advantage there, even if the IGBT wins at the rating plate. Ask what current the converter actually sits at, not what it is rated for.

Why do MOSFETs parallel happily while IGBTs are supplied as matched modules?

The sign of the temperature coefficient decides it, and it flips the feedback loop from positive to negative.

MOSFET (positive coefficient): \(R_{DS(on)}\) rises with temperature. A device taking more than its share heats up, becomes more resistive, and pushes current back to its neighbours. The imbalance self-corrects.

IGBT (negative coefficient at low current): \(V_{CE(sat)}\) falls with temperature. A device taking more than its share heats up, drops less voltage, and takes still more. The imbalance grows — the same runaway seen with paralleled diodes in Chapter 2.

Two practical notes: modern IGBTs are designed so the coefficient turns positive above roughly half rated current, which helps at high load but not at light load. And a common heatsink is not optional for either device: it couples the temperatures so the whole group tracks together, which is why multi-die modules on a single baseplate exist.

A MOSFET with \(Q_G = 90\) nC is driven from 12 V at 200 kHz. Find the gate drive power. Where does it go?

\(P_{drive} = Q_GV_{GS}f_s = (90\times10^{-9})(12)(200\times10^{3}) = \) 0.216 W.

Where it goes is the interesting part. Almost none of it is dissipated in the MOSFET. The energy is dissipated in the resistance of the charging path — the driver's output transistors and the external gate resistor \(R_G\).

Two consequences that catch people out:

The gate resistor must be rated for it. 0.216 W across a small surface-mount resistor is not trivial, and at 500 kHz with a bigger device it can reach a watt or more.
The driver IC must dissipate its share. Driver overheating in high-frequency designs is common and is easily missed, because the obvious suspect is always the power device.

Note also what \(P_{drive}\) is proportional to: frequency. It is another term that punishes you for switching fast, alongside \(E_{on}\) and \(E_{off}\).

A bridge leg destroys both devices at power-up, every time, with no load connected. Where would you look?

Both devices dying together, with no load, means the fault current came from the DC link straight through the leg — shoot-through. Four suspects, in order of likelihood:

Inadequate or absent dead time. Check the actual gate waveforms with a differential probe, not the controller's intent. Include the driver's propagation-delay mismatch, not just its typical delay.
Undefined gate state at power-up. Before the controller initialises, its outputs float. Without pull-down resistors at the gates, stray coupling turns devices on. This exactly matches "every time, at power-up".
\(dv/dt\)-induced turn-on. When one device switches, the \(dv/dt\) couples through \(C_{GD}\) of the opposite device and can lift its gate above threshold. The cure is negative off-state bias and a low-impedance gate pull-down — dead time does not fix this, which is why it is so often missed.
Bootstrap not pre-charged. The high-side supply may be below its undervoltage lockout at power-up, leaving that device partly on — a linear resistor across the DC link.

The "at power-up, every time, no load" pattern points hardest at suspects 2 and 4, since both are initialisation-state problems rather than steady-state ones.

An IGBT is rated to survive a short circuit for 10 µs. Your protection circuit detects the fault in 2 µs and turns the device off in 0.5 µs. Is that a good design?

The timing is comfortable. The 0.5 µs turn-off is the problem.

During a short circuit the device is carrying perhaps ten times rated current. Turning that off in 0.5 µs gives an enormous \(di/dt\), and the DC-link stray inductance responds with \(V = L\,di/dt\). With \(L = 100\) nH and a fall from 600 A in 0.5 µs, that is \(100\times10^{-9} \times 1.2\times10^{9} = \) 120 V of overshoot on top of the rail — and stray inductance in a poorly laid-out bus can be several times that.

So the protection circuit destroys the device it was fitted to save, via overvoltage instead of overcurrent.

The correct design is a soft turn-off: deliberately switch to a much larger gate resistance (or ramp the gate down) so the fault current decays over 2–3 µs instead of 0.5 µs. You still finish inside the 10 µs budget, and the overshoot stays within the device's voltage rating.

This is a good example of a general principle: protection must be designed against the failure it creates, not only the failure it prevents.

Part 1 is now complete. In one sentence each, when would you specify a diode, an SCR, a MOSFET, and an IGBT?

Diode — when the circuit itself should decide conduction and you need no control at all: rectifier bridges, freewheeling paths, blocking and clamping.
SCR — when an AC supply will commutate it for free and you want the lowest possible on-state drop at very high current: phase-controlled rectifiers, soft starters, HVDC valves, crowbars.
MOSFET — when the voltage is low (under a few hundred volts) and the frequency is high, and you want easy paralleling: SMPS, point-of-load converters, low-voltage drives.
IGBT — when the current is high and the frequency is moderate (a few kHz to ~30 kHz) at 600 V and above: motor drives, solar and EV inverters, UPS, welding.

And the meta-answer: the question is never "which device is best". It is "which axis is my design constrained on — voltage, current, frequency, or drive complexity?". Every chapter of Part 1 has been an answer to a different version of that question, and Parts 2 to 7 now apply those devices to the four conversion families.

Practice

Problems

Sort each question into one of three domains before reaching for a relation:

Conduction — \(R_{DS(on)}\) or \(V_{CE(sat)}\), duty ratio, hot values.
Switching — \(E_{on}\), \(E_{off}\), frequency, tail current, recovery of the opposing diode.
Drive and thermal — \(Q_G\), \(R_G\), dead time, \(R_{th}\) chain, SOA.

Problems 1–6 are direct application; 7–10 need judgement; the remainder are design questions worth discussing in a tutorial.

State which device you would choose for: (a) a 48 V, 30 A, 200 kHz DC–DC converter, (b) a 400 V, 100 A, 8 kHz motor drive, (c) a 6 kV, 2 kA HVDC valve, (d) a 12 V, 5 A point-of-load regulator.
Explain why the power MOSFET has an intrinsic body diode, and give one situation in which that diode is welcome and one in which it is a problem.
A MOSFET has \(R_{DS(on)} = 18\) mΩ at 25 °C, doubling by 125 °C. Find the conduction loss carrying 25 A at \(D = 0.6\), hot.
An IGBT with \(V_{CE(sat)} = 1.9\) V carries 40 A at \(D = 0.4\). Find the conduction loss, and the current at which a MOSFET of 40 mΩ (hot) would match it.
A device has \(E_{on} = 2.4\) mJ and \(E_{off} = 1.8\) mJ. Find the switching loss at 4, 16 and 40 kHz, and comment on which application each frequency suits.
For the device of Problem 5 with 30 W of conduction loss, find the frequency at which switching loss equals conduction loss.
A MOSFET has \(Q_G = 75\) nC, \(Q_{GD} = 20\) nC and a 5 V plateau, driven from 12 V. Find \(I_{G(peak)}\) and \(t_{sw}\) for \(R_G = 5\ \Omega\) and \(R_G = 15\ \Omega\), and the drive power at 250 kHz.
Explain, in terms of \(C_{GD}\), why a negative off-state gate bias prevents false turn-on, and relate the mechanism to the \(dv/dt\) triggering of Chapter 3.
A high-side driver needs 150 nC per event, draws 250 µA quiescent, and must support a 200 µs on-time with 0.4 V droop. Size \(C_{boot}\) and state why 100% duty cycle is impossible.
A device dissipates 85 W with \(R_{th(j-c)} = 0.25\) and interface 0.12 °C/W. With \(T_a = 40\) °C, find the heatsink resistance for \(T_j = 150\) °C and for \(T_j = 110\) °C.
Three MOSFETs of 22, 25 and 28 mΩ share 90 A. Find each current, and explain why no sharing resistors are needed.
A 20 kHz, 400 V, 60 A IGBT inverter leg suffers repeated failures of the upper device only, always during rapid load changes. Using the concepts of this chapter — dead time, \(dv/dt\)-induced turn-on, bootstrap droop, desaturation and RBSOA — propose three plausible causes, state what measurement would distinguish them, and give the remedy for each.

Tip: three datasheet parameters answer most questions in this chapter. \(R_{DS(on)}\) or \(V_{CE(sat)}\) gives conduction loss and needs the hot value. \(E_{on}\) and \(E_{off}\) give switching loss and scale with \(f_s\). \(Q_G\) and \(Q_{GD}\) give drive power and transition speed. If a problem quotes a resistance or a saturation voltage it is a conduction question; if it quotes millijoules it is a switching question; if it quotes nanocoulombs it is a gate-drive question.