Transients on Transmission Lines
Everything so far on lines has been steady state — a sinusoid that has been running forever. But the most consequential moments on a line are the first few nanoseconds after something changes: a switch closes, a digital edge launches, a lightning surge arrives. Because the line has a finite transit time, the source cannot know the load exists until a wave has travelled down and back. In that interval the line behaves like a pure resistance \(Z_0\), launches a step, and then the reflections begin — bouncing between the two ends, each smaller than the last, the voltage climbing or ringing its way to the DC answer. This chapter tracks that dance with the bounce diagram, and ends with the trick that turns it into a fault-finding instrument.
- Why the source first sees the line as a resistance \(Z_0\), launching \(V_1^{+}=V_g Z_0/(R_g+Z_0)\).
- The load and source reflection coefficients \(\Gamma_L\) and \(\Gamma_g\).
- The one-way transit time \(T=\ell/u\) and how each round trip scales by \(\Gamma_g\Gamma_L\).
- How to draw and read a bounce (lattice) diagram.
- The staircase approach to the steady value \(V(\infty)=V_g R_L/(R_g+R_L)\).
- Matched-source and matched-load special cases, and time-domain reflectometry for locating faults.
Steady State to Transient
The phasor analysis of Chapters 24 and 25 answers "what does the line do to a continuous sine wave?" It says nothing about the moment that wave is switched on. For a step or a pulse — a digital bit, a surge, the leading edge of any signal — we need the transient response in the time domain. The key physical fact is that information travels at finite speed \(u\), so a line of length \(\ell\) has a one-way transit time:
Until a full round trip \(2T\) has elapsed, the source has received no news from the load. We restrict attention to lossless lines with purely resistive terminations \(R_g\) and \(R_L\), driven by a DC source switched on at \(t=0\) — the canonical transient problem.
The Initial Wave
At the instant the switch closes, the source looks into the line and sees… not \(R_L\), which is a transit time away and still unknown, but the line's own characteristic impedance \(Z_0\). The line accepts current exactly as a resistor \(Z_0\) would. So the launched voltage is a simple resistive divider between \(R_g\) and \(Z_0\):
This step propagates toward the load at speed \(u\), arriving at \(t=T\). Behind its leading edge the line is charged to \(V_1^{+}\); ahead of it the line is still quiet. This is the seed from which the entire transient grows.
Reflections at Both Ends
When the step reaches the load at \(t=T\), the load demands its own ratio of voltage to current, \(R_L\) — which \(V_1^{+}\) and \(I_1^{+}\) generally do not satisfy. The line resolves the mismatch by sending back a reflected wave, scaled by the familiar load reflection coefficient. That reflected wave reaches the source at \(t=2T\), where \(R_g\) imposes its ratio, so a second reflection is launched, scaled by the source reflection coefficient:
From then on the pattern is mechanical. Every bounce off the load multiplies the travelling wave by \(\Gamma_L\); every bounce off the source multiplies it by \(\Gamma_g\). One complete round trip — load then source — therefore scales the wave by the product \(\Gamma_g\Gamma_L\), and the successive waves form a geometric sequence \(V_1^{+},\,\Gamma_g\Gamma_L V_1^{+},\,(\Gamma_g\Gamma_L)^2 V_1^{+},\dots\) Since both coefficients have magnitude \(\le1\) for resistive terminations, the bounces shrink and the line settles.
The Bounce Diagram
The bookkeeping is made visual by the bounce diagram (or lattice diagram): position runs across, time runs down, and each travelling wave is a diagonal line crossing the line in one transit time \(T\). At each end the diagonal reflects, picking up a factor of \(\Gamma_L\) or \(\Gamma_g\). To find the voltage at any place and time, draw a vertical line at that position and add up every wave whose diagonal it has already crossed.
Voltage in Time
At the load, the voltage updates every time a new wave arrives — once per round trip, at \(t=T, 3T, 5T,\dots\) Each arrival adds a forward wave and its instantly-reflected partner, a contribution \((1+\Gamma_L)\) times the incoming wave. The result is a staircase that steps toward the final value, overshooting and correcting if the steps alternate in sign:
Summing the geometric series of all contributions gives a closed form, and it collapses — reassuringly — to the plain DC voltage divider, exactly what circuit theory predicts once the wave nature has died away:
Special Terminations
The behaviour ranges from a single clean step to endless ringing, depending on the terminations. Three cases are worth committing to memory:
| Case | Condition | Effect |
|---|---|---|
| Matched source | \(R_g=Z_0\;(\Gamma_g=0)\) | load reflection is absorbed; settles after \(2T\), no further bounces |
| Matched load | \(R_L=Z_0\;(\Gamma_L=0)\) | no reflection at all; final value reached at \(t=T\) |
| Open / short load | \(\Gamma_L=\pm1\) | full reflection; persistent ringing, damped only by \(R_g\) |
This is the whole rationale for terminating high-speed digital lines. An unterminated trace (\(R_L\) large, \(R_g\) small) rings violently as edges reflect back and forth, producing overshoot and false logic transitions. Adding a series resistor at the driver to make \(R_g=Z_0\), or a parallel resistor at the receiver to make \(R_L=Z_0\), kills the reflections and lets the signal settle in one or two transit times. Signal integrity at gigahertz edge rates is, at bottom, this chapter applied to circuit-board traces.
Time-Domain Reflectometry
Run the logic backwards and the transient becomes a measuring instrument. Send a fast step down an unknown cable and watch the echoes: every impedance discontinuity — a break, a crush, a bad connector, a branch — sends a reflection back, arriving after a round-trip delay that pinpoints its distance. This is time-domain reflectometry (TDR):
The sign of the echo even tells you the fault type — a positive reflection means a higher impedance (an open or break), a negative one means a lower impedance (a short or crush) — directly from \(\Gamma=(Z_{\text{fault}}-Z_0)/(Z_{\text{fault}}+Z_0)\). Cable technicians, board designers, and chip engineers all use TDR to find discontinuities they can never see.
Worked Examples
Problem. A \(10\,\text{V}\) source with \(R_g=30\,\Omega\) is switched onto a \(50\,\Omega\) line. Find the initial wave \(V_1^{+}\) and current \(I_1^{+}\).
Solution. The source sees \(Z_0\), so divide between \(R_g\) and \(Z_0\):
Problem. A \(12\,\text{V}\) source, \(R_g=150\,\Omega\), drives a \(50\,\Omega\) line into \(R_L=25\,\Omega\). Find \(\Gamma_g\), \(\Gamma_L\), and the load voltage just after \(t=T\).
Solution. \(V_1^{+}=12(50/200)=3\,\text{V}\); the load voltage on first arrival is \(V_1^{+}(1+\Gamma_L)\):
Problem. For the same circuit, find the final load voltage \(V(\infty)\).
Solution. The transient settles to the DC divider — confirm it equals the bounce series:
Problem. A \(6\,\text{V}\) source with \(R_g=50\,\Omega\) drives a \(50\,\Omega\) line into \(R_L=100\,\Omega\). When does the load voltage reach its final value, and what is it?
Solution. \(\Gamma_g=0\), so the load reflection is absorbed at the source — the load reaches its final value on first arrival:
Problem. A \(20\,\text{m}\) cable has a dielectric of \(\varepsilon_r=2.25\). Find the one-way transit time \(T\) and the round-trip time.
Solution. \(u=c/\sqrt{\varepsilon_r}=2\times10^8\,\text{m/s}\); then \(T=\ell/u\):
Problem. A TDR step into a cable (\(u=2\times10^8\,\text{m/s}\)) returns an echo at \(300\,\text{ns}\). How far away is the fault, and what kind is it if the echo is negative?
Solution. Use \(d=u\,t_{\text{echo}}/2\); a negative echo means a lower impedance:
Chapter Summary
Source sees \(Z_0\) first: \(V_1^{+}=V_g\dfrac{Z_0}{R_g+Z_0}\), launched at \(t=0\).
\(\Gamma_L=\dfrac{R_L-Z_0}{R_L+Z_0}\), \(\Gamma_g=\dfrac{R_g-Z_0}{R_g+Z_0}\).
Transit time \(T=\ell/u\); each round trip scales the wave by \(\Gamma_g\Gamma_L\).
Zig-zag in the z–t plane; sum the waves that have arrived.
Staircase converges to the DC divider \(V(\infty)=V_g\dfrac{R_L}{R_g+R_L}\).
Match either end to stop ringing; TDR locates faults via \(d=ut_{\text{echo}}/2\).
Problems
For each item, compute \(V_1^{+}\), \(\Gamma_L\), and \(\Gamma_g\) first — they generate the whole bounce sequence. Remember the load voltage updates every \(2T\) starting at \(t=T\). Difficulty rises down the list.
- A \(5\,\text{V}\) source with \(R_g=25\,\Omega\) drives a \(75\,\Omega\) line. Find \(V_1^{+}\).
- For a \(50\,\Omega\) line into \(R_L=150\,\Omega\), find \(\Gamma_L\).
- For the same line driven through \(R_g=50\,\Omega\), find \(\Gamma_g\) and explain what it implies.
- A \(2\,\text{m}\) PCB trace has \(u=1.5\times10^8\,\text{m/s}\). Find the transit time \(T\).
- A \(10\,\text{V}\) source, \(R_g=100\,\Omega\), \(Z_0=50\,\Omega\), \(R_L=\infty\) (open). Find \(V_1^{+}\) and the load voltage just after \(t=T\).
- For \(V_g=8\,\text{V}\), \(R_g=20\,\Omega\), \(Z_0=50\,\Omega\), \(R_L=200\,\Omega\), find \(V(\infty)\).
- A \(9\,\text{V}\) source, \(R_g=150\,\Omega\), \(Z_0=50\,\Omega\), \(R_L=0\) (short). Sketch the first three steps of the load current in time.
- Show that a matched load (\(R_L=Z_0\)) gives no reflection and the load reaches \(V(\infty)\) at \(t=T\).
- A TDR echo returns at \(450\,\text{ns}\) on a cable with \(u=2\times10^8\,\text{m/s}\). Find the fault distance.
- For \(V_g=12\,\text{V}\), \(R_g=150\,\Omega\), \(Z_0=50\,\Omega\), \(R_L=25\,\Omega\), find the load voltage at \(t=3T\).
- Explain why a series resistor at the driver equal to \(Z_0\) eliminates ringing on a digital line.
- A positive TDR echo of relative size \(0.2\) is seen. Estimate the impedance of the discontinuity relative to \(Z_0\).