Unit 9 — Power Devices, SMPS/UPS & Control Systems: Complete Exam Notes

§ 9.1SCR: Characteristics & Two-Transistor Model

The Silicon Controlled Rectifier (thyristor) is a four-layer P-N-P-N, three-terminal (Anode, Cathode, Gate) latching switch — the workhorse of high-power control (kV, kA).

V–I characteristic (three regions)

• Forward blocking (V_AK > 0, gate open): only small leakage until the forward break-over voltage V_BO; J₂ blocks.
• Forward conduction (latched): after triggering, V_AK drops to ~1–1.5 V, large current flows, device acts as a closed switch; negative-resistance transition between the two.
• Reverse blocking (V_AK < 0): like a reverse diode until reverse breakdown V_BR (J₁, J₃ block).

Two-transistor (regenerative) model — the key explainer

Split the PNPN into a PNP (Q₁) + NPN (Q₂) with cross-coupled collector–base:

Gate current raises α₂ (α rises with current) → loop gain reaches 1 → each transistor drives the other into saturation → latch. Once latched, the gate loses control.

Key currents & turn-off

• Latching current I_L: minimum anode current to stay on just after triggering (gate still applied); holding current I_H: minimum to remain on (I_L ≈ 2–3 × I_H).
• Turn-off = commutation (drop I_A below I_H): natural/line commutation (AC reverses each half cycle — phase-controlled rectifiers) or forced commutation (DC circuits: a charged capacitor / LC momentarily reverse-biases or zeros I_A — choppers, inverters). Turn-off time t_q (reverse + gate-recovery) defines slow vs fast (inverter-grade) SCRs.
• Turn-on methods: gate triggering (normal), plus forward over-voltage, dv/dt, light (LASCR), and temperature (all undesired — see §9.5).
• Ratings: V_DRM/V_RRM, I_T(avg)/I_T(rms), I²t surge, di/dt & dv/dt limits.
• GTO (gate turn-off thyristor): a negative gate pulse turns it off — used in traction inverters before IGBTs.

§ 9.2DIAC & TRIAC

DIAC (DIode AC switch)

• Two-terminal, bidirectional three-layer (or 5-layer) device — no gate; conducts in either direction once |V| exceeds the break-over voltage V_BO (~30 V), then exhibits a negative-resistance snap (V drops ~5 V).
• Symmetrical V–I (breaks over both polarities). Chief use: triggering device for the TRIAC gate — provides a sharp current pulse at a controlled phase angle in dimmer/speed circuits.

TRIAC (TRIode AC switch)

• Three-terminal (MT1, MT2, Gate), bidirectional thyristor ≡ two SCRs in inverse-parallel sharing one gate → controls both half-cycles of AC directly.
• Four-quadrant triggering (MT2 ±, gate ±); quadrant I⁺ and III⁻ are most sensitive; quadrant II/III with opposite-polarity gate are weaker — so dv/dt and asymmetry need care.
• Limitations vs back-to-back SCRs: lower power/voltage, poorer dv/dt immunity and commutation (single device sees the full reversal) → snubber needed; used to ~kW, mains 50/60 Hz.
• Phase control the standard application: DIAC + RC sets the firing angle α each half cycle → lamp dimmers, fan/universal-motor speed, heater control.
  Phase-controlled output (resistive load, full wave) $$ V_{o(rms)} = V_{rms}\sqrt{\frac{1}{\pi}\left[(\pi - \alpha) + \frac{\sin 2\alpha}{2}\right]} \qquad (\alpha = \text{firing angle}) $$

§ 9.3Power Transistors: BJT, MOSFET, IGBT

• Safe Operating Area (SOA): the V–I–time envelope; BJTs suffer second breakdown (current crowding/thermal runaway) → restricted SOA; MOSFETs are largely free of it (positive TC spreads current) — a recurring MCQ.
• MOSFET = majority-carrier, no storage time, body diode included; gate is capacitive (drive current only to charge C_iss — Miller plateau during switching).
• IGBT = MOS gate + BJT output (voltage-driven input, conductivity-modulated low-drop output) → combines MOSFET ease of drive with BJT low conduction loss at high voltage; tail current limits f_sw. The dominant device in EV/industrial inverters.
• SiC MOSFET / GaN HEMT (Unit-1 §1.17) now extend f_sw, voltage and efficiency beyond Si.

§ 9.4Thyristor Protection: Over-Voltage & Over-Current

Over-voltage protection

• Sources: switching/commutation transients, lightning, supply spikes; exceeding V_DRM can falsely fire or destroy the device.
• Remedies: RC snubber across the SCR (limits dv/dt and absorbs transient energy — also §9.5), metal-oxide varistor (MOV) / selenium suppressor / TVS clamping the line, crowbar (an SCR that fires to short the supply into a fuse on over-voltage), and voltage-grading networks for series strings.

Over-current protection

• Sources: load short, commutation failure, overload. SCRs have low thermal mass → act fast.
• Remedies: fast-acting (semiconductor) HRC fuses with I²t coordination — the fuse I²t must be less than the SCR's withstand I²t so the fuse clears first; magnetic circuit breakers for slower overloads; current-limiting reactor (series L) caps di/dt and peak fault current; electronic over-current relays gating the trigger off.
• Series/parallel operation: voltage-equalizing resistors + RC for series strings; current-sharing reactors + matched devices for parallel.

• Thermal: heat sinks, junction-to-case thermal resistance budget \( T_J = T_A + P\theta_{JA} \); forced-air/liquid cooling for high power.

§ 9.5SCR Triggering: dv/dt & di/dt

dv/dt (false turn-on) and its snubber

• A rapidly rising anode voltage drives capacitive (displacement) current through junction J₂: \( i = C_{J2}\,dv/dt \). If large enough it acts like gate current → unwanted firing without a gate signal — a reliability hazard.
• Cure: RC snubber across the SCR limits the rate the device sees:
  Snubber action $$ \left.\frac{dv}{dt}\right|_{device} \approx \frac{V}{R_s C_s}\ \text{(initial)};\qquad R_s \text{ limits capacitor discharge current at turn-on} $$
  C_s slows the voltage rise; R_s damps the L-C ringing and limits the C-discharge surge into the SCR when it does fire (R_s also bounds turn-on di/dt from the snubber).

di/dt (turn-on current rate)

• At turn-on, conduction starts in a small area near the gate and spreads (plasma spreading velocity ~50–100 µm/µs). If anode current rises faster than the conducting region grows → local hot spot → device failure.
• Cure: series inductor (di/dt reactor / saturable reactor) in the anode line limits \( di/dt = V/L \); interdigitated/amplifying gates speed up area spreading. Manufacturer's di/dt rating must not be exceeded.

§ 9.6Gate Triggering: Single Pulse & Train of Pulses

• Gate requirements: the gate pulse must exceed I_GT/V_GT, stay within the safe gate-power locus, and persist until anode current exceeds the latching current I_L — otherwise the SCR fails to stay on. Steep-front pulses reduce turn-on di/dt stress and spread; pulse amplitude ≥ a few × I_GT for reliability.
• Triggering circuits: RC phase-shift (simple, lossy), UJT relaxation oscillator (the classic — intrinsic standoff ratio η ≈ 0.5–0.8; \( f = 1/[RC\ln(1/(1-\eta))] \); fires near V_P = ηV_BB + V_D), PUT, ramp-comparator, and isolated pulse-transformer / optocoupler gate drives.

Single pulse vs train of pulses (the named comparison)

• Why a train wins for inductive loads: with a lagging current the anode current may not reach I_L during a single short pulse — repeated pulses keep re-attempting the latch until conduction is established; also eases pulse-transformer design and gate heating.

§ 9.7DC Motors: Construction & Speed Control

Construction & basics

• Stator field (poles/permanent magnet) + rotor armature + commutator + brushes (mechanical inverter keeping torque unidirectional). Back-EMF \( E_b = k\phi N \); torque \( T = k\phi I_a \); terminal \( V = E_b + I_aR_a \).
• Types: shunt (≈ constant speed), series (high starting torque, speed ∝ 1/load — traction, starters), compound; separately excited (precise control).

• Armature-voltage control (V): speed ∝ V below base speed, constant torque — the modern method via a controlled rectifier (phase-controlled SCR bridge) for AC supply or a DC chopper (PWM, duty D → V_o = D·V_in) for DC supply. Smooth, efficient.
• Field (flux) control (φ): weaken field → speed above base, constant power region; limited range, simple/cheap.
• Armature-resistance control (R_a added): reduces speed but wastes power in the resistor (poor efficiency) — legacy.
• Four-quadrant operation, regenerative braking (return energy to supply) with reversible converters.
• BLDC (electronic commutation, no brushes — reliability, efficiency) increasingly replaces brushed DC.

§ 9.8AC Motors: Construction & Speed Control

Induction motor (the industrial workhorse)

• Three-phase stator → rotating field; squirrel-cage rotor (rugged, cheap) or wound rotor (slip-ring); rotor runs at slip (2–5% full load) — induction, asynchronous. Single-phase versions need a starting auxiliary (capacitor-start, split-phase, shaded-pole).
• Speed-control methods:
  • V/f control (VFD — the dominant method): vary frequency f (changes N_s) while keeping V/f constant to hold flux → wide smooth range, constant torque; realized by a rectifier → DC link → IGBT PWM inverter (power-electronics tie-in).
  • Pole-changing (discrete speeds), stator-voltage control (fans), rotor-resistance control (wound rotor — like DC R_a, lossy), slip-recovery (Scherbius) schemes.

Synchronous motor

• Runs exactly at N_s (zero slip); needs DC field + starting means; power-factor correction by over-excitation (synchronous condenser); constant-speed drives.

Universal (series AC/DC) motor: high speed, light tools/appliances — TRIAC phase-controlled (§9.2). Stepper/servo for precise positioning (Unit-6 §6.17).

§ 9.9Switched-Mode Power Supply (SMPS)

An SMPS regulates by switching the pass device fully ON/OFF at high frequency (tens of kHz–MHz) and filtering, instead of dissipating the difference in a linear pass transistor. The switch is in saturation or cutoff → low loss → 70–95% efficiency, small high-frequency magnetics, light weight.

• Isolated (transformer) topologies: flyback (cheap, < ~150 W — stores energy in the transformer gap, chargers/adapters), forward (single-switch, mid-power), push–pull / half-bridge / full-bridge (high power, better core utilization). Transformer gives isolation + multiple/turns-ratio outputs.
• Regulation loop: output sampled → error amp vs reference → PWM comparator vs sawtooth → adjusts duty cycle (voltage-mode) or peak current (current-mode); optocoupler crosses the isolation barrier.
• Building blocks: switch (MOSFET/IGBT), fast diode (Schottky/synchronous rectifier), inductor (energy storage), output capacitor (ripple), high-f transformer. Higher f_sw → smaller L, C, transformer but more switching loss/EMI; soft-switching (ZVS/ZCS resonant) reduces both.

§ 9.10Uninterruptible Power Supply (UPS)

A UPS supplies the load through a stored-energy path (battery + inverter) so power is maintained during mains failure, sag, or surge. Core chain: rectifier/charger → battery → inverter → load, with a transfer/static switch and bypass.

• Online UPS rationale: continuous conversion regenerates a clean sine independent of input quality → zero transfer time, full conditioning; static bypass handles overload/fault.
• Battery: VRLA/Li-ion; backup time = (battery Wh × efficiency)/load W; sized for ride-through to generator start or graceful shutdown.
• Inverter output quality: pure sine (sensitive/PFC loads) vs modified/stepped sine (cheap, basic loads).
• Specs: VA/W rating (power factor!), runtime, efficiency, THD, transfer time; contrast with a standby generator (long outages, slow start) — often paired.

§ 9.11Open-Loop & Closed-Loop Control Systems

• Loop gain GH; characteristic equation 1 + GH = 0 (its roots = closed-loop poles → stability, §9.14–9.15).
• Sensitivity: feedback reduces sensitivity to plant variation by 1/(1+GH); also reshapes bandwidth, disturbance and noise response (the §4.9/§3.x feedback story applied to systems).
• Time-domain specs (second-order, Unit-3 §3.10): rise time, peak overshoot \( M_p = e^{-\pi\zeta/\sqrt{1-\zeta^2}} \), settling \( t_s = 4/\zeta\omega_n \), damping ζ, natural frequency ω_n.
• Steady-state error & system type (number of s in the denominator = number of integrators):
  Static error constants $$ K_p = \lim_{s\to0}GH,\ \ K_v = \lim_{s\to0}sGH,\ \ K_a = \lim_{s\to0}s^2GH; \quad e_{ss}(\text{step}) = \frac{1}{1+K_p},\ e_{ss}(\text{ramp}) = \frac{1}{K_v} $$
  Type-0 → finite step error; Type-1 → zero step error, finite ramp error; Type-2 → tracks ramps with zero error. Adding an integrator (PI, §9.16) raises the type → kills steady-state error.

§ 9.12Block-Diagram Reduction

• Strategy: combine innermost cascades/parallels first, collapse inner feedback loops, then relocate summing/take-off points to untangle interlocking loops, repeat until a single block C/R remains.
• The relocation rules keep the signal mathematically unchanged — the inserted 1/G or G compensates the moved block.
• For multi-input systems (reference + disturbance), use superposition: find C/R with disturbance = 0 and C/D with reference = 0, then add.

§ 9.13Transfer Function & Signal-Flow Graphs

• Transfer function T(s) = C(s)/R(s) at zero initial conditions = ℒ{output}/ℒ{input}; poles = roots of the characteristic polynomial (denominator), zeros = numerator roots (Unit-3 §3.11). Defined only for LTI systems; impulse response = ℒ⁻¹{T(s)}.
• Signal-flow graph (SFG): nodes = variables, directed branches = gains; an algebraic, no-relocation alternative to block diagrams. Vocabulary: forward path, loop, non-touching loops, path gain, loop gain.

• Δ (graph determinant) = 1 − (sum of all loop gains) + (sum of products of two non-touching loops) − (products of three non-touching loops) + …
• P_k = gain of the k-th forward path; Δ_k = Δ evaluated with all loops touching P_k removed.
• One formula gives C/R directly — no successive reduction; the reason SFGs are exam favourites for complex multi-loop systems.

§ 9.14Routh–Hurwitz Stability Criterion

Procedure

1. Necessary condition: all coefficients of the characteristic polynomial \( a_ns^n + \cdots + a_0 \) present and of the same sign (a missing or sign-changed coefficient ⇒ unstable immediately).
2. Build the Routh array (sⁿ, sⁿ⁻¹ rows from coefficients; lower rows from 2×2 determinants).
3. Stability ⟺ no sign change in the first column; the number of first-column sign changes = number of RHP roots.

• Special cases:
  • Zero in the first column (rest of row nonzero): replace with ε → 0⁺ and continue.
  • Entire row of zeros: symmetric roots (on jω axis / RHP–LHP pairs) — form the auxiliary equation from the row above, differentiate, and use its coefficients; the auxiliary roots reveal jω-axis (marginal) crossings.
• Marginal stability: a row of zeros with auxiliary roots purely on the jω axis → sustained oscillation at \( \omega = \sqrt{\text{auxiliary root}} \).
• Design use: find the range of a gain K for stability (the classic numerical) — express the first-column entries in K and require all > 0; the boundary value gives the critical gain and oscillation frequency.

§ 9.15Nyquist Plot & Stability

A frequency-domain stability test using the open-loop G(jω)H(jω) to judge the closed-loop — and, unlike Routh, it handles transport delay and reads off relative stability (margins).

• N = number of clockwise encirclements of the −1 + j0 point by the Nyquist plot of GH (the polar plot for ω: −∞→∞, mapping the closed contour); P = open-loop poles in the RHP; Z = closed-loop poles in the RHP (must be 0 for stability). Encirclements counted counter-clockwise = −N.
• Open-loop-stable case (P = 0): closed loop stable ⟺ the plot does not encircle −1 — the everyday version.
• Relative stability — margins (Unit-3 §3.12):
  Gain & phase margins $$ GM = \frac{1}{|GH|}\bigg|_{\angle GH = -180^\circ}\ (\text{dB} = -20\log|GH|); \qquad PM = 180^\circ + \angle GH\big|_{|GH| = 1} $$
  positive GM and PM ⇒ stable; the closer the plot passes to −1, the smaller the margins, the more oscillatory.
• Relation to Bode (same information, different view): gain-crossover (|GH| = 1) ↔ PM; phase-crossover (∠ = −180°) ↔ GM. Polar-plot crossing of the negative real axis at distance d from origin → GM = 1/d.

§ 9.16On-Off, P, PI, PD & PID Controllers

• Term summary (memory hook): P = present error, I = accumulated past error, D = predicted future error.
• Tuning — Ziegler–Nichols (the named method): increase K_p until sustained oscillation → record ultimate gain K_u and period T_u → set \( K_p = 0.6K_u,\ T_i = T_u/2,\ T_d = T_u/8 \) (classic PID); or the open-loop reaction-curve (process-reaction) method. Cohen–Coon, IMC as alternatives; modern auto-tuners.
• Practical refinements: derivative on measurement (not error) to avoid setpoint kick; filtered D; integral anti-windup clamping; setpoint weighting.
• Realization: op-amp analog PID (integrator + differentiator + summer, Unit-4 §4.12) or digital (difference-equation PID in a microcontroller, Unit-6 — sampled e[n], velocity form).

§ 9.17Unit-9 Formula Sheet

§ 9.18Quick Revision Notes — Unit 9 in 25 Points

↑ Back to top of Unit 9