Unit 6 — 8086 Microprocessor & 8051 Microcontroller: Complete Exam Notes

§ 6.18086 Architecture: BIU, EU & Segmentation

The 8086 (1978): 16-bit µP, 20-bit address bus → 1 MB memory, 16-bit data bus (multiplexed AD₀–AD₁₅), 5/8/10 MHz clocks, ~29,000 transistors, 40-pin DIP, +5 V. The 8088 is identical internally but has an 8-bit external data bus (original IBM PC).

Two-unit pipelined architecture

• Bus Interface Unit (BIU): generates addresses, fetches instructions into a 6-byte prefetch queue (8088: 4 bytes), reads/writes data; contains segment registers + Instruction Pointer (IP).
• Execution Unit (EU): decodes/executes from the queue; contains the general registers, ALU, flags.
• Fetch overlaps execution → pipelining; the queue flushes on jumps/branches (the cost of transfers).

Register set

• General (16-bit, byte-addressable halves): AX (accumulator — MUL/DIV/IO), BX (base — memory pointer), CX (count — loops, shifts, strings), DX (data — 32-bit MUL/DIV partner, port address); each splits into H/L bytes (AH/AL …).
• Pointer/Index: SP (stack pointer), BP (base pointer — stack-frame access via SS), SI/DI (string source/destination indices).
• Segment registers: CS (code), DS (data), SS (stack), ES (extra — string destination).
• Flags (9 of 16 used): status — CF, PF, AF (auxiliary, BCD), ZF, SF, OF; control — TF (single-step trap), IF (INTR enable), DF (string direction: 0 → auto-increment).

• Each segment ≤ 64 KB, starts on a 16-byte (paragraph) boundary; segments may overlap; many segment:offset pairs map to one PA (e.g., 2100:0234 → 21234H too).
• Default pairs: CS:IP (code), DS:SI/BX (data), SS:SP/BP (stack), ES:DI (string destination); segment-override prefixes change defaults.
• Benefits: 1 MB reach from 16-bit registers, relocatable code/data, natural program structure.

Pins & modes (essentials)

• ALE demultiplexes AD lines (latch 74373); BHE̅ + A₀ select byte/word on the two banks (§6.6); READY inserts wait states; RESET → CS = FFFFH, IP = 0000H → first fetch at FFFF0H.
• Minimum mode (MN/MX̅ = 1): single processor, 8086 generates control signals itself. Maximum mode (= 0): multiprocessor (with 8087 coprocessor / 8089 IOP); the 8288 bus controller decodes S̅₂S̅₁S̅₀ into bus commands; queue-status and LOCK̅ pins appear.

§ 6.28086 Addressing Modes

• Valid memory-pointer registers: only BX, BP, SI, DI (never AX/CX/DX inside brackets) — a favourite trap.
• BP defaults to the stack segment; all other pointers default to DS.

§ 6.38086 Instruction Set

• Data transfer (no flag effects): MOV, PUSH/POP (always 16-bit), XCHG, IN/OUT, LEA (EA → register; arithmetic without memory access), LDS/LES (load pointer + segment), XLAT (AL = [BX+AL] table lookup), LAHF/SAHF, PUSHF/POPF.
• Arithmetic: ADD/ADC, SUB/SBB, INC/DEC (CF unaffected by INC/DEC!), NEG, CMP (subtract, flags only), MUL/IMUL (AX = AL×src; DX:AX = AX×src), DIV/IDIV (quotient AL/AX, remainder AH/DX; divide-by-zero → INT 0), CBW/CWD sign extensions; BCD adjusters DAA/DAS (packed), AAA/AAS/AAM/AAD (unpacked ASCII).
• Logical & shifts: AND/OR/XOR/NOT, TEST (AND, flags only); SHL/SAL, SHR (0 → MSB), SAR (sign-preserving) — shift count 1 or CL; rotates ROL/ROR/RCL/RCR (through carry). SHL = ×2, SAR = ÷2 signed.
• String instructions (the 8086's signature): MOVS, CMPS, SCAS, LODS, STOS (B/W suffix); SI/DI auto-update per DF (CLD/STD); REP (with CX), REPE/REPZ, REPNE/REPNZ prefixes — block move = CLD; MOV CX,N; REP MOVSB.
• Control transfer: JMP (short ±127, near, far); conditional jumps (JZ/JNZ, JC, JO, JS, JP; signed JG/JL/JGE/JLE vs unsigned JA/JB/JAE/JBE — all short-range); LOOP/LOOPE/LOOPNE (CX-driven); CALL/RET (near/far; RET n cleans stack); INT n / INTO / IRET (§6.4).
• Processor control: CLC/STC/CMC, CLI/STI, CLD/STD, HLT, NOP, WAIT, LOCK (bus lock prefix), ESC (coprocessor).

§ 6.48086 Interrupts

• Interrupt Vector Table (IVT): lowest 1 KB (00000–003FFH); 256 vectors × 4 bytes (IP low word, CS high word). Vector address = type × 4.
• Response sequence: PUSH Flags → clear IF, TF → PUSH CS → PUSH IP → load CS:IP from IVT; IRET restores IP, CS, Flags.
• Dedicated types: 0 divide error; 1 single-step (TF); 2 NMI (non-maskable pin, type fixed); 3 breakpoint (1-byte INT 3 — debuggers); 4 overflow (INTO). Types 5–31 reserved; 32–255 user/software.
• Hardware: NMI (edge, unmaskable — power-fail, parity) and INTR (level, masked by IF; type supplied by the 8259A PIC during INTA̅ cycles; one 8259 → 8 levels, cascadable to 64).
• Software: INT n (any type), INTO, and CPU-generated exceptions (divide error, single step).
• Priority (highest → lowest): divide error/INT n/INTO (internal) → NMI → INTR → single-step.
• Interrupt latency factors; nested interrupts re-enabled by STI inside the ISR; ISRs end with IRET (vs RET for procedures — a classic distinction).

§ 6.58086 Assembly Programming

• Assembler directives (not instructions — generate no code): SEGMENT/ENDS, ASSUME, ORG, DB/DW/DD (define data), EQU, DUP, PROC/ENDP (NEAR/FAR), MACRO/ENDM, OFFSET/SEG/PTR operators, END.
• Canonical patterns the exam recycles:
  • Block transfer: LEA SI, SRC / LEA DI, DST / MOV CX, N / CLD / REP MOVSB.
  • Largest element: load first into AL; loop CMP AL,[SI] / JAE skip / MOV AL,[SI] — JAE for unsigned, JGE for signed.
  • Sum with carry: ADD AL,[SI] / ADC AH, 0 — multiprecision via ADC/SBB chains.
  • BCD packed addition: ADD AL, BL / DAA.
  • ASCII↔binary: AND 0FH strips '0'–'9'; OR 30H restores; AAM splits AL into AH:AL digits (divide by 10).
  • Delay loops: MOV CX, N / L: LOOP L — time = N × (LOOP cycles)/f_clk.
• Procedures: CALL pushes IP (near) or CS:IP (far); parameters via registers or stack (BP frame: PUSH BP / MOV BP,SP / […BP+4] = first parameter); preserve registers with PUSH/POP discipline.
• Macros vs procedures: macro = inline expansion (faster, larger code, no CALL overhead); procedure = single copy (CALL/RET time cost).
• Modular flow: .ASM → assembler (.OBJ) → linker (.EXE) → loader; DEBUG/emulators for tracing (TF single-step).

§ 6.68086 Memory & I/O Interfacing

Memory banks

• 1 MB split into two 512 KB banks: even/lower bank (D₀–D₇, enabled by A₀ = 0) and odd/upper bank (D₈–D₁₅, enabled by BHE̅ = 0).

• Misaligned word (odd address) costs two bus cycles — why data alignment matters.
• Address decoding: full (all lines → unique map) vs partial (aliases); 74138 decoders / PROM decoding; chip-select arithmetic: a 64 KB device needs A₀–A₁₅ internally, decoder on A₁₆–A₁₉ — compute address ranges (standard numericals).
• EPROM placed at the top (must contain FFFF0H reset vector); RAM at the bottom (IVT at 00000H).

I/O interfacing

• 8255A PPI (the canonical port chip): three 8-bit ports A, B, C (C splittable); control word at the fourth address. Mode 0 simple I/O, Mode 1 strobed (handshake via port C), Mode 2 bidirectional (port A); BSR mode sets/resets individual PC bits. Control word: bit 7 = 1 for mode set (e.g., 80H = all ports output, mode 0; 9BH = all input).
• Supporting cast: 8254 timer, 8259A PIC (§6.4), 8237 DMA, 8251 USART — recognize roles.

§ 6.7Microcontrollers & the 8051: Overview

8051 (MCS-51, Intel 1981) feature card — quote these numbers

• 8-bit CPU; on-chip 4 KB ROM, 128 B RAM; two 16-bit timers (T0, T1); 4 × 8-bit I/O ports (P0–P3, 32 lines); full-duplex UART; 5 interrupt sources (2 external, 2 timer, 1 serial) with 2 priority levels; 16-bit PC and DPTR; 64 KB external program + 64 KB external data reach; 40-pin DIP.
• Clock: each machine cycle = 12 oscillator periods → 12 MHz crystal = 1 µs cycle; standard serial crystal 11.0592 MHz.
• Family: 8031 (ROM-less), 8751 (EPROM), 8052 (8K ROM, 256 B RAM, third timer T2), 89C51/89S52 (flash, ISP).
• Pins to know: EA̅ (0 = all code external — mandatory for 8031), PSEN̅ (external program-memory read strobe), ALE (latch A0–A7 from P0), RST (high ≥ 2 cycles).

§ 6.88051 Architecture, Register Set & Memory Organization

Internal RAM map (128 bytes, 00–7FH)

• 00–1FH: four register banks (Bank 0–3, R0–R7 each); active bank chosen by PSW bits RS1 RS0 (fast context switch for interrupts).
• 20–2FH: bit-addressable area — 16 bytes = 128 bits, bit addresses 00–7FH (the Boolean processor's data field).
• 30–7FH: scratch-pad general RAM (default stack growth region).
• 8052 adds 80–FFH indirect-only upper RAM (overlaps SFR addresses, separated by addressing mode).

SFRs (80–FFH, direct-only)

• A/ACC (E0H) accumulator, B (F0H) MUL/DIV partner, PSW (D0H), SP (81H — resets to 07H, pre-increments on PUSH), DPTR = DPH:DPL (16-bit pointer), P0–P3 (80, 90, A0, B0H), plus TMOD/TCON/TH/TL (§6.15), SCON/SBUF (§6.16), IE/IP (§6.14), PCON (SMOD, idle/power-down bits).
• SFRs at addresses ending in 0H/8H are bit-addressable (P0–P3, PSW, ACC, B, TCON, SCON, IE, IP).

Ports (HW behaviour asked often)

• P0: open-drain — needs external pull-ups as plain I/O; multiplexed AD0–AD7 in external-bus mode.
• P1: dedicated I/O, internal pull-ups.
• P2: I/O or high address byte A8–A15.
• P3: I/O + alternates — P3.0 RXD, P3.1 TXD, P3.2 INT0̅, P3.3 INT1̅, P3.4 T0, P3.5 T1, P3.6 WR̅, P3.7 RD̅.
• Quasi-bidirectional: write 1 to a pin before using it as input; read-pin vs read-latch (read-modify-write instructions read the latch).

§ 6.98051 Addressing Modes

• Memory-space selectors: plain MOV = internal RAM/SFR; MOVX = external data RAM (uses RD̅/WR̅); MOVC = code/program memory (read-only, uses PSEN̅) — the Harvard separation in instruction form.

§ 6.108051 Data-Transfer Instructions

• MOV family: MOV A,Rn / MOV Rn,A / MOV direct,direct (memory-to-memory — 8086 lacks this!) / MOV @Ri,#data / MOV DPTR,#data16. Flags unaffected (except writes to PSW/A affecting P).
• External & code memory: MOVX A,@DPTR; MOVX @DPTR,A; MOVX A,@Ri (page mode, P2 supplies A8–A15); MOVC A,@A+DPTR; MOVC A,@A+PC (table within code).
• Stack: PUSH direct / POP direct (direct addresses only — PUSH ACC, not PUSH A in many assemblers); SP increments before PUSH (grows upward), decrements after POP — §6.13.
• Exchange: XCH A, source (full byte swap with A); XCHD A,@Ri — swaps lower nibbles only (BCD juggling); SWAP A — swaps A's nibbles (4-bit rotate).
• Lookup-table idiom: MOV DPTR,#TABLE / MOV A,index / MOVC A,@A+DPTR — 7-segment patterns, linearization tables.

§ 6.118051 Arithmetic & Logic Instructions

Arithmetic (A-centric; affect CY, AC, OV, P)

• ADD A,src / ADDC A,src (with carry — multibyte chains); SUBB A,src (always subtracts borrow — CLR C first for a plain subtract; there is no SUB!).
• INC / DEC on A, Rn, direct, @Ri; INC DPTR (16-bit, no DEC DPTR!); INC/DEC do not touch CY.
• MUL AB: A×B → B:A (high:low); OV = 1 if product > FFH; CY cleared. DIV AB: A÷B → quotient in A, remainder in B; OV flags divide-by-zero.
• DA A: decimal adjust after ADD/ADDC only — adds 06/60H per nibble-carry rules for packed BCD.
• Signed overflow: OV set when carry into MSB ≠ carry out (two-positive→negative etc.).

Logic (flags: only P via A, except RRC/RLC)

• ANL, ORL, XRL — A,src or direct,A or direct,#data (logic directly on RAM/SFRs — masking port bits without touching A).
• CLR A, CPL A; rotates: RL A / RR A (8-bit circular) and RLC A / RRC A (9-bit through carry — multibyte shifts, serial bit-banging); SWAP A (= RL A ×4).
• Masking idioms: ANL clears selected bits (AND with 0), ORL sets (OR with 1), XRL toggles; ANL P1,#0F0H clears P1 low nibble in place.

§ 6.12Bit-Level & Control-Transfer Instructions

Boolean processor (the 8051's trademark)

• Operates on 128 RAM bits (20–2FH) + bit-addressable SFR bits (e.g., P1.3, TR0, EA); carry CY acts as the 1-bit accumulator.
• Instructions: SETB bit / CLR bit / CPL bit; MOV C,bit / MOV bit,C; ANL C,bit / ANL C,/bit (complemented operand); ORL C,bit; JB bit,rel / JNB / JBC (jump-if-bit-then-clear — atomic flag test); JC/JNC.
• Single-instruction relay logic: MOV C,P1.0 / ANL C,P1.1 / MOV P2.0,C implements AND of two inputs to an output — no byte masking needed.

Control transfer

• Jumps by reach: SJMP (relative, −128…+127), AJMP (absolute, same 2 KB page, 11-bit), LJMP (anywhere in 64 KB, 16-bit); JMP @A+DPTR (computed dispatch). Same trio for calls: ACALL / LCALL.
• Conditional (all relative, ±127): JZ/JNZ (test A, since no Z flag), JC/JNC, bit jumps above, and the loop pair:
  • DJNZ Rn,rel / DJNZ direct,rel — decrement, jump if not zero: the canonical delay/loop primitive.
  • CJNE A,#data,rel (also A,direct / Rn,#data / @Ri,#data) — compare-jump-if-not-equal; sets CY = 1 if first operand < second → magnitude comparison follows with JC/JNC.
• NOP (1 cycle — delay padding); RET / RETI in §6.13–6.14.

§ 6.13Stack Operations & Subroutines

• Stack lives in internal RAM, grows upward; SP resets to 07H → first PUSH lands at 08H (inside Bank 1 — re-initialize, e.g., MOV SP,#5FH or #30H, when banks/bit area are needed).
• PUSH direct: SP←SP+1, then store; POP direct: read, then SP←SP−1 (pre-increment/post-decrement — opposite vertical sense to the 8086's downward stack).
• LCALL/ACALL: push PC (low byte first, then high) = return address, load new PC. RET: pop PC high then low. RETI additionally clears the interrupt-in-progress logic — using RET in an ISR blocks same/lower-priority interrupts thereafter (classic trap).
• Nesting depth limited by RAM ceiling 7FH; each call costs 2 bytes; register preservation discipline: PUSH ACC / PUSH PSW … POP in reverse; or switch register banks (PSW RS bits) in the ISR for zero-cost context save.
• Parameter passing: registers (fast), fixed RAM, or stack; subroutine archetypes — software delay (nested DJNZ), code-table reads, BCD/ASCII conversion.
• Delay arithmetic example (12 MHz → 1 µs/cycle): MOV R2,#250 / L: DJNZ R2,L ≈ 250 × 2 µs = 500 µs (DJNZ = 2 cycles).

§ 6.148051 Interrupts

Reset vector = 0000H; vectors are 8 bytes apart — short ISRs fit in place, longer ones LJMP out.

• IE register (A8H, bit-addressable): EA | — | ET2 | ES | ET1 | EX1 | ET0 | EX0 — EA must be 1 plus the individual enable (two-key system). Example: MOV IE,#10000110B enables INT1 and Timer 0.
• IP register (B8H): set bit → high priority; high can preempt low; equals resolve by the default order above. Two levels only.
• External-interrupt triggering (TCON): IT0/IT1 = 0 → level (low) triggered (source must release before RETI or it re-fires); = 1 → falling-edge triggered (IE0/IE1 latched, auto-cleared on vectoring).
• Timer flags TF auto-clear on vectoring; serial RI/TI must be cleared in software (the ISR must test which one fired).
• Hardware ISR entry: PC pushed (only PC! — save PSW/ACC yourself), vector loaded; RETI ends it (§6.13).
• Latency: 3–8 machine cycles (instruction completion + vectoring).

§ 6.158051 Timers/Counters

• Two 16-bit up-counters T0 (TH0:TL0), T1 (TH1:TL1); count machine cycles (f_osc/12) as a timer, or external pulses on T0/T1 pins (P3.4/3.5, max f_osc/24) as a counter — selected by the C/T̅ bit.
• TMOD (89H, not bit-addressable): upper nibble T1, lower T0; each nibble = GATE | C/T̅ | M1 | M0. GATE = 1 → run only while INTx̅ pin high (hardware gating — pulse-width measurement).
• TCON (88H, bit-addressable): TF1 TR1 TF0 TR0 (+ IE/IT bits §6.14) — TRx run control (SETB TR0), TFx overflow flags.

• Recipe (mode 1, polling): MOV TMOD,#01H → load THx:TLx → SETB TRx → JNB TFx,$ → CLR TRx → CLR TFx → reload for the next round. Interrupt version: ET0/EA set, reload inside the ISR.
• Square wave of period T: toggle a pin each T/2 overflow; frequency measurement: count pulses (counter mode) over a gated 1 s timer window.

§ 6.168051 Serial Communication & RS232

• Full-duplex UART: TXD (P3.1), RXD (P3.0); SBUF (99H) is two registers at one address (write → transmit shift register; read → receive buffer; double-buffered receive).
• SCON (98H, bit-addressable): SM0 SM1 | SM2 (multiprocessor) | REN (receive enable) | TB8 RB8 (9th bits) | TI RI (transmit/receive complete — software-cleared).

11.0592 MHz exists precisely because 11.0592M/12/32 = 28800 divides into standard baud rates exactly; SMOD (PCON.7) doubles the rate.

• Transmit: MOV SBUF,A → poll JNB TI,$ → CLR TI. Receive: SETB REN → JNB RI,$ → MOV A,SBUF → CLR RI. Interrupt-driven via vector 0023H (test TI vs RI inside).
• RS-232: the EIA standard — logic 1 = −3…−15 V (mark), logic 0 = +3…+15 V (space): inverted, bipolar → TTL-incompatible. MAX232 level shifter (on-chip charge pumps generate ±10 V from +5 V with four 1–10 µF capacitors; two drivers + two receivers) sits between 8051 TXD/RXD and the DB9 (pin 2 RXD, 3 TXD, 5 GND on PC side); null-modem cross TX↔RX. Handshake lines (RTS/CTS, DTR/DSR) optional; distance ≤ ~15 m, rates to 115.2 kbaud.

§ 6.17Interfacing: LED, LCD, Keyboard, Stepper Motor

LED & 7-segment

• Single LED: series resistor R = (V_CC − V_F)/I_F (5 V, 2 V, 10 mA → 330 Ω); ports sink better than they source → common practice: active-low drive (LED to V_CC through R, pin sinks). P0 needs pull-ups.
• 7-segment: common-anode (segment lit by 0) vs common-cathode (lit by 1); code table in ROM read by MOVC; multiplexed multi-digit: one digit at a time > ~50 Hz refresh — persistence of vision; transistor drivers per digit.

LCD (16×2, HD44780)

• Pins: RS (0 = command, 1 = data), R/W̅ (usually grounded = write), EN (falling-edge latches the byte), D0–D7 (or 4-bit mode on D4–D7 — two nibbles per byte, saves pins), V_EE contrast pot.
• Command set to quote: 38H 8-bit/2-line/5×7 · 0EH display+cursor on · 01H clear · 06H entry mode (increment) · 80H cursor to line-1 home (C0H = line 2).
• Sequence: command/data on port → set RS → pulse EN high→low → delay (or poll busy flag D7 with R/W̅ = 1). Clear/home commands need ~1.6 ms; others ~40 µs.

Matrix keyboard (4×4)

• 16 keys on 8 lines (4 rows out + 4 columns in with pull-ups) instead of 16. Scanning: ground one row at a time, read columns; a low column identifies (row, col) → key code via table.
• Essentials: debouncing (~10–20 ms wait or double-read — contacts bounce mechanically), ghosting/rollover limits (diodes for n-key rollover), wait-for-release to avoid repeats; interrupt variant: all rows low, columns AND-ed into INT0̅.

Stepper motor

• Brushless motor moving in discrete steps — open-loop position control. Unipolar (center-tapped, simple drive) vs bipolar (H-bridge, more torque).
• Drive sequences (4-coil unipolar): wave (one coil: 8→4→2→1), full-step (two coils: 9→C→6→3 — more torque), half-step (alternating 1-and-2 coils, 8 patterns → halves the step angle, doubles resolution). Reverse the sequence to reverse rotation.
• Interface: port nibble → ULN2003 Darlington array (or transistors) with freewheeling diodes (inductive kick) → coils; never drive coils from port pins directly.
• Stepper arithmetic $$ \text{steps/rev} = \frac{360^\circ}{\text{step angle}}\ \ (1.8^\circ \to 200);\qquad \text{RPM} = \frac{60\,f_{step}}{\text{steps/rev}} $$
  Speed set by inter-step delay (DJNZ/timer); too fast → missed steps (torque–speed curve).

§ 6.18Unit-6 Formula Sheet

§ 6.19Quick Revision Notes — Unit 6 in 25 Points

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