Unit 2 — IC Fabrication, Thin Films, MOS Technology & VLSI: Complete Exam Notes

§ 2.1Crystal Growth & Wafer Preparation

VLSI requires defect-free single-crystal silicon. Raw quartzite is reduced to metallurgical-grade Si (98%) in an arc furnace, converted to trichlorosilane (SiHCl₃), fractionally distilled, and reduced by H₂ (Siemens process) to electronic-grade polysilicon (impurities < ppb).

Czochralski (CZ) growth — the workhorse

• Polysilicon melted in a fused-silica (SiO₂) crucible at ~1420 °C; a seed crystal of the desired orientation ((100) for MOS, (111) for bipolar) is dipped and slowly pulled while rotating (pull rate ~mm/min, counter-rotation of crucible).
• Neck (Dash technique) eliminates dislocations; diameter controlled by pull rate and temperature.
• Crucible dissolution introduces oxygen (~10¹⁸ cm⁻³) and carbon — oxygen is partly useful: internal gettering of metallic impurities and mechanical strengthening.
• Dopant added to the melt; incorporation governed by the segregation coefficient.

where X is the melt fraction solidified. Since \(k_0 < 1\) for most dopants (B: 0.8, P: 0.35, As: 0.3, Sb: 0.023), the dopant is rejected into the melt and the ingot tail is more heavily doped — axial non-uniformity is intrinsic to CZ.

Float-Zone (FZ) growth

• An RF-heated molten zone traverses a vertical polysilicon rod; no crucible → highest purity, very low oxygen.
• Impurities (k₀ < 1) travel with the zone to the rod end — zone refining; after n passes purity improves dramatically.
• Used for high-resistivity material: power devices, detectors, THz components. Limitation: smaller diameters, costlier, more fragile growth.

Wafer preparation

Ingot → grinding to diameter → flat/notch marking orientation and type → wire-saw slicing → lapping → edge rounding → chemical-mechanical polishing to mirror finish → RCA cleaning (SC-1: NH₄OH+H₂O₂ removes organics/particles; SC-2: HCl+H₂O₂ removes metals; HF dip strips native oxide). Crystal planes are described by Miller indices; (100) preferred for MOS due to lowest interface-state density.

§ 2.2Epitaxy

Epitaxy ("arranged upon") = growth of a single-crystal layer that replicates the substrate's crystallographic orientation. Homoepitaxy: Si on Si; heteroepitaxy: GaN on sapphire, SiGe on Si (strain if lattice-mismatched — basis of strained-Si mobility enhancement; relaxation beyond the critical thickness creates misfit dislocations).

Vapor-Phase Epitaxy (VPE/CVD)

• Standard Si source chemistries: \( \text{SiCl}_4 + 2\text{H}_2 \rightarrow \text{Si} + 4\text{HCl} \) (~1200 °C, reversible — HCl can etch), SiHCl₃, SiH₂Cl₂, or silane \( \text{SiH}_4 \rightarrow \text{Si} + 2\text{H}_2 \) (~650–900 °C, irreversible, lower-T).
• Growth regimes: low T — surface-reaction limited (Arrhenius, T-sensitive); high T — mass-transport limited (T-insensitive, preferred for uniformity).
• In-situ doping with AsH₃, PH₃, B₂H₆. Issues: autodoping (dopant evaporating from buried layers re-incorporates) and pattern shift.
• Classic use: lightly doped n-epi over n⁺ buried layer for bipolar; p-epi on p⁺ substrate for latch-up-resistant CMOS.

Molecular Beam Epitaxy (MBE)

• Effusion (Knudsen) cells evaporate elemental beams in ultra-high vacuum (~10⁻¹⁰–10⁻¹¹ Torr) onto a heated substrate; shutters give monolayer (atomic-layer) control.
• Low growth rate (~1 µm/h ≈ 1 monolayer/s); in-situ RHEED oscillations count monolayers.
• The tool that built quantum wells, superlattices, HEMT and QW-laser structures (links to Unit 1 §1.13–1.14). Drawback: throughput and cost.

MOCVD / MOVPE

• Metal-organic precursors — trimethylgallium (TMGa), trimethylindium + hydrides (AsH₃, NH₃): \( \text{(CH}_3)_3\text{Ga} + \text{AsH}_3 \rightarrow \text{GaAs} + 3\text{CH}_4 \).
• Workhorse for production III–V and GaN LED/laser growth: faster than MBE, no UHV, excellent large-area uniformity; hazard: toxic hydrides.

Liquid-Phase Epitaxy (LPE)

Growth from a supersaturated molten solution (e.g., GaAs from Ga-rich melt) on a sliding graphite boat; near-equilibrium, simple and cheap, thick high-quality layers; poor thickness control for nm structures — historical workhorse for early LEDs/lasers.

§ 2.3Thermal Oxidation — Deal–Grove Model

Silicon's decisive advantage: it grows a high-quality native insulator. Thermal SiO₂ (amorphous, ε_r = 3.9, E_g ≈ 9 eV, breakdown ~10⁷ V/cm) serves as gate dielectric, diffusion/implant mask, surface passivation and isolation.

• Dry oxidation: slow, dense, lowest interface-trap density → gate oxides.
• Wet/steam oxidation: ~5–10× faster (H₂O has much higher solubility in SiO₂) but slightly inferior quality → field/masking oxides.
• Rate increases with temperature, pressure (HiPOx), (111) orientation, and heavy doping (chlorine ambient improves quality, getters Na⁺).
• Thin-oxide regime (< ~20 nm dry) grows faster than Deal–Grove predicts (initial rapid-growth anomaly).
• Oxide charges (memorize the four): interface-trapped \(Q_{it}\), fixed oxide \(Q_f\) (near interface, positive), oxide-trapped \(Q_{ot}\), mobile ionic \(Q_m\) (Na⁺, K⁺ — the historic V_T-drift culprit). All shift flat-band/threshold voltage: \( \Delta V = -Q/C_{ox} \).
• Oxide colour chart (interference) gives quick thickness estimates; ellipsometry for precision.

§ 2.4Lithography

Lithography transfers the designed pattern from a mask/reticle to a radiation-sensitive photoresist on the wafer — the step that defines feature size and dominates fab cost (perhaps one-third of processing).

Process sequence

1. Dehydration bake + HMDS adhesion promoter
2. Spin-coat resist (thickness ∝ 1/√spin-speed)
3. Soft bake (solvent removal)
4. Align & expose (contact / proximity / projection)
5. Post-exposure bake (CAR resists; reduces standing waves)
6. Develop (TMAH)
7. Hard bake → etch or implant → strip (O₂ plasma ashing / piranha)

Exposure systems and resolution

• Contact printing: resolution ~λ-scale but mask damage; proximity: gap g limits resolution \( \approx \sqrt{\lambda g} \); projection (steppers/scanners): industry standard, reduction optics (4–5×).

Resolution improves with shorter λ and larger numerical aperture, but DOF collapses as NA² — the central lithographic trade-off. Wavelength roadmap: Hg g-line 436 nm → i-line 365 nm → KrF 248 nm → ArF 193 nm (+ immersion, water n = 1.44 raises effective NA to ~1.35) → EUV 13.5 nm (Sn-plasma source, all-reflective Mo/Si multilayer optics, vacuum operation; HVM since ~2019).

Resolution-enhancement techniques (RET): phase-shift masks, optical proximity correction (OPC), off-axis illumination, multiple patterning (LELE, SADP/SAQP) — these pushed k₁ toward its ~0.25 limit.

Non-optical lithography

• Electron-beam: direct-write, no mask, ~nm resolution (PMMA resist); limited by proximity effect (backscattered-electron exposure) and serial throughput → mask making & research.
• X-ray: 1:1 proximity printing with ~1 nm λ; membrane-mask difficulty.
• Nanoimprint (NIL): mechanical mold pressing — high resolution, low cost, defectivity challenge.

§ 2.5Doping: Diffusion & Ion Implantation

Thermal diffusion

High-temperature (900–1200 °C) introduction of dopants governed by Fick's laws: \( J = -D\,\partial C/\partial x \), \( \partial C/\partial t = D\,\partial^2 C/\partial x^2 \), with \( D = D_0 e^{-E_a/kT} \) (E_a ≈ 3–4 eV for substitutional dopants).

Two-step practice: shallow erfc predep (often capped by C_s = solid solubility) followed by Gaussian drive-in that pushes the junction deeper while lowering surface concentration. Junction depth: solve \(C(x_j) = C_B\) (background). Characteristic length \( \sqrt{Dt} \); for sequential steps, total \( Dt = \sum D_it_i \). Limitations: isotropic (lateral spread ≈ 0.75–0.8 x_j under the mask), poor dose precision, high thermal budget.

Ion implantation — the modern standard

• Dopant ions accelerated (1 keV–1 MeV), mass-separated by analyzing magnet, raster-scanned; dose measured by integrated beam current — precision < 1%, low temperature, masked by resist itself.
• Depth profile ≈ Gaussian around the projected range R_p with straggle ΔR_p:

• Energy loss = nuclear stopping (dominant for heavy/slow ions; causes damage) + electronic stopping (light/fast). R_p increases with energy, decreases with ion mass.
• Channeling: ions steered down open crystal axes penetrate anomalously deep — suppressed by 7° tilt, screen oxide, or pre-amorphization.
• Lattice damage (amorphization at high dose) must be repaired and dopants activated by annealing — RTA (~1000 °C, seconds) or spike/laser anneal to limit diffusion; transient-enhanced diffusion (TED) from point defects is the shallow-junction enemy.
• Applications: V_T-adjust implant (precise shallow dose), self-aligned source/drain (gate as mask), wells, halo/LDD, SIMOX oxygen implant for SOI.

§ 2.6Etching

Etching removes material selectively through the resist/hard-mask windows. Two figures of merit:

Wet (chemical) etching

• Isotropic (A ≈ 0) → undercut ≈ film thickness; excellent selectivity; cheap, batch.
• Standard chemistries: SiO₂ — HF / buffered HF (BHF = HF + NH₄F); Si — HNA (HNO₃ oxidizes + HF dissolves); Si₃N₄ — hot H₃PO₄ (180 °C); Al — H₃PO₄-based mix.
• Anisotropic crystallographic etchants (KOH, TMAH, EDP): etch (100) ≫ (111) (up to 400:1) → V-grooves and cavities bounded by (111) planes at 54.74°; heavily boron-doped Si acts as etch stop — the foundation of bulk MEMS micromachining.

Dry (plasma) etching

• Plasma etching: purely chemical via radicals (e.g., CF₄ → F* etches Si as volatile SiF₄) — isotropic, gentle.
• Sputter/ion milling: purely physical Ar⁺ bombardment — anisotropic but unselective, damaging.
• Reactive Ion Etching (RIE): the synergy — ions damage/activate the surface vertically while radicals etch chemically; sidewall polymer passivation (fluorocarbon from CHF₃, C₄F₈) blocks lateral attack → anisotropic and selective. The VLSI default.
• Deep RIE (Bosch process): alternating SF₆ etch / C₄F₈ passivation cycles → aspect ratios > 50:1 (scalloped walls) for TSVs and MEMS.
• End-point detection: optical emission spectroscopy / laser interferometry. Concerns: loading effect, micro-trenching, plasma charge damage to gate oxides.

§ 2.7Isolation Methods

Adjacent devices must not interact electrically. Evolution of isolation:

• Junction (diffused) isolation — bipolar era: p⁺ moats surround each n-epi island; the island-substrate junction is kept reverse-biased. Penalty: large area, junction capacitance, leakage at temperature.
• LOCOS (LOCal Oxidation of Silicon): Si₃N₄ (over a pad oxide) masks active areas; thick field oxide grown elsewhere; a channel-stop implant under the field oxide raises parasitic-FET V_T.
  Bird's beakLateral oxidant diffusion under the nitride edge lifts it, wasting ~0.1–0.5 µm per edge and creating the characteristic taper; the Kooi (white-ribbon) nitride defect degrades subsequent gate oxide. These limits killed LOCOS below ~0.35 µm.
• STI (Shallow Trench Isolation) — the modern standard (< 0.25 µm): RIE a shallow trench (~0.3–0.5 µm) → liner oxidation → CVD/HDP oxide fill → CMP planarization (nitride as polish stop). Fully planar, no bird's beak, tight pitch.
• SOI (Silicon-On-Insulator): devices in a thin Si film over buried oxide (BOX) — made by SIMOX (O⁺ implant + anneal) or Smart-Cut (H⁺ implant + wafer bonding + split). Benefits: near-total isolation, no latch-up, lower junction capacitance (speed/power), radiation hardness; FD-SOI offers back-gate biasing. Costs: wafer price, self-heating, floating-body (history) effect in PD-SOI.
• Trench + buried-layer isolation in BiCMOS/power ICs; deep trenches also isolate high-voltage islands.

§ 2.8Metallization & Bonding

Metallization

• Functions: gate electrodes (historically Al → poly-Si → metal gates again at high-k nodes), contacts, and interconnect (now 10+ levels).
• Aluminium era: ρ ≈ 2.7 µΩ·cm, good oxide adhesion, ohmic on p-Si. Problems: junction spiking (Si dissolves into Al — cured by Al-1%Si or barrier metals TiN/TiW), electromigration — momentum transfer from electron wind moves atoms, opening voids/hillocks. Median time to failure follows Black's equation:

• Cu addition (Al-0.5%Cu) and bamboo grain structure improve EM life.
• Copper era (≥ 1997): ρ ≈ 1.7 µΩ·cm, ~10× EM resistance — but Cu cannot be plasma-etched and diffuses fast in Si/SiO₂ → damascene process: etch trenches/vias in dielectric → Ta/TaN diffusion barrier + Cu seed (PVD) → electroplate Cu → CMP. Dual damascene fills via + line together.
• Low-k dielectrics (carbon-doped oxide, porous SiO₂, air gaps) cut RC interconnect delay \( \tau \propto \rho\varepsilon \) — interconnect, not transistor, delay dominates modern chips.
• Silicides (TiSi₂, CoSi₂, NiSi) lower S/D and poly sheet resistance; salicide = self-aligned silicide. Contact plugs: CVD tungsten (W) with TiN liner.

Bonding & packaging

• Wire bonding (chip pad → lead frame): thermocompression (Au, heat+pressure, ball–wedge), ultrasonic (Al wire, room T, wedge–wedge), thermosonic (Au ball, heat+ultrasound — the production standard). Watch for Au–Al intermetallics ("purple plague", Au₂Al... AuAl₂) causing brittle failure.
• Tape-Automated Bonding (TAB): all leads bonded at once to a flexible tape — thin, gang bonding.
• Flip-chip (C4): solder bumps over the whole die face, flipped onto the substrate, reflowed, underfilled — shortest interconnect (lowest L), highest I/O density, best for high-speed/power; rework is harder.
• Package families: DIP → QFP/SOIC (surface mount) → BGA → CSP/WLP → 2.5D/3D (TSV through-silicon vias, interposers, stacked memory). Hermetic ceramic vs plastic molding; die attach: eutectic Au-Si or epoxy.

§ 2.9Thin-Film Deposition Techniques

Physical Vapor Deposition (PVD)

• Thermal evaporation: source heated (resistive boat / e-beam) in vacuum ~10⁻⁶ Torr; long mean free path → line-of-sight, poor step coverage; e-beam version handles refractory metals; alloy stoichiometry drifts (different vapor pressures).
• Sputtering: Ar⁺ ions (DC for metals, RF for insulators, magnetron for rate) knock target atoms off — momentum transfer, not heat. Better adhesion, alloy/compound stoichiometry preserved, better step coverage than evaporation; reactive sputtering (Ar + N₂/O₂) deposits TiN, AlN, ITO. Sputter yield = atoms ejected per incident ion.

Chemical Vapor Deposition (CVD)

Step coverage / conformality ranking: ALD > LPCVD > PECVD ≈ sputtering > evaporation.

Other routes: spin-on (resists, SOG, sol-gel), electroplating (damascene Cu), PLD (research oxides). Film stress (tensile/compressive) and adhesion are key quality metrics; thickness via stylus profilometry, ellipsometry, or quartz-crystal monitor during evaporation.

§ 2.10Characterization: XRD, TEM, SEM, EDX

X-Ray Diffraction (XRD)

• Cu Kα (λ = 1.5406 Å) typical; θ–2θ scan identifies phases and crystal structure (peak positions → d-spacings → lattice constant), texture (preferred orientation), strain (peak shift), and crystallinity (amorphous = broad halo).
• Crystallite size from peak broadening — Scherrer equation:

• Non-destructive, no vacuum; variants: GIXRD for thin films, XRR for thickness/density, rocking curves for epitaxial quality.

Scanning Electron Microscopy (SEM)

• Focused e-beam (1–30 keV) rastered; signals: secondary electrons (SE, <50 eV, surface-sensitive → topography), backscattered electrons (BSE, ∝ Z → composition contrast), characteristic X-rays (→ EDX).
• Resolution ~1–10 nm; large depth of field (the "3D look"); insulating samples need conductive coating (Au/C) or low-vacuum mode to avoid charging. Cross-section SEM measures film thickness and etch profiles.

Transmission Electron Microscopy (TEM)

• High-energy beam (80–300 keV) transmitted through an electron-transparent (<100 nm) specimen — laborious prep (FIB lift-out, ion milling).
• Atomic resolution (<0.1 nm aberration-corrected): lattice fringes, interfaces, dislocations; SAED (selected-area electron diffraction) gives local crystallography — spots = single crystal, rings = polycrystal, diffuse = amorphous. HAADF-STEM gives Z-contrast atomic maps.

Energy-Dispersive X-ray Spectroscopy (EDX/EDS)

• Attached to SEM/TEM; the beam ejects core electrons; relaxation emits characteristic X-rays whose energies follow Moseley's law \( \sqrt{\nu} \propto (Z - \sigma) \) → elemental identification (qualitative + semi-quantitative, ~0.1–1 wt% detection), line scans and elemental maps.
• Limits: poor for light elements (Z < ~5, Be window absorbs), peak overlaps; interaction volume (~µm³ in SEM) limits spatial resolution.

§ 2.11Thin-Film Active & Passive Devices

Passive components

• Measured by four-point probe: \( R_\square = (\pi/\ln 2)(V/I) = 4.532\,V/I \) for thin films, collinear equal-spaced probes.
• Thin-film resistors: NiCr, TaN, SnO₂, cermet (Cr-SiO) — tight tolerance, low TCR (±10–100 ppm/°C), laser-trimmable; superior precision/noise vs diffused or poly resistors (which have large TCR and voltage coefficients).
• Thin-film capacitors: MIM (metal–insulator–metal) with SiO₂/Si₃N₄/Ta₂O₅/HfO₂; \( C = \varepsilon_0\varepsilon_r A/d \); merits: low parasitics, no voltage dependence (vs MOS/junction capacitors). MIS and interdigitated variants for RF.
• Thin-film inductors: spiral metal traces, Q limited by series resistance and substrate eddy currents.
• Hybrid microcircuits: thin-film (sputtered, precise) vs thick-film (screen-printed pastes fired ~850 °C, cheap) on alumina substrates.

Active thin-film devices — the TFT

• Thin-Film Transistor: MOSFET-like device whose channel is a deposited semiconductor film on glass/plastic — no single-crystal wafer needed. Structures: staggered/inverted-staggered (bottom-gate a-Si standard).
• Channel materials: a-Si:H (µ ≈ 0.5–1 cm²/V·s — pixel switches), LTPS poly-Si by excimer-laser crystallization (µ ≈ 50–100 — drivers, AMOLED), IGZO amorphous oxide (µ ≈ 10, ultra-low leakage), organic OTFTs (flexible).
• Same square-law I–V as the MOSFET but lower µ and notable subthreshold/stability (bias-stress V_T shift) issues; this is the active-matrix backplane technology of §1.16's displays.
• Other thin-film actives: poly-Si diodes, thin-film solar cells (a-Si, CdTe, CIGS), SAW devices on piezo films (ZnO/AlN).

§ 2.12MOS Technology & VLSI

• Integration eras by device count: SSI (<10²) → MSI → LSI (10³–10⁵) → VLSI (10⁵–10⁶+) → ULSI/GSI (10⁹+ today).
• Moore's law (1965): transistor count per chip doubles ~every 18–24 months — an economic observation that became the industry roadmap; now sustained by 3D (FinFET → gate-all-around nanosheets, 3D-NAND, chiplets) rather than pure 2D shrink.
• Why MOS conquered bipolar for VLSI: self-isolation (no isolation islands needed), smaller footprint, near-zero static gate current, simpler process (fewer masks), and CMOS's negligible static power.
• Self-aligned silicon-gate process (the historical turning point): poly-Si gate is deposited before S/D implantation and acts as the implant mask → gate–S/D overlap capacitance minimized, alignment-insensitive.
• Modern enhancements appearing in exams as keywords: high-k/metal gate (HfO₂ replaces SiO₂ below ~1.2 nm to stop gate tunneling; EOT = equivalent oxide thickness \( t_{high\text{-}k}\cdot 3.9/\varepsilon_{high\text{-}k} \)), strained Si channels, FinFET (tri-gate) electrostatics, FD-SOI.
• Yield economics: die cost ∝ 1/yield; Y ≈ e^{−AD} (Poisson, defect density D, die area A) — why small dies and cleanrooms (Class 1/ISO) matter.

§ 2.13Scaling of MOS Devices

Dennard's constant-field scaling (1974): shrink every dimension and voltage by k (>1) and raise doping by k so internal fields stay constant — devices get faster, denser and cooler per gate simultaneously.

Why ideal scaling broke down — short-channel effects (SCE):

• Threshold-voltage roll-off (S/D depletion regions share channel charge) and DIBL (drain-induced barrier lowering — V_T falls with V_DS).
• Subthreshold leakage: swing \( S = (kT/q)\ln 10 \,(1 + C_{dep}/C_{ox}) \ge 60\ \text{mV/dec at 300 K} \) cannot scale — V_T can't drop with V_DD without exponential leakage; hence the power wall and "dark silicon".
• Velocity saturation (I_D becomes ∝ (V_GS−V_T), not squared), mobility degradation by vertical field, hot-carrier injection (mitigated by LDD spacers), gate-oxide tunneling (→ high-k), punch-through (→ halo implants), gate-line edge roughness and dopant fluctuation variability.
• Interconnect RC delay scales up relative to gates — Cu/low-k and repeaters (links §2.8).
• Geometric responses: FinFET/GAA wrap the gate around the channel to restore electrostatic control (better S, less DIBL).

§ 2.14NMOS & CMOS Structures and Fabrication

NMOS technology (historical baseline)

• Single n-channel device family on p-substrate; logic = NMOS driver + load (resistor → saturated/linear enhancement load → depletion load, the best: gate tied to source, nearly constant-current pull-up).
• Classic flow: field oxidation (LOCOS) → gate oxide → poly gate → self-aligned n⁺ S/D implant → CVD oxide → contacts → metal.
• Fatal flaw: static power — pull-up conducts whenever output is low; ratioed logic (output-low level depends on driver/load size ratio).

CMOS structures

• Complementary NMOS + PMOS pair needs both substrate polarities → wells: n-well (PMOS in well; cheapest, NMOS keeps high-mobility substrate), p-well, or twin-well/twin-tub (modern: each device's body independently optimized), plus retrograde wells by high-energy implant.

Representative n-well CMOS process flow (mask-by-mask)

1. p-substrate; n-well mask — phosphorus implant + drive-in
2. Active-area mask — pad oxide + nitride; STI trench etch, fill, CMP (or LOCOS field oxide in legacy flows) with channel-stop implants
3. V_T-adjust implants (separate masks for NMOS/PMOS)
4. Gate oxidation (dry, high quality) → LPCVD poly-Si → gate mask + RIE (critical CD)
5. LDD implants → sidewall-spacer (CVD oxide/nitride + anisotropic etchback)
6. n⁺ S/D mask (As) and p⁺ S/D mask (BF₂) — self-aligned to gate+spacer; RTA activation
7. Salicidation (Ni/Co) of gate & S/D
8. ILD deposition + CMP → contact mask → W plugs → metal levels (damascene Cu) → passivation + pad mask

Latch-up — the classic CMOS hazard

§ 2.15MOS Transistor Characteristics & Threshold Voltage

(Device physics in depth: Unit 1 §1.12. Here, the technology-linked essentials.)

• Process knobs on V_T: t_ox (C_ox), channel doping (V_T-adjust implant ΔV_T = qΦ/C_ox for a shallow dose Φ), gate material (φ_ms: n⁺-poly vs p⁺-poly vs metal work function), and oxide charge control (Cl gettering of Na⁺).
• Body effect: \( V_T = V_{T0} + \gamma(\sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F}) \), \( \gamma = \sqrt{2\varepsilon_sqN_A}/C_{ox} \).
• I–V recap: triode \( I_D = \mu C_{ox}\tfrac{W}{L}[(V_{GS}-V_T)V_{DS} - V_{DS}^2/2] \); saturation \( \tfrac12\mu C_{ox}\tfrac{W}{L}(V_{GS}-V_T)^2(1+\lambda V_{DS}) \); subthreshold: exponential, swing ≥ 60 mV/dec.
• C–V profiling of the MOS capacitor (accumulation–depletion–inversion; HF vs LF curves) extracts t_ox, substrate doping, flat-band voltage and interface-state density — the standard process-monitoring measurement; bias-temperature stress reveals mobile Na⁺.

§ 2.16NMOS & CMOS Inverters

NMOS inverter

• Driver + load (resistive / enhancement / depletion). Ratioed: \( V_{OL} \) set by the driver:load (W/L) ratio; \(V_{OH} = V_{DD}\) only for depletion load (enhancement-saturated load loses a V_T).
• Static current flows in the output-low state → power; asymmetric rise (slow, through load) vs fall (fast, through driver).

CMOS inverter — the canonical gate

• PMOS pull-up + NMOS pull-down, gates tied (input), drains tied (output). In either logic state one device is OFF → static current ≈ 0 (only leakage); ratioless, full rail-to-rail swing \(V_{OH}=V_{DD},\ V_{OL}=0\).

Voltage-transfer characteristic (VTC) — five regions as input rises: (A) N off/P linear → (B) N sat/P linear → (C) both saturated (near-vertical transition; both conduct → current spike) → (D) N linear/P sat → (E) P off. The transition gives very high gain — the basis of regenerative logic levels.

For a symmetric inverter (V_M = V_DD/2): set β_n = β_p → \( (W/L)_p \approx (\mu_n/\mu_p)(W/L)_n \approx 2\text{–}3\times \) wider PMOS.

V_IL, V_IH defined where dV_out/dV_in = −1; symmetric CMOS approaches NM ≈ V_DD/2 each — the best of any logic family.

Quadratic V_DD dependence motivates voltage scaling. Propagation delay \( t_p \approx 0.69\,R_{eq}C_L \); energy–delay trade-off drives sizing.

§ 2.17Charge-Coupled Device (CCD)

Invented by Boyle & Smith (Bell Labs, 1969; Nobel 2009). A CCD is a dense array of MOS capacitors operated in deep depletion (a non-equilibrium state — gate pulsed beyond inversion before thermal carriers can form the inversion layer), so each electrode holds a potential well that stores signal charge.

Charge storage

• Photons absorbed in the depletion region generate EHPs; electrons collect in the well (p-substrate device), holes are swept away. Stored charge ∝ light intensity × integration time.
• Well capacity (full-well, ~10⁴–10⁶ e⁻) ∝ \(C_{ox}\,\Delta V\); exceeding it spills charge into neighbours — blooming (controlled by anti-blooming drains).
• Thermally generated dark current fills wells even in darkness (doubles every ~6–8 °C) → astronomical CCDs are cooled.
• Buried-channel CCD: a thin n-implant moves the storage potential minimum below the Si–SiO₂ interface, avoiding interface traps → far better transfer efficiency and noise (standard in imaging).

Charge transfer

• Clocking adjacent gates moves the packet — charge "coupled" from well to well like a bucket brigade. Schemes: three-phase (classic, unambiguous direction), two-phase (built-in asymmetric implant), four-phase; transfer physics = self-induced drift + fringing fields + thermal diffusion.

With thousands of transfers in a megapixel imager, CTE must exceed 0.99999 (ε < 10⁻⁵) — e.g., 0.99999^{2000} ≈ 0.98.

• Readout: final stage dumps each packet onto a floating diffusion → \( \Delta V = Q/C \) sensed by an on-chip source follower; correlated double sampling (CDS) cancels kTC reset noise.
• Imager architectures: linear (fax/scanners), full-frame (needs shutter), frame-transfer (storage half), interline (shielded vertical registers — camcorders; smear trade-off).

Applications & CMOS-sensor comparison

• Imaging (astronomy — quantum efficiency >90% back-illuminated, scientific cameras, early digital photography), spectroscopy, analog delay lines/shift registers and (historically) serial memories.
• CCD vs CMOS APS: CCD — global charge transfer, superb uniformity/low noise, but high clock power, slow, special fab. CMOS sensor — per-pixel amplifier, random access, low power, standard CMOS fab, now dominant; CCD survives in niche scientific use.

§ 2.18Basics of VLSI Design, Stick Diagrams & Layout Design Rules

Design abstraction & flow

Specification → architecture (RTL) → logic synthesis → circuit → layout (physical design) → verification (DRC: design-rule check; LVS: layout-vs-schematic; parasitic extraction) → tape-out (GDSII) → mask making. Design styles: full-custom, standard-cell (semi-custom), gate array, FPGA (Unit-V). Guiding principles: regularity, modularity, locality (hierarchy contains complexity).

Layer encoding and stick diagrams

A stick diagram is a topology-only cartoon of the layout: colored lines for layers, no dimensions — it captures relative placement and connectivity before exact geometry.

• Rules of thumb: lines on different layers cross freely except poly × diffusion (creates a device); contacts join layers; demarcation line separates PMOS (top, near V_DD rail) from NMOS (bottom, near GND) in standard-cell stick plans; series/parallel device stacks read directly from the gate network (NAND: series NMOS + parallel PMOS).
• From stick diagram → layout: assign widths per design rules; Euler-path ordering of gates yields an unbroken diffusion strip (minimum area).

Layout design rules

• Design rules are the contract between designer and fab: geometric minima guaranteeing manufacturability against misalignment, lithographic rounding, and process spread. Categories: minimum width (each layer), minimum spacing (same/different layers), extension (poly past diffusion = gate overhang), enclosure/surround (well around p-diff; metal around contact), and contact sizing.
• Lambda (λ) rules (Mead & Conway): all geometry in units of a single scalable parameter λ ≈ half the minimum feature (e.g., 0.5 µm process → λ = 0.25 µm). Portability across processes at some area penalty.

• Micron (absolute) rules: actual µm/nm values per layer — tighter, process-specific, used in production; λ rules are pedagogical/prototyping (MOSIS). Advanced nodes add restricted-design-rule grids, antenna rules (charge collection on long poly/metal during plasma steps), density rules (CMP uniformity, dummy fill), and metal slotting.

§ 2.19Unit-2 Formula Sheet

§ 2.20Quick Revision Notes — Unit 2 in 25 Points

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