Unit 4 — Analog Circuits, Op-Amps & PLL: Complete Exam Notes

§ 4.1Rectifiers & Filters

A rectifier converts AC to pulsating DC. Three classic topologies — memorize the comparison table cold; it is among the most repeated numerical sources in the paper.

Bridge wins: no centre-tap, PIV only V_m, best TUF — at the cost of two diode drops (significant for low-voltage outputs; remedy: Schottky or synchronous rectification).

Filters

• Capacitor (peak) filter: C charges to V_m, discharges into load between peaks — sawtooth ripple.
  Capacitor-filter ripple (full-wave) $$ V_{r(pp)} = \frac{I_{dc}}{2fC}, \qquad r = \frac{1}{4\sqrt{3}fCR_L}, \qquad V_{dc} \approx V_m - \frac{V_{r(pp)}}{2} $$
  (Half-wave: replace 2f by f.) Light load → small ripple; penalty: large repetitive surge/peak diode current in narrow conduction angles.
• Inductor filter: opposes current changes; ripple r = R_L/(3√2·ωL) — improves at heavy load (opposite of C filter).
• LC (choke-input) filter: ripple ≈ independent of load, r = √2/(12ω²LC); critical (bleeder) inductance L_c = R_L/3ω needed for continuous conduction.
• π (CLC) filter: best smoothing, poorer regulation; ripple ∝ 1/(C₁C₂LR_L).

§ 4.2Voltage-Regulator ICs & Regulated Power Supply

Block chain of a linear regulated supply: transformer → rectifier → filter → regulator → load. The regulator holds V_out against input (line) and load variations.

• Zener shunt regulator (Unit-1 §1.8): simplest; poor efficiency at light load.
• Series-pass (linear) regulator: error amplifier compares a sample of V_out (divider) with a reference (Zener/bandgap) and drives a series pass transistor — negative feedback holds V_out = V_ref(1 + R₁/R₂). Add current-limit (foldback for short-circuit safety) and a Darlington pass stage for current.
• Three-terminal fixed ICs: 78xx (+5, +6, +9, +12, +15, +24 V) and 79xx (negative); need V_in ≥ V_out + ~2 V dropout; internal thermal shutdown and current limit; bypass capacitors at both pins for stability. LDOs reduce dropout to ~0.1–0.5 V.
• LM317 adjustable: maintains 1.25 V between OUT and ADJ:
  LM317 output $$ V_{out} = 1.25\left(1 + \frac{R_2}{R_1}\right) + I_{ADJ}R_2 \quad (I_{ADJ} \approx 50\ \mu A,\ \text{usually negligible}) $$
• IC 723: the classic building-block regulator — internal 7.15 V reference, error amp, pass transistor (150 mA, externally boostable), and current-limit sense; configurable as low-V (2–7) or high-V (7–37) regulator; basis of many lab supplies.
• SMPS vs linear (detail in Unit-IX): linear — quiet, simple, efficiency ≈ V_out/V_in (often 30–50%); switching — 70–95% efficient, small magnetics at high f_sw, but switching noise/EMI.

§ 4.3BJT Biasing, Operating Point & Stability

Biasing fixes the quiescent point Q(I_CQ, V_CEQ) on the DC load line \( V_{CE} = V_{CC} - I_C(R_C + R_E) \) so the signal swings linearly — for max symmetric swing place Q mid-line (V_CEQ ≈ V_CC/2). The Q-point drifts with temperature through three culprits: I_CO doubles every 10 °C, V_BE drops ~2.5 mV/°C, and β rises with T (and spreads unit-to-unit).

• Voltage-divider design: Thevenin V_B = V_CC·R₂/(R₁+R₂), R_B = R₁∥R₂; \( I_C \approx \dfrac{V_B - V_{BE}}{R_E + R_B/\beta} \) — β-insensitive when R_B ≪ βR_E (rule: R_B ≤ 0.1βR_E) and V_E ≈ 1–2 V. Ideal S → 1; S ranges 1 … 1+β.
• R_E = DC negative feedback: I_C rises → V_E rises → V_BE falls → I_C pulled back. Bypass capacitor C_E restores AC gain while keeping DC stability.
• Thermal runaway: I_C↑ → junction power ↑ → T_J↑ → I_CO/β↑ → I_C↑… Avoided when \( \partial P_C/\partial T_J < 1/\theta_{JA} \); inherently safer when V_CE < V_CC/2. Heat sinks lower θ.
• Compensation techniques: diode in the base divider tracks V_BE(T); thermistor/sensistor adjusts bias; matched-pair (current-mirror) bias in ICs.

§ 4.4FET Biasing

• JFET / depletion MOSFET (needs V_GS < 0 for n-channel):
  • Fixed (gate) bias: negative supply through R_G — poor, parameter-sensitive.
  • Self bias: source resistor; I_D through R_S makes \( V_{GS} = -I_D R_S \); solve with the square law \( I_D = I_{DSS}(1 - V_{GS}/V_P)^2 \) graphically (bias line through origin, slope −1/R_S) or algebraically. Self-correcting: I_D↑ → V_GS more negative → I_D↓.
  • Voltage-divider bias: \( V_{GS} = V_G - I_DR_S \) with V_G = V_DD·R₂/(R₁+R₂) — flattest bias line, least sensitivity to device spread (best).
  • Current-source bias: a BJT/JFET current source in the source lead pins I_D exactly.
• Enhancement MOSFET (needs V_GS > V_T): drain-to-gate feedback bias (R_F from drain; since I_G = 0, V_GS = V_DS — guarantees saturation) or voltage-divider bias; use \( I_D = K(V_{GS} - V_T)^2 \).
• Gate current ≈ 0 in all FETs → huge R_G permissible (MΩ) without bias shift — the input-impedance advantage.
• Q-point checks: confirm \( V_{DS} > V_{GS} - V_P \) (JFET) or \( > V_{GS} - V_T \) (MOS) for saturation-region operation.

§ 4.5BJT Amplifiers: CE, CB, CC

Small-signal models: h-parameter (h_ie, h_re, h_fe, h_oe — Unit-3 two-port heritage) or hybrid-π with \( g_m = I_C/V_T \) (≈ 40·I_C at room T), \( r_\pi = \beta/g_m = h_{ie} \), \( r_e = V_T/I_E \approx 26/I_{E(mA)}\ \Omega \).

• Unbypassed R_E (swamping): \( A_v \approx -R_C/(r_e + R_E) \) — gain stabilized against r_e (temperature/bias) at the price of magnitude; R_in rises to r_π + (1+β)R_E.
• Emitter follower impedance transformation: looking into the base, emitter impedances appear ×(1+β); looking into the emitter, base-side impedances ÷(1+β) — the universal buffering identity.
• Cascode (CE + CB): CE gain into the low input impedance of CB kills the Miller effect → wide bandwidth with high gain; standard in RF and op-amp internals.
• Darlington pair: composite β ≈ β₁β₂, very high R_in, two V_BE drops, slower.

§ 4.6FET Amplifiers: CS, CG, CD

• Unbypassed R_S: \( A_v = \dfrac{-g_mR_D}{1 + g_mR_S} \) — source degeneration, same stabilization logic as the BJT's R_E.
• FET vs BJT amplifier: FET gives higher R_in, lower noise, but lower g_m at equal current (g_m(BJT) = I_C/V_T beats g_m(FET) = 2I_D/(V_GS−V_T)) → less gain per stage.
• MOSFET versions identical in form; CMOS active-load stages (current-mirror load) achieve \(A_v = -g_m(r_{o,n}\|r_{o,p})\) — the IC gain cell.

§ 4.7Classification of Amplifiers & Power Classes

Classification axes

• By signal size: small-signal (linear models valid) vs large-signal (power).
• By frequency: DC/audio (20 Hz–20 kHz) / video (wideband) / RF tuned (narrowband).
• By coupling: RC-coupled (cheap, flat mid-band, blocks DC), transformer-coupled (impedance matching, efficient power transfer, bulky, poor response), direct-coupled (amplifies DC, drift problem — op-amp internals).
• By quantity amplified: voltage/current/transconductance/transresistance — pairs with the four feedback topologies (§4.9).

Power-amplifier classes (conduction angle)

• Class A: Q mid-line, device always on; dissipation maximum at zero signal — P_D(max) = 2P_o(max) for transformer-coupled.
• Class B push-pull: complementary (NPN+PNP) or transformer-phase-split pair, each handles a half cycle; crossover distortion near zero (both off for |v_in| < V_BE). Even harmonics cancel in ideal push-pull.
• Class AB: slight forward bias (diode/V_BE-multiplier) removes crossover; thermal tracking via the bias diodes mounted on the heat sink.
• Class C: narrow current pulses re-shaped to a sine by a resonant tank; efficiency rises as conduction angle shrinks (at falling output power).
• Figures of merit: efficiency η = P_ac/P_dc, collector dissipation, harmonic distortion \( THD = \sqrt{D_2^2 + D_3^2 + \cdots} \), power-output capability.

§ 4.8Frequency Response of Amplifiers

• Mid-band gain flat; low-frequency roll-off from coupling and bypass capacitors (each forms a high-pass with its seen resistance, f_L = 1/2πRC; the largest individual f_L dominates); high-frequency roll-off from device/stray shunt capacitances (C_π, C_µ, C_wiring).
• Miller effect: feedback capacitance across an inverting gain A appears at the input multiplied:
  Miller capacitance $$ C_{in(Miller)} = C_f(1 + |A|), \qquad C_{out(Miller)} = C_f\left(1 + \tfrac{1}{|A|}\right) \approx C_f $$
  — dominant HF limit of CE/CS stages; defeated by cascode (CB/CG sees no Miller) or by the CC/CD buffer.
• BJT HF figures: \( f_\beta \) (β falls 3 dB), \( f_T = \beta f_\beta = g_m/2\pi(C_\pi + C_\mu) \) — gain–bandwidth of the device.
• Multistage: overall gain multiplies (dB add); bandwidth shrinks:
  n identical stages $$ f_{H(n)} = f_H\sqrt{2^{1/n} - 1}, \qquad f_{L(n)} = \frac{f_L}{\sqrt{2^{1/n}-1}} \quad (n = 2: \times 0.644) $$
• Gain–bandwidth conservation: in a single-pole stage, trading gain (e.g., by feedback) buys bandwidth — see §4.9, §4.11.
• Square-wave testing: LF tilt/sag ↔ f_L; rounded edges ↔ f_H (t_r ≈ 0.35/f_H, Unit-3).

§ 4.9Concept of Feedback

What negative feedback buys (all by the factor 1 + Aβ)

• Gain stability: \( \dfrac{dA_f}{A_f} = \dfrac{1}{1+A\beta}\,\dfrac{dA}{A} \) — gain set by passive β network.
• Bandwidth extension: \( f_{H,f} = f_H(1+A\beta) \), \( f_{L,f} = f_L/(1+A\beta) \); gain×bandwidth constant.
• Distortion & noise (inside the loop) reduced ÷(1+Aβ); input-referred noise of the first stage is not improved.
• Impedances re-shaped per topology (below) — the design lever.
• Cost: gain ÷(1+Aβ); risk: instability if phase reaches 180° while |Aβ| ≥ 1 (gain/phase margins, Unit-3 §3.12).

Memory rule: series mixing raises R_in, shunt mixing lowers it; voltage sampling lowers R_out, current sampling raises it.

Positive feedback (loop phase 0°): |Aβ| < 1 → regenerative gain boost (historic); |Aβ| = 1 → oscillation (§4.10); |Aβ| > 1 → latching (Schmitt trigger §4.13).

§ 4.10Oscillators: Phase-Shift, Wien, Hartley, Colpitts, Crystal

RC oscillators (audio range)

• RC phase-shift: inverting amplifier (180°) + three RC sections contributing the other 180° (60° each at f₀).
  Phase-shift oscillator $$ f_0 = \frac{1}{2\pi RC\sqrt{6}}, \qquad |A| \ge 29 \ (\text{the RC ladder attenuates } 1/29) $$
  (FET version as stated; BJT loading modifies to \( f_0 = \tfrac{1}{2\pi RC\sqrt{6 + 4R_C/R}} \), h_fe(min) ≈ 44.5 for R_C = R.)
• Wien bridge: non-inverting amp (0°) + lead-lag network (0° at f₀, β = 1/3).
  Wien bridge $$ f_0 = \frac{1}{2\pi RC}, \qquad A \ge 3 \ \Rightarrow\ R_f = 2R_1 $$
  Amplitude stabilization: lamp/thermistor or diode-limited R_f. The standard lab audio oscillator (tunable, low distortion).

LC oscillators (RF) — the general three-reactance form

Amplifier with reactances X₁ (input side), X₂ (output side), X₃ (feedback): oscillation needs X₁ + X₂ + X₃ = 0 with X₁, X₂ alike and X₃ opposite.

• Hartley ("H = henry → two inductors"): tapped L (L₁, L₂, mutual M) + one C.
  Hartley $$ f_0 = \frac{1}{2\pi\sqrt{(L_1 + L_2 + 2M)\,C}}, \qquad |A|_{min} = \frac{L_1}{L_2}\ (\text{feedback ratio } \beta = L_2/L_1) $$
• Colpitts ("C → two capacitors"): tapped C (C₁, C₂) + one L.
  Colpitts $$ f_0 = \frac{1}{2\pi\sqrt{L\,C_{eq}}}, \quad C_{eq} = \frac{C_1C_2}{C_1+C_2}, \qquad |A|_{min} = \frac{C_2}{C_1} $$
  Preferred at HF (capacitive divider absorbs device capacitances); Clapp adds a small series C₃ ≪ C₁,C₂ that dominates f₀ → frequency nearly independent of transistor capacitance (better stability).

Crystal oscillators

• Quartz piezoelectric resonator ≡ series R-L-C (motional) ∥ parallel C₀ (holder). Two resonances: series \( f_s = \tfrac{1}{2\pi\sqrt{LC}} \) and parallel/antiresonant \( f_p = f_s\sqrt{1 + C/C_0} \) slightly above; crystal operates inductive between f_s and f_p (replaces L in a Colpitts → Pierce configuration).
• Extraordinary Q ~ 10⁴–10⁶ → frequency stability ~ppm (TCXO/OCXO to ppb); clocks, µP timing, carrier generation. Overtone operation for > ~30 MHz.

§ 4.11Op-Amp Characteristics

A direct-coupled, very-high-gain differential amplifier: diff input pair → gain stage(s) with internal compensation capacitor → class-AB output buffer. Output \( V_o = A_{OL}(V_+ - V_-) \).

• Golden rules (negative feedback active): (1) no current into the inputs; (2) V₊ = V₋ — the inverting input of an inverting amp sits at virtual ground.
• CMRR = A_d/A_cm (dB: 20 log) — rejection of signals common to both inputs (hum, sensor common-mode).
• Gain–bandwidth product: single-pole compensated op-amp: \( A_{CL} \times f_{3dB} = f_T \) (e.g., gain 100 → 10 kHz BW on a 741).
• Slew rate \( SR = \max|dV_o/dt| = I_{tail}/C_{comp} \); large-signal limit. Maximum undistorted sine ("full-power bandwidth"):
  Slew-rate limit $$ f_{max} = \frac{SR}{2\pi V_{peak}} $$
  Small signals are bandwidth-limited; large signals slew-limited (triangular distortion).
• Offsets: V_io and I_B drive output errors ×(1 + R_f/R₁); bias-current compensation resistor \( R_{comp} = R_1 \| R_f \) at V₊; nulling pins on the 741.
• PSRR, output swing within rails (rail-to-rail types), input common-mode range, latch-up free modern devices.

§ 4.12Op-Amp Computational Applications

• Integrator + summer + inverter = analog computer solving ODEs (the "computational" in the syllabus); integrator also generates triangles from squares (§4.17) and is the core of dual-slope ADCs.
• Frequency view: integrator |H| = 1/ωRC (unity at ω = 1/RC); differentiator |H| = ωRC.

§ 4.13Comparators & Schmitt Trigger

Comparator

• Op-amp open-loop (or dedicated IC — LM311/LM339: faster, open-collector, no compensation): \( V_o = +V_{sat} \) if V₊ > V₋ else −V_sat. Zero-crossing detector (reference = 0) and level detector (reference = V_R).
• Weakness: noise near the threshold causes multiple output chatter; slow inputs dwell in the linear region. Cure: hysteresis.

Schmitt trigger (regenerative comparator)

Positive feedback to V₊ creates two thresholds — a bistable transfer characteristic with a hysteresis loop.

• Input must cross V_UT to switch one way and fall below V_LT to switch back — noise smaller than V_H cannot retrigger. Reference offset shifts the loop center.
• Applications: squaring any waveform, noise-immune level detection, switch debouncing, ON–OFF (bang-bang) control with deadband, relaxation oscillator core (§4.17), wave regeneration in digital receivers (74HC14 hex Schmitt inverter).
• Speed: output transitions at slew rate regardless of input speed — regenerative snap.

§ 4.14Instrumentation Amplifiers

Precision differential amplifier for low-level transducer signals (strain gauges, thermocouples, biopotentials) riding on large common-mode voltages. Requirements: very high R_in on both inputs, high CMRR, precise gain set by one resistor, low drift.

Three op-amp architecture

Stage 1: two non-inverting buffers sharing gain resistor R_G (their inverting inputs joined through it). Stage 2: unity (or fixed-gain) difference amplifier.

• Why it wins: input stage gives differential gain but unity common-mode gain (common-mode passes un-amplified to the matched difference stage) → CMRR multiplies; both inputs see op-amp R_in directly; single-resistor (R_G) gain programming without disturbing matching.
• Monolithic in-amps (AD620, INA128): laser-trimmed internal resistors, CMRR 100–120 dB, gain 1–1000 via external R_G.
• Bridge measurement: in-amp across a Wheatstone bridge senses mV-level imbalance \( V_d \approx V_{ex}\,\Delta R/4R \); guard drives and shield techniques preserve CMRR at the cable.
• Difference-amp alone fails: R_in unequal/low, CMRR collapses with 0.1% resistor mismatch (CMRR ≈ (1+R₂/R₁)/4ε).

§ 4.15Wave-Shaping Circuits

Clippers (limiters) — remove part of a waveform

• Series (diode in signal path) or shunt (diode across output); positive/negative/biased variants — clipping level = V_R ± 0.7 V; combination (two biased diodes) → slicer/amplitude limiter (e.g., ±V_Z ± 0.7 with back-to-back Zeners).
• Applications: protection, FM amplitude limiting, generating trapezoids/squares from sines.

Clampers (DC restorers) — shift the whole waveform

• C + diode (+ R): diode pins one peak near 0 (or V_R), capacitor stores the required DC; output swings entirely above (positive clamper) or below (negative clamper) the clamp level. Peak-to-peak is preserved; need RC ≫ T.
• Memory rule: output ≈ input + V_C; diode direction decides the sign. Application: video DC restoration, voltage doubler front ends.

RC shaping & precision circuits

• RC differentiator (RC ≪ T): square → spikes (edge detector); RC integrator (RC ≫ T): square → triangle-ish ramps (cf. §3.13 regimes).
• Precision (super) diode / precision rectifiers: diode inside an op-amp loop divides V_γ by A_OL → rectifies mV signals; half-wave and full-wave (absolute-value) versions; peak detector = precision diode + hold capacitor (+ buffer); sample-and-hold as its switched cousin.
• Voltage multipliers (half/full-wave doubler, Cockcroft–Walton ladder) — clamp + peak-rectifier cascades.

§ 4.16Active Filters

Op-amp + RC networks replace inductors: gain possible, near-ideal cascading (low Z_out), tunable — limited by op-amp GBW. (Passive/image filters: Unit-3 §3.13.)

• First-order LP: \( H = \dfrac{A_0}{1 + j f/f_c} \), \( f_c = \dfrac{1}{2\pi RC} \), −20 dB/dec; HP is the RC-swapped mirror.
• Second-order Sallen–Key (VCVS) LP: two RC + non-inverting gain A₀ = 1 + R_f/R₁:
  Sallen–Key equal-component design $$ f_c = \frac{1}{2\pi RC}, \qquad Q = \frac{1}{3 - A_0} \;\Rightarrow\; \textbf{Butterworth (Q = 0.707): } A_0 = 1.586,\ \ A_0 \ge 3 \Rightarrow \text{oscillation} $$
• −40 dB/dec per second-order section; cascade sections (with tabulated Q's) for higher order: overall slope −20n dB/dec.
• Band-pass: multiple-feedback (MFB) single-op-amp for Q ≲ 10: f₀, BW = f₀/Q; narrowband Q > 10 conventions; band-reject: twin-T with bootstrap, or LP + HP summed (wideband notch); 50 Hz hum notch is the standard example.
• State-variable (universal) filter: two integrators + summer give simultaneous LP/BP/HP outputs, independent f₀ and Q tuning; add a summer for notch/all-pass. All-pass: flat magnitude, phase shifter/delay equalizer.
• Response families recap (match-the-property): Butterworth — maximally flat; Chebyshev — equiripple, steeper; Elliptic — steepest; Bessel — linear phase/constant delay.
• Op-amp limits: f_c·gain ≪ GBW; slew rate caps large-signal output (f_max = SR/2πV_p); switched-capacitor filters (MF10) emulate R = 1/f_clkC for clock-tunable f_c.

§ 4.17Multivibrators & the 555 Timer

Op-amp astable (Schmitt + RC)

Triangular-wave generator: Schmitt trigger + integrator loop — triangle at the integrator, square at the Schmitt; \( f = \dfrac{R_2}{4R_1RC} \) for the standard pair.

555 timer (the exam favourite)

Internals: three 5 kΩ divider (thresholds 2V_CC/3 and V_CC/3), two comparators, SR flip-flop, discharge transistor, output buffer. Pins: 1 GND, 2 Trigger, 3 Out, 4 Reset, 5 Control (bypass 0.01 µF), 6 Threshold, 7 Discharge, 8 V_CC.

• Duty cycle always > 50% in the basic astable (charge through R_A+R_B, discharge through R_B); 50% via diode across R_B or R_A ≪ R_B tricks.
• Control pin (5) varies the 2V_CC/3 threshold → VCO / pulse-position modulation; timing independent of V_CC (ratiometric thresholds).
• Applications: timers, clocks, PWM, missing-pulse detector, frequency divider, touch switch.

§ 4.18Phase-Locked Loops (PLL)

Negative-feedback loop locking a local oscillator to an input's phase/frequency. Blocks: phase detector (PD) → loop (low-pass) filter → error voltage → VCO; VCO output feeds back to the PD.

• Operation: free-running (unlocked) → capture (pull-in toward f_in) → lock (f_VCO = f_in exactly; residual phase error supplies the control voltage). In lock, frequency error = 0.
• Key ranges $$ \textbf{Lock range } \Delta f_L \;>\; \textbf{Capture range } \Delta f_C; \qquad \Delta f_C \approx \sqrt{\frac{\Delta f_L}{2\pi\,\tau_{filter}}}\ \ (\text{narrower filter} \Rightarrow \text{smaller capture}) $$
  Lock range set by PD/VCO gains \(K_\phi K_v\); capture additionally throttled by the loop filter — the classic conceptual MCQ.
• Components: PD types — analog multiplier (K_φ sin φ_e), XOR (digital, 90° quiescent), phase-frequency detector + charge pump (infinite pull-in, no false lock); VCO conversion gain K_v (Hz/V); loop order/type sets tracking of steps/ramps.
• IC 565: classic analog PLL — free-running \( f_o \approx \dfrac{1.2}{4R_TC_T} \), lock range \( \Delta f_L = \pm\dfrac{8f_o}{V_{CC,total}} \), capture \( \Delta f_C = \pm\sqrt{\dfrac{\Delta f_L}{2\pi(3.6\times10^3)C}} \). CMOS 4046 for digital work.
• Applications (each is a one-line exam answer):
  • FM demodulation: VCO control voltage is the message.
  • FSK decoding (modems), AM synchronous detection (PLL regenerates the carrier).
  • Frequency synthesis: ÷N counter in the feedback → f_out = N·f_ref; programmable channel spacing = f_ref.
  • Frequency multiplication/translation, clock recovery from data, motor-speed control, carrier tracking in receivers.

§ 4.19V/F & F/V Converters

Voltage-to-Frequency (V/F)

• Output frequency ∝ input voltage — a linear VCO. Architectures:
  • Integrator + comparator (multivibrator type): input current charges C to a threshold, reset, repeat → f = V_in/(V_ref·RC)-type linearity.
  • Charge-balance (the precision standard, LM331/VFC32): each output pulse removes a fixed charge packet Q = I_ref·t; balance forces \( f = \dfrac{V_{in}}{R\,Q} \) — linearity ~0.01%, wide dynamic range.
• IC 566 (function-generator VCO): \( f_o = \dfrac{2(V_{CC} - V_C)}{R_TC_TV_{CC}} \) — simultaneous square + triangle outputs; control via pin 5 (pairs with the 565 PLL).
• Applications: cheap high-resolution ADC (count pulses over a gate time — inherent integration averages noise), telemetry over a single line / optocoupler (frequency is noise-immune and isolation-friendly), light/temperature transmitters, integrating DVMs.

Frequency-to-Voltage (F/V)

• Inverse function: input conditioned (Schmitt) → fixed-width, fixed-height pulse per cycle (monostable/charge pump) → averaging low-pass → \( V_o = k\,f_{in} \) (e.g., LM331 reversed, LM2907 with built-in comparator + charge pump).
• Design trade-off: larger filter C → less ripple but slower response (ripple ∝ 1/f_inRC).
• Applications: tachometer (speed from encoder/ignition pulses), FSK/FM demodulation, frequency meters, motor-speed feedback for control loops, RPM gauges.
• A V/F at the sender and F/V at the receiver = robust analog telemetry link; both functions are also subsumed by a PLL (VCO = V/F; PD+filter = F/V).

§ 4.20Unit-4 Formula Sheet

§ 4.21Quick Revision Notes — Unit 4 in 25 Points

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