Operational Amplifiers: Comprehensive Guide for B.Tech & GATE

Section 01

Foundations of the Operational Amplifier

What Is an Operational Amplifier?

An operational amplifier is a high-gain, direct-coupled, differential-input voltage amplifier. Originally designed in the 1940s to perform mathematical operations — addition, subtraction, integration, differentiation — in analog computers, today a single IC (μA741, LM358, TL081…) costs a few rupees and forms the heart of almost every analog signal-processing block.

Why it matters: Almost every sensor interface, audio circuit, instrumentation system, and control loop uses op-amps. Mastering them is equivalent to mastering analog electronics.

Standard op-amp triangular symbol with inverting input (−), non-inverting input (+), output, and dual supply rails — Standard op-amp circuit symbol showing the inverting input (−), non-inverting input (+), output terminal, and positive/negative power supply connections.

A Short History of the Op-Amp

Year	Milestone
1941	Karl D. Swartzel (Bell Labs) designs the first patented vacuum-tube op-amp for the M9 gun director.
1947	John Ragazzini (Columbia University) coins the term operational amplifier.
1953	First commercial op-amp, the GAP/R K2-W (vacuum tube).
1963	Bob Widlar designs the first monolithic IC op-amp — the μA702 at Fairchild Semiconductor.
1965	The legendary μA709 (Widlar) sets the template for IC op-amps.
1968	David Fullagar releases the μA741 — internally compensated, easy to use, still in production.
1970s+	FET-input (μA740, LF356), CMOS, rail-to-rail, low-noise, chopper-stabilised, and high-speed (GHz) variants emerge.

Take-Away

The op-amp is one of the most successful and democratising devices in electronics history. Knowing the 741 pin-out is a rite of passage for every electronics engineer.

Internal Block Diagram of an Op-Amp

Op-amp internal four-stage block diagram: differential amplifier stage, intermediate gain stage (Darlington), level shifter, and Class-AB push-pull output stage — Internal block diagram of a general-purpose op-amp showing the four functional stages. The differential amplifier rejects common-mode noise; the intermediate stage provides additional voltage gain; the level shifter removes DC bias; the Class-AB output stage delivers low impedance and high current drive.

Stage Functions (Part 1)

Differential amplifier: Amplifies \((v_+ - v_-)\) and rejects common-mode noise.
Intermediate gain stage: Provides additional gain (~500×) and impedance buffering (Darlington pair).

Stage Functions (Part 2)

Level shifter: Brings DC level back to 0 V so output is 0 when differential input is 0.
Output stage: Low output impedance, high current drive, wide voltage swing.

Pin Diagram of the μA741 (8-Pin DIP)

μA741 8-pin DIP top-view pinout: pin 1 offset null, pin 2 inverting input, pin 3 non-inverting input, pin 4 negative supply, pin 5 offset null, pin 6 output, pin 7 positive supply, pin 8 NC — μA741 8-pin DIP package top-view pinout. Pins 1 and 5 connect to an external offset-null potentiometer; pins 2 and 3 are the inverting and non-inverting inputs; pin 6 is the output; pins 4 and 7 are the negative and positive supply rails.

Pin(s)	Name	Purpose
1, 5	Offset null	External potentiometer to null the input offset voltage
2	\(v_-\) (Inverting input)	Negative differential input
3	\(v_+\) (Non-inverting input)	Positive differential input
4	\(-V_{EE}\)	Negative supply (−15 V typical)
6	Output	\(v_o\)
7	\(+V_{CC}\)	Positive supply (+15 V typical)
8	N.C.	Not connected

Power supply options: Single supply (e.g. +12 V) or dual supply (±15 V) are both common. A dual supply allows the output to swing both positive and negative around 0 V.

The Ideal Op-Amp — A Useful Fiction

Parameter	Ideal Value	Practical (741 typical)
Open-loop gain \(A_{OL}\)	\(\infty\)	\(2 \times 10^5\)
Input impedance \(R_i\)	\(\infty\)	2 MΩ
Output impedance \(R_o\)	0	75 Ω
Bandwidth (BW)	\(\infty\)	\(f_T = 1\) MHz
CMRR	\(\infty\)	90 dB
Slew rate (SR)	\(\infty\)	0.5 V/μs
Input offset \(V_{io}\)	0	2 mV
Input bias current \(I_B\)	0	80 nA
PSRR	\(\infty\)	90 dB
Noise	0	~20 nV/√Hz

Equivalent Circuit of a Practical Op-Amp

Practical op-amp equivalent circuit: input resistance Ri across the differential input terminals, voltage-controlled voltage source A_OL times vd, and series output resistance Ro driving the output terminal — Equivalent circuit of a practical op-amp. The input differential resistance \(R_i\) loads the source; the voltage-controlled voltage source \(A_{OL} v_d\) models the amplification; the series output resistance \(R_o\) limits current drive.

Open-Loop Differential Gain

\[ v_o = A_{OL}(v_+ - v_-) = A_{OL}\,v_d \] Practical values: \(A_{OL} \approx 10^5\) to \(10^6\) (i.e. 100 dB to 120 dB).

Open-Loop Operation (No Feedback)

Without negative feedback, the op-amp acts as a comparator — the output saturates to \(\pm V_{sat}\). The two golden rules do not apply in this mode.

Pedagogical Approach

Every topic in these notes follows a consistent flow: Why we need it → What the circuit looks like → How to derive its behaviour → Where it is applied → Worked numerical example. Three pillars underpin op-amp mastery:

Intuition first — always ask: what is the op-amp trying to keep equal?
Two golden rules — \(V^+ = V^-\) and \(I^+ = I^- = 0\) explain 90 % of all circuits.
Practice by derivation — never memorise a formula you cannot re-derive in 60 seconds.

Ideal vs. Practical Op-Amp Parameters

Ideal Op-Amp

Infinite open-loop gain \(A_{OL} \to \infty\), infinite input resistance \(R_i \to \infty\), zero output resistance \(R_o = 0\), infinite bandwidth, zero offset, zero noise, zero drift.

Two Golden Rules (ideal with feedback)

Rule 1: \(V^+ = V^-\) (virtual short).
Rule 2: \(I^+ = I^- = 0\) (no input current).
Both apply only when negative feedback is present and the op-amp is in its linear region.

DC Imperfections

Input Offset Voltage \(V_{io}\)

The small differential input voltage required to null the output. For the 741: \(V_{io} \approx 2\) mV typical. Referred to the output of a closed-loop circuit with gain \(A_{CL}\):

\[ V_{oo} = A_{CL} \cdot V_{io} \]

Input Bias Current \(I_B\) and Offset Current \(I_{io}\)

Each input draws a small base/gate current. The average is \(I_B = (I_B^+ + I_B^-)/2\) and the mismatch is \(I_{io} = |I_B^+ - I_B^-|\). For the 741: \(I_B \approx 80\) nA, \(I_{io} \approx 20\) nA.

Output offset due to bias currents

\[ V_{oo} = V_{io}\!\left(1+\dfrac{R_f}{R_1}\right) + I_B\,R_f \] For an inverting amplifier with feedback resistor \(R_f\) and input resistor \(R_1\).

Compensating for Bias Current

Insert a compensating resistor \(R_c\) in series with the non-inverting input so that the voltage drops produced by \(I_B\) at the two inputs cancel:

\[ R_c = R_1 \,\Vert\, R_f = \dfrac{R_1 R_f}{R_1 + R_f} \]

The residual output offset is then governed by the much smaller offset current:

\[ V_{oo} \approx I_{io}\,R_f \ll I_B\,R_f \]

Op-amp inverting amplifier with compensation resistor Rc at the non-inverting input to cancel bias-current errors — Bias-current compensation in an inverting amplifier: a compensation resistor \(R_c = R_1 \parallel R_f\) inserted at the non-inverting input reduces the output DC error from \(I_B R_f\) to \(I_{io} R_f\).

Thermal Drift

Offsets and bias currents change with temperature. For instrumentation work, this drift is the real design challenge, not the nominal offset value.

\[ \Delta V_{io} = \left.\frac{\partial V_{io}}{\partial T}\right|_T \cdot \Delta T \quad [\text{V}/^\circ\text{C}] \]

Typical 741: \(dV_{io}/dT \approx 6\,\mu\text{V}/^\circ\text{C}\), \(dI_{io}/dT \approx 0.2\,\text{nA}/^\circ\text{C}\).
Premium precision op-amps (OP07, AD8551): \(<1\,\mu\text{V}/^\circ\text{C}\).
Chopper-stabilized parts: \(<0.05\,\mu\text{V}/^\circ\text{C}\).

AC Characteristics

Frequency Response and Gain–Bandwidth Product

The open-loop gain rolls off at 20 dB/decade above the dominant pole \(f_1\). A single-pole model gives:

\[ A_{OL}(f) = \dfrac{A_0}{1 + j\,f/f_1}, \qquad |A_{OL}(f)| \approx \dfrac{f_T}{f} \quad (f \gg f_1) \]

Gain–Bandwidth Product (GBP)

\[ A_{CL} \times BW_{CL} = f_T \] For the 741: \(f_T \approx 1\) MHz, so a closed-loop gain of 100 yields a bandwidth of only 10 kHz.

Bode magnitude plot showing open-loop gain A₀ rolling off at −20 dB/decade above f₁, closed-loop gain ACL, and unity-gain bandwidth fT — Bode magnitude plot of an internally compensated op-amp. The open-loop gain \(A_0\) is constant below \(f_1\), then rolls off at −20 dB/decade. The closed-loop gain trades bandwidth for gain such that \(A_{CL} \times BW_{CL} = f_T\).

Slew Rate

Definition: The maximum rate of change of the output voltage: \[ \mathrm{SR} = \left.\frac{dv_o}{dt}\right|_{\max} \;[\text{V}/\mu\text{s}] \] The internal compensation capacitor \(C_C\) can only be charged by a finite current \(I_{max}\), so \(\mathrm{SR} = I_{max}/C_C\).

Full-Power Bandwidth

For a sinusoidal output \(v_o = V_m \sin(2\pi f t)\), the maximum undistorted frequency is: \[ f_{\max} = \dfrac{\mathrm{SR}}{2\pi V_m} \]

Slew-Rate Distortion

Demanding a \(dv_o/dt\) faster than SR turns the output into a triangular wave. Typical SR values: 741 → 0.5 V/μs; LF356 → 12 V/μs; AD811 (video) → 2500 V/μs.

Common-Mode Rejection Ratio (CMRR)

For inputs \(v_1, v_2\): \(v_d = v_1 - v_2\), \(v_c = \tfrac{1}{2}(v_1+v_2)\), \(v_o = A_d v_d + A_c v_c\).

\[ \mathrm{CMRR} = \left|\dfrac{A_d}{A_c}\right|, \qquad \mathrm{CMRR_{dB}} = 20\log_{10}\!\left|\dfrac{A_d}{A_c}\right| \]

Typical 741: 90 dB. Instrumentation-grade INA126: \(>110\) dB. High CMRR is critical for thermocouples, ECG, and strain-gauge circuits that ride on common-mode noise.

Power-Supply Rejection Ratio (PSRR)

\[ \mathrm{PSRR} = \dfrac{\Delta V_{CC}}{\Delta V_{io}}, \qquad \mathrm{PSRR_{dB}} = 20\log_{10}\!\left|\dfrac{\Delta V_{CC}}{\Delta V_{io}}\right| \]

Typical 741: ~90 dB. PSRR decreases at high frequencies, so 0.1 μF ceramic decoupling capacitors at supply pins are mandatory in any PCB layout.

Noise in Op-Amps

Referred to the input, every op-amp produces input voltage noise \(e_n\) [nV/√Hz] and input current noise \(i_n\) [pA/√Hz]. Each spectrum has a \(1/f\) region below corner frequency \(f_c\) and white noise above it.

\[ E_{no} = G_n\sqrt{e_n^2\Delta f + (i_n R_{eq})^2\Delta f + 4kT R_{eq}\Delta f} \]

where \(G_n = 1+R_f/R_1\) is the noise gain, \(R_{eq}\) is the equivalent source resistance, and \(\Delta f\) is the bandwidth.

How to Choose an Op-Amp for Low Noise

Low source impedance (microphone, MC cartridge): BJT-input, low-\(e_n\) part (e.g. NE5534).
High source impedance (photodiode, electrometer): JFET/CMOS-input, low-\(i_n\) part (e.g. LF356, LMC6064) — otherwise the \(i_n R_s\) term dominates.

Summary: Typical 741 Parameters

Parameter	Typical Value	Significance
\(A_{OL}\) (open-loop gain)	\(2\times10^5\)	Sets accuracy of closed-loop gain
\(R_i\) (input resistance)	2 MΩ	Loading on source
\(R_o\) (output resistance)	75 Ω	Ability to drive loads
\(V_{io}\) (input offset voltage)	2 mV	DC error at output
\(I_B\) (input bias current)	80 nA	Voltage drop across resistors
\(I_{io}\) (input offset current)	20 nA	Residual after compensation
CMRR	90 dB	Common-mode rejection
PSRR	30 μV/V	Supply noise rejection
SR (slew rate)	0.5 V/μs	Large-signal speed
\(f_T\) (unity-gain BW)	1 MHz	Small-signal speed
\(e_n\) (input voltage noise)	~20 nV/√Hz	Noise floor
\(V_{sat}\) (output swing)	±13 V (with ±15 V supply)	Output headroom

Section 02

The Differential Amplifier Stage

The Atomic Building Block: Every op-amp begins with a differential amplifier. Understanding its four configurations is the foundation for everything that follows.

Four Input/Output Configurations

Dual-Input, Balanced-Output (DIBO) — two signals in, output taken between two collectors.
Dual-Input, Unbalanced-Output (DIUO) — two signals in, output taken w.r.t. ground.
Single-Input, Balanced-Output (SIBO) — one signal, two-ended output.
Single-Input, Unbalanced-Output (SIUO) — the typical single-ended configuration.

In all cases two signal modes are analysed: differential mode (\(v_d\)) — the useful signal — and common mode (\(v_c\)) — the noise or interference to be rejected.

DIBO: Dual-Input, Balanced-Output

BJT differential pair with two inputs v1 and v2 at the bases, emitters joined to a tail resistor RE, and collectors loaded by RC resistors with output vo taken between them — Dual-Input, Balanced-Output (DIBO) differential pair: the output \(v_o = v_{o2} - v_{o1}\) is taken between the two collector nodes, doubling the available gain compared to the single-ended output.

Differential Gain

\[ A_d = -\frac{R_C}{2r_e}\ (\text{per side}), \quad A_d^{\text{bal}} = \frac{R_C}{r_e} \]

Common-Mode Gain & CMRR

\[ A_c \approx -\frac{R_C}{2R_E + r_e} \approx 0\ (R_E \to \infty) \] \[ \mathrm{CMRR} = \frac{2R_E}{r_e} \]

where \(r_e = V_T/I_E\) is the small-signal emitter resistance.

Improving CMRR — Active Tail Current Source

Key idea: An active tail source (e.g. transistor \(Q_3\)) has a very large small-signal output resistance \(r_o\), so common-mode inputs barely change \(I_{EE}\) — \(A_c\) falls and CMRR rises dramatically (replacing \(R_E\) with \(r_o \sim \mathrm{M}\Omega\) in the CMRR formula).

Tail-Current Set Point

\[ I_{EE} \approx \dfrac{V_B - V_{BE} + V_{EE}}{R_E} = \dfrac{V_{R_2} - V_{BE}}{R_E} \] where \(R_1\) and \(R_2\) form the base voltage divider and \(R_E\) fixes the tail current.

Configuration Summary

Configuration	Differential Gain	Common-Mode Gain	Notes
DIBO	\(R_C/r_e\)	\(\approx R_C/2R_E\)	High gain; two ends to use
DIUO	\(R_C/(2r_e)\)	\(\approx R_C/2R_E\)	Most common at op-amp inputs
SIBO	\(R_C/r_e\)	Same as DIBO	One input grounded
SIUO	\(R_C/(2r_e)\)	Same as DIUO	Single-ended in and out

Mnemonic

Balanced output → double the gain (you read across both collectors).
Unbalanced output → half the gain (you read only one collector).

Section 03

Feedback Theory in Op-Amps

The General Feedback Topology

Block diagram of a negative feedback system: forward amplifier A, feedback network β, summing junction, with signals vs, vd, vo, vf labelled — General negative-feedback block diagram. The forward amplifier has gain \(A\), the feedback network samples the output and returns a fraction \(\beta v_o\) to be subtracted from the source \(v_s\).

Closed-Loop Gain

\[ v_o = A(v_s - \beta v_o) \;\Rightarrow\; A_f = \dfrac{v_o}{v_s} = \dfrac{A}{1 + A\beta} \] Loop gain: \(A\beta\). Desensitivity factor: \(D = 1 + A\beta\). For \(A\beta \gg 1\): \(A_f \approx 1/\beta\).

Benefits of Negative Feedback

Property	Effect (desensitivity factor \(D = 1+A\beta\))
Gain	Reduced by \(D\): \(A_f = A/D\)
Gain stability	\(\dfrac{dA_f/A_f}{dA/A} = \dfrac{1}{D}\)
Input impedance	\(R_{if} = R_i \cdot D\) (series-mixed) or \(R_i/D\) (shunt-mixed)
Output impedance	\(R_{of} = R_o/D\) (voltage-sampled) or \(R_o \cdot D\) (current-sampled)
Bandwidth	Increased by \(D\): \(f_{Hf} = f_H \cdot D\)
Distortion	Reduced by \(D\)
Intrinsic noise	Unchanged

The famous trade-off: You sacrifice gain to gain everything else. With \(A_{OL} \sim 10^5\) available, that is a very favourable bargain.

The Four Feedback Topologies

Topology	Sampled at Output	Mixed at Input	Op-Amp Example
Voltage-series	Voltage	Voltage (series)	Non-inverting amplifier
Voltage-shunt	Voltage	Current (shunt)	Inverting amplifier
Current-series	Current	Voltage (series)	V-to-I converter
Current-shunt	Current	Current (shunt)	Current amplifier

How to Recognise a Topology

Step 1: If the feedback wire connects to the inverting input through a resistor → shunt input; otherwise series.
Step 2: If feedback samples the load voltage (parallel to output) → voltage sampling; if it samples a series current → current sampling.

The Two Golden Rules — Revisited

With \(A_{OL} \to \infty\) and a small finite \(v_o\):

\[ v_d = v_+ - v_- = v_o/A_{OL} \to 0 \quad\Rightarrow\quad v_+ = v_-\ \text{(virtual short)} \]

With \(R_i \to \infty\), no current flows into the input terminals: \(i_+ = i_- = 0\).

Necessary Conditions

The golden rules apply only when: (1) negative feedback is present, and (2) the op-amp is in its linear region (\(|v_o| < V_{sat}\)).

Section 04

Closed-Loop Configurations

The Inverting Amplifier

Inverting op-amp amplifier with input resistor R1, feedback resistor Rf, non-inverting input grounded, showing virtual ground at the inverting input node — Inverting amplifier configuration. The inverting input is held at virtual ground (0 V), making the gain \(A_v = -R_f/R_1\) independent of the open-loop gain.

KCL at virtual ground (inverting node held at 0 V):

\[ \dfrac{v_i - 0}{R_1} = \dfrac{0 - v_o}{R_f} \]

Inverting Gain

\[ A_v = \dfrac{v_o}{v_i} = -\dfrac{R_f}{R_1} \] Input impedance: \(Z_{in} = R_1\) (sees virtual ground). Output impedance: \(Z_o \approx 0\). Bandwidth: \(\mathrm{BW} = f_T/(1+R_f/R_1)\).

Pro: Predictable gain, convenient summing point. Con: Finite input impedance equal to \(R_1\) loads the source.

The Non-Inverting Amplifier

Non-inverting op-amp amplifier with input at the non-inverting terminal, gain-setting resistor divider R1 and Rf on the inverting side — Non-inverting amplifier. The virtual short forces \(v_- = v_+ = v_i\), and the voltage divider formed by \(R_1\) and \(R_f\) sets the closed-loop gain \(A_v = 1 + R_f/R_1 \geq 1\).

\[ v_- = v_o \cdot \dfrac{R_1}{R_1+R_f} = v_i \]

Non-Inverting Gain

\[ A_v = 1 + \dfrac{R_f}{R_1} \quad (\text{always} \geq 1) \] Input impedance: \(Z_{in} \to \infty\). Output impedance: \(Z_o \approx 0\).

The Voltage Follower (Unity-Gain Buffer)

Op-amp voltage follower with output directly connected back to the inverting input, giving unity gain with very high input and very low output impedance — Voltage follower (unity-gain buffer): direct output-to-inverting-input feedback, equivalent to \(R_f = 0\), \(R_1 = \infty\) in the non-inverting configuration. Ideal for impedance isolation.

Properties

\[ v_o = v_i, \quad Z_{in} \to \infty, \quad Z_o \to 0 \]

Uses: Impedance buffer for high-Z sources (pH sensor, electrometer), inter-stage isolation, power buffering without voltage change.

Stability Tip

Some op-amps are not unity-gain stable — always check the datasheet for a minimum stable closed-loop gain specification.

Section 05

Linear Applications

Summing (Adder) Amplifier

Op-amp inverting summer with three input resistors R1 R2 R3 joining at a virtual-ground summing node and a single feedback resistor Rf — Inverting summing amplifier. KCL at the virtual-ground summing node yields a weighted sum of the input voltages. Equal resistors produce a simple adder; setting \(R_f = R/n\) produces an averager.

KCL at virtual ground:

\[ \dfrac{v_1}{R_1} + \dfrac{v_2}{R_2} + \dfrac{v_3}{R_3} = -\dfrac{v_o}{R_f} \]

Weighted Summer

\[ v_o = -R_f \!\left( \dfrac{v_1}{R_1} + \dfrac{v_2}{R_2} + \dfrac{v_3}{R_3} \right) \]

Worked Example — Designing a Summing Amplifier

Problem

Design a circuit to compute \(v_o = -(2v_1 + 5v_2 + 0.5v_3)\) using a 741 op-amp with \(R_f = 100\) kΩ.

Solution: For each input, \(R_f/R_i\) equals the desired weight:

Coefficient 2 for \(v_1\): \(R_1 = R_f/2 = 50\) kΩ
Coefficient 5 for \(v_2\): \(R_2 = R_f/5 = 20\) kΩ
Coefficient 0.5 for \(v_3\): \(R_3 = R_f/0.5 = 200\) kΩ

Bias compensation: \(R_c = R_1 \Vert R_2 \Vert R_3 \Vert R_f \approx 11.4\) kΩ placed at the non-inverting input.

Headroom check: With each input at ±1 V, \(|v_o|_{\max} = 7.5\) V — well within the ±13 V swing of the 741.

Difference (Subtractor) Amplifier

With both inputs applied through matched resistors to the inverting and non-inverting inputs, superposition gives:

\[ v_o = v_2 \cdot \dfrac{R_g}{R_2+R_g} \cdot \!\left(1+\dfrac{R_f}{R_1}\right) - \dfrac{R_f}{R_1}v_1 \]

Balanced Design (\(R_f/R_1 = R_g/R_2\))

\[ v_o = \dfrac{R_f}{R_1}(v_2 - v_1) \] Note: A 1 % resistor mismatch limits the CMRR of the subtractor to approximately 40 dB.

Instrumentation Amplifier (3-Op-Amp)

Three-op-amp instrumentation amplifier: Stage 1 consists of two non-inverting buffers with a shared gain-setting resistor Rg between their inverting inputs, Stage 2 is a unity-gain difference amplifier — Three-op-amp instrumentation amplifier. Stage 1 provides differential gain set by a single resistor \(R_g\) while presenting near-infinite input impedance at both terminals. Stage 2 (difference amplifier) rejects common-mode voltage.

Overall Gain

\[ v_o = \left( 1 + \dfrac{2R_1}{R_g} \right) \cdot \dfrac{R_f}{R}\,(v_2 - v_1) \]

Advantages: Very high \(Z_{in}\); gain set by one resistor \(R_g\); CMRR determined only by Stage 2 resistor matching. Widely used in medical instrumentation and strain-gauge bridges.

Ideal and Practical Integrators

Ideal Integrator

\[ v_o(t) = -\dfrac{1}{RC}\int_0^t v_i(\tau)\,d\tau + v_o(0) \] Transfer function: \(H(s) = -1/(sRC)\). Unity gain at \(\omega = 1/RC\).

Practical Integrator

\[ H(s) = -\dfrac{R_f/R}{1 + sR_f C} \] Integrates for \(f > f_a = 1/(2\pi R_f C)\); behaves as inverting amplifier for \(f < f_a\).

Differentiator

Ideal Differentiator

\[ v_o(t) = -RC\,\dfrac{dv_i}{dt}, \quad H(s) = -sRC \] Magnitude: \(|H(j\omega)| = \omega RC\) — a +20 dB/decade slope.

Noise Problem

The ideal differentiator amplifies HF noise. Practical versions add \(R_1\) in series with \(C\) and \(C_f\) in parallel with \(R\) to limit HF gain.

V-to-I and I-to-V Converters

V-to-I Converter (floating load)

\[ i_L = \dfrac{v_i}{R} \] Output current is independent of \(Z_L\) — a transconductance amplifier.

I-to-V Converter (transimpedance)

\[ v_o = -i_i \cdot R_f \] Used in photodiode amplifiers and current-output DACs.

Howland Current Pump (Grounded-Load V-to-I)

Howland current pump op-amp circuit with four matched resistors R1 R2 R3 R4 and a grounded load ZL, providing a load-independent output current — Howland current pump. With the matched-resistor condition \(R_2/R_1 = R_4/R_3\), the load current \(i_L\) depends only on the differential input voltage, not on the impedance of the grounded load.

Matched-Resistor Condition (\(R_2/R_1 = R_4/R_3\))

\[ i_L = \dfrac{v_2 - v_1}{R_1}\cdot\dfrac{R_2}{R_4} \quad \xrightarrow{R_1=R_2=R_3=R_4}\; i_L = \dfrac{v_2-v_1}{R} \] Applications: bipolar current sources for RTD/strain-gauge excitation, electrochemical stimulators.

Charge Amplifier (Piezoelectric Front-End)

Output

\[ v_o(t) = -\dfrac{q(t)}{C_f} \] Low-frequency cut-on: \(f_L = 1/(2\pi R_f C_f)\). Used in accelerometers and ultrasonic transducers.

Section 06

Non-Linear Applications

The Comparator

Transfer Characteristic

\[ v_o = \begin{cases}+V_{sat}, & v_i > V_{ref}\\-V_{sat}, & v_i < V_{ref}\end{cases} \]

Applications: threshold detection, zero-crossing detection, window detectors, ADC stages. The zero-crossing detector (\(V_{ref} = 0\)) converts a sine wave to a square wave. A window detector uses two comparators with outputs OR-ed to indicate when the input lies within \([V_L, V_H]\).

Schmitt Trigger — Comparator with Hysteresis

Inverting Schmitt trigger with positive feedback via resistor divider R1-R2, and its hysteresis loop showing upper and lower threshold voltages VUT and VLT — Inverting Schmitt trigger with positive feedback. Hysteresis between the upper threshold \(V_{UT}\) and lower threshold \(V_{LT}\) prevents output chattering when noisy signals cross the threshold.

Inverting Schmitt Thresholds

\[ V_{UT} = +V_{sat}\cdot \dfrac{R_1}{R_1+R_2} \] \[ V_{LT} = -V_{sat}\cdot \dfrac{R_1}{R_1+R_2} \] \[ V_H = V_{UT}-V_{LT} = \dfrac{2R_1 V_{sat}}{R_1+R_2} \]

Non-Inverting Schmitt Thresholds

\[ V_{UT} = +V_{sat}\cdot\dfrac{R_1}{R_2} \] \[ V_{LT} = -V_{sat}\cdot\dfrac{R_1}{R_2} \] Output transitions in the same direction as the input.

Choosing \(V_H\): Make the hysteresis just larger than the peak noise amplitude. Too small → chattering; too large → insensitivity to real signal changes.

Multivibrators and Waveform Generators

Astable Multivibrator (Square-Wave Generator)

The op-amp is used open-loop with positive feedback (Schmitt configuration) and a timing RC network on the inverting input. The capacitor charges through \(R\) toward the threshold, flipping the output, then charges in the other direction — producing a continuous square wave.

Period of Oscillation

\[ T = 2RC \ln\!\left(1 + \dfrac{2R_1}{R_2}\right) \] Special case: \(R_2 = 1.16\,R_1 \Rightarrow T = 2RC\).

Monostable Multivibrator (One-Shot)

Has one stable state; a trigger drives the output to an unstable state for a fixed time \(T\), then it returns. Used for pulse generation, debouncing, and missing-pulse detection.

\[ T = RC\,\ln\!\left(\dfrac{1+V_D/V_{sat}}{1-\beta}\right), \quad \beta = \dfrac{R_1}{R_1+R_2} \]

Triangular-Wave Generator

A Schmitt trigger drives an integrator; the Schmitt output is a square wave and the integrator converts it to a triangle wave via feedback.

Triangular Wave Parameters

\[ V_p = V_{sat}\cdot \dfrac{R_1}{R_2}, \qquad f = \dfrac{R_2}{4\,R_1 R C} \]

Wien-Bridge Oscillator

Conditions for Oscillation

\[ f_o = \dfrac{1}{2\pi RC}, \qquad \dfrac{R_f}{R_1} = 2 \;\Longleftrightarrow\; A_v = 3 \]

RC Phase-Shift Oscillator

Three cascaded RC sections each provide 60° of phase shift for a total of 180° at one specific frequency; the inverting op-amp adds another 180°, satisfying the Barkhausen criterion.

Design Equations

\[ f_o = \dfrac{1}{2\pi RC\sqrt{6}}, \qquad |A_v| \geq 29, \qquad R'_f \geq 29\,R \]

Precision Rectifiers

Precision Half-Wave Rectifier (Superdiode)

A passive diode has a forward voltage drop of ~0.7 V that ruins precision for small signals. The op-amp drives whatever voltage is needed at its output to overcome \(V_D\), so the effective threshold at the node becomes \(V_D/A_{OL} \approx 0\).

Behavior

\[ v_o = \begin{cases} -\dfrac{R_f}{R_1}\,v_i, & v_i < 0 \\[4pt] 0, & v_i > 0\end{cases} \]

Precision Full-Wave Rectifier (Absolute-Value Circuit)

Stage 1 is a precision half-wave rectifier producing \(v_1\). Stage 2 is an inverting summer combining \(v_1\) with weight 2 (through \(R/2\)) and the original \(v_i\) with weight 1 (through \(R\)), yielding \(v_o = |v_i|\).

Two-stage precision full-wave rectifier: Stage 1 is a precision half-wave rectifier, Stage 2 is an inverting summer combining v1 and vi with weights 2 and 1 to produce |vi| — Precision full-wave rectifier (absolute-value circuit). Stage 1 produces the half-wave rectified signal \(v_1\); Stage 2 combines \(v_1\) and \(v_i\) in a 2:1 ratio to reconstruct the full-wave output \(v_o = |v_i|\).

Log and Antilog Amplifiers

Log Amplifier Output

\[ v_o = -V_T \ln\!\left(\dfrac{v_i}{I_s R}\right) \] Requires \(v_i > 0\). \(V_T \approx 26\) mV at room temperature.

Antilog Amplifier Output

\[ v_o = -R_f\,I_s\, e^{-v_i/V_T} \] The exponential relationship is achieved by placing the transistor at the input.

Applications: analog multiply/divide, dB meters, audio compressors. Temperature drift is the main limitation — use a matched transistor pair or a compensated IC (AD538, LOG112).

Sample-and-Hold Circuit

Key Parameters

Acquisition time: \(t_{aq} \approx 5\,R_{on}C_H\)
Droop rate: \(dv_o/dt = I_{leak}/C_H\)
Aperture time: switch turn-off uncertainty → amplitude jitter

Peak Detector

A precision diode (op-amp A₁ + diode \(D\)) charges a hold capacitor \(C_H\) only when \(v_i\) rises above the previously stored peak. When \(v_i\) falls, \(D\) reverse-biases and \(C_H\) retains the peak voltage.

\[ v_o(t) = \max_{0\le \tau \le t} v_i(\tau) \]

A reset switch discharges \(C_H\) between measurements. Used in envelope detection, AM demodulation, and AGC systems.

Section 07

Active Filters

Definition: A frequency-selective circuit using op-amps and RC networks (no inductors) — offering high \(Q\), adjustable gain, low cost, and freedom from inductor parasitics.

Classification by Passband

Low-pass (LPF), High-pass (HPF), Band-pass (BPF), Band-stop / Notch (BSF), All-pass (phase equalizer).

Classification by Response Shape

Butterworth: maximally flat passband. Chebyshev: passband ripple, steeper roll-off. Bessel: linear phase. Elliptic: ripple in both bands, sharpest cutoff.

Order and Roll-Off

An \(n\)-th order filter rolls off at \(20n\) dB/decade beyond the cutoff — sharper transition requires more components.

First-Order Low-Pass Filter

First-order active low-pass filter with RC network at the non-inverting input and gain-setting resistors R1 Rf at the inverting side — First-order active low-pass filter. The RC network at the non-inverting input sets the cutoff frequency; \(R_f\) and \(R_1\) set the DC gain \(A_0\). Roll-off is −20 dB/decade beyond \(f_c\).

Transfer Function

\[ H(s) = \dfrac{A_0}{1 + s/\omega_c}, \quad A_0 = 1+\dfrac{R_f}{R_1}, \quad f_c = \dfrac{1}{2\pi RC} \] At \(f = f_c\): \(|H| = A_0/\sqrt{2}\) (i.e. −3 dB). Roll-off: −20 dB/decade.

Second-Order Low-Pass Filter (Sallen-Key)

Second-order Sallen-Key low-pass filter with two RC sections providing 40 dB per decade roll-off, and a non-inverting amplifier with Ra Rb setting the Q factor — Second-order Sallen-Key low-pass filter. Two RC stages provide −40 dB/decade roll-off. In the equal-component design (\(R_1 = R_2 = R\), \(C_1 = C_2 = C\)), Butterworth response is achieved when \(A_0 = 1.586\) (\(Q = 0.707\)).

Transfer Function

\[ H(s) = \dfrac{A_0\,\omega_o^2}{s^2 + (\omega_o/Q)s + \omega_o^2}, \quad \omega_o = \dfrac{1}{\sqrt{R_1 R_2 C_1 C_2}} \] Equal-component design: \(f_o = 1/(2\pi RC)\), \(Q = 1/(3-A_0)\). Butterworth: \(A_0 = 1.586\).

High-Pass Filters

A first-order HPF is obtained by interchanging \(R\) and \(C\) in the LPF circuit:

\[ H(s) = \dfrac{A_0\,s/\omega_c}{1 + s/\omega_c}, \quad f_c = \dfrac{1}{2\pi RC}, \quad A_0 = 1+\dfrac{R_f}{R_1} \]

The second-order HPF (Sallen-Key) is obtained by swapping \(R\) and \(C\) in the 2nd-order LPF:

\[ H(s) = \dfrac{A_0\,s^2}{s^2 + (\omega_o/Q)s + \omega_o^2} \]

Band-Pass Filters

A wideband BPF is formed by cascading an HPF (cutoff \(f_L\)) and an LPF (cutoff \(f_H\)) with \(f_L < f_H\).

BPF Parameters

\[ f_o = \sqrt{f_L f_H}, \quad BW = f_H - f_L, \quad Q = f_o/BW \] \(Q < 10\): wideband BPF (cascade HPF + LPF). \(Q > 10\): narrow-band (use Multiple-Feedback BPF).

Multiple-Feedback Band-Pass Filter

For \(C_1 = C_2 = C\):

\[ f_o = \dfrac{1}{2\pi C}\sqrt{\dfrac{R_1+R_2}{R_1 R_2 R_3}}, \quad Q = \pi f_o R_3 C, \quad A_o = -\dfrac{R_3}{2R_1} \]

State-Variable Filter (KHN Biquad)

State-variable (KHN) filter block diagram: summing-inverting amplifier feeding two cascaded integrators with dual feedback paths, producing high-pass, band-pass, and low-pass outputs simultaneously — State-variable (Kerwin-Huelsman-Newcomb) biquad filter. A two-integrator loop produces three simultaneous outputs — high-pass, band-pass, and low-pass — from a single circuit. The resonant frequency \(\omega_o = 1/RC\) and quality factor \(Q\) are independently tunable.

Design

\[ \omega_o = \dfrac{1}{RC}, \quad Q \text{ set by resistor ratio} \] Commercial ICs: UAF42, AF100. Advantages: low component sensitivity; \(\omega_o\) and \(Q\) independently adjustable.

Band-Stop (Notch) Filter

Eliminates a single interfering frequency, such as 50/60 Hz mains hum from ECG signals. Two common designs:

Twin-T notch: Highest selectivity, requires precise component matching. \(f_n = 1/(2\pi RC)\).
Wide-band BSF: Cascade LPF and HPF in parallel via a summing amplifier.

All-Pass Filter (Phase Equalizer)

Passes all frequencies with constant unity amplitude but variable phase — used to correct phase distortion in cables and communication channels.

Transfer Function

\[ H(s) = \dfrac{1 - sRC}{1 + sRC}, \quad |H(j\omega)| = 1\ \forall\,\omega, \quad \phi(\omega) = -2\arctan(\omega RC) \] At \(\omega = 1/RC\): \(\phi = -90^\circ\). As \(\omega \to \infty\): \(\phi \to -180^\circ\).

Section 08

Special-Purpose ICs

The 555 Timer

Introduced in 1972 by Hans Camenzind (Signetics), the 555 timer is one of the most-sold integrated circuits in history. Internal blocks include a three-resistor voltage divider setting thresholds at \(V_{CC}/3\) and \(2V_{CC}/3\), two comparators, an SR flip-flop, a 200 mA output buffer, and a discharge transistor.

NE555 internal block diagram: three 5kΩ resistor divider, two comparators for threshold and trigger, SR flip-flop, discharge transistor, and output buffer driver — Internal architecture of the NE555 timer. The three 5 kΩ resistors set the comparator reference voltages at \(V_{CC}/3\) (trigger) and \(2V_{CC}/3\) (threshold). The SR flip-flop controls the output and the discharge transistor.

Astable Mode (Continuous Square Wave)

\[ T_H = 0.693\,(R_A + R_B)\,C \] \[ T_L = 0.693\,R_B\,C \] \[ f = \dfrac{1.44}{(R_A + 2R_B)C}, \quad D = \dfrac{R_A+R_B}{R_A+2R_B} \] Duty cycle is always \(>50\%\) (add a diode across \(R_B\) for \(D < 50\%\)).

Monostable Mode (Single Pulse)

\[ T = 1.1\,R\,C \] Applications: pulse generators, PWM controllers, frequency-to-voltage converters, touch switches, servo-motor drivers.

Voltage-Controlled Oscillator (VCO)

An oscillator whose output frequency varies linearly with a control voltage \(V_c\):

\[ f_o = f_c + K_{VCO}\,V_c \quad [\text{Hz/V}] \]

NE566 design equation: \(f_o = 2(V_{CC}-V_c)/(R_1 C_1 V_{CC})\), with \(R_1\) in 2–20 kΩ and \(f_{\max} \approx 1\) MHz. Applications: FM modulators, PLL building blocks, function generators.

Phase-Locked Loop (PLL)

Phase-locked loop block diagram with three blocks in a closed loop: Phase Detector, Low-Pass Filter, and VCO, with output fed back to the phase detector — PLL block diagram. The phase detector compares the input signal \(v_s\) with the VCO output, generating an error voltage \(v_e\). The low-pass filter removes high-frequency components to produce the control voltage \(v_c\) that tunes the VCO to track the input frequency.

PLL Key Parameters

\[ \text{Lock range:}\ \Delta f_L = \pm\dfrac{8 f_o}{V_{CC}} \] \[ \text{Capture range:}\ \Delta f_C = \pm\sqrt{\dfrac{\Delta f_L}{2\pi\tau}} \] ICs: NE565, CD4046. Applications: FM demodulation, FSK demodulation, clock recovery, frequency synthesis.

Digital-to-Analog Converters (DAC)

Weighted-Resistor DAC

Each digital bit drives an input through a binary-weighted resistor. Problems: requires a wide range of resistor values (1× to \(2^n\times\)) which is difficult to maintain accurately for high-bit-count converters.

\[ v_o = -V_{ref}\dfrac{R_f}{R}\!\left(b_3\cdot\tfrac{1}{1}+b_2\cdot\tfrac{1}{2}+b_1\cdot\tfrac{1}{4}+b_0\cdot\tfrac{1}{8}\right) \]

R-2R Ladder DAC

R-2R ladder network DAC: series R resistors form the horizontal rail, shunt 2R resistors connect to bit switches, with the output driving an op-amp summing junction — R-2R ladder DAC architecture. Only two resistor values (\(R\) and \(2R\)) are needed regardless of the number of bits, making this the dominant DAC architecture in practical ICs.

R-2R Output

\[ v_o = -\dfrac{R_f}{2R}\cdot V_{ref}\cdot\dfrac{D}{2^n} \] Resolution: \(\Delta v_o = V_{ref}/(2^n) \cdot R_f/(2R)\).

Analog-to-Digital Converters (ADC)

Type	Principle	Speed	Resolution
Flash	\(2^n-1\) comparators vs. resistor ladder	Very fast (GS/s)	Low (8-bit)
Successive Approx. (SAR)	Binary search via DAC + comparator	Medium (MS/s)	Medium (12–18-bit)
Dual-slope (integrating)	Integrates input then reference; counts time	Slow (S/s–kS/s)	Very high (22-bit)
Sigma-Delta (ΣΔ)	Oversampling + noise-shaping + decimation	Slow–medium	Very high (24-bit audio)
Counter (ramp)	Compares input to counter-driven DAC ramp	Slow	Medium

Key Spec: Resolution

\[ \Delta V_{\min} = \dfrac{V_{ref}}{2^n} \quad (n = \text{bits}) \] Example: 12-bit ADC with \(V_{ref} = 5\) V: \(\Delta = 5/4096 \approx 1.2\) mV.

Successive-Approximation Register (SAR) ADC

For an \(n\)-bit converter, \(n\) comparison clocks are needed. The algorithm: (1) try MSB = 1 — if DAC output \(> v_i\), reset it to 0, else keep 1; (2) move to the next bit and repeat; (3) after \(n\) steps the SAR holds the digital code closest to \(v_i\). Conversion time: \(n\) clocks. Example ICs: ADS7886, ADC0808, MCP3008.

SAR ADC block diagram: comparator receives analog input vi and DAC feedback voltage, SAR logic processes comparator output and drives the DAC with an n-bit code, producing digital output after n clock cycles — Successive-Approximation Register (SAR) ADC. The SAR logic performs a binary search: at each clock cycle one bit is resolved by comparing \(v_i\) against the DAC output. After \(n\) cycles the \(n\)-bit digital code converges to the closest representation of \(v_i\).

Section 09

Frequency Response and Stability

Compensation and Stability

Each pole of \(A_{OL}(s)\) adds 90° of phase lag. If the total phase lag reaches 180° at the frequency where \(|A_{OL}\beta| = 1\), negative feedback becomes positive feedback — leading to oscillation.

Stability Criteria

Gain Margin (GM): \(-|A_{OL}\beta|_{dB}\) at the phase-180° crossover frequency.
Phase Margin (PM): \(180^\circ - |\angle A_{OL}\beta|\) at the unity-gain frequency.
Rule of thumb: PM ≥ 45°, GM ≥ 6 dB.

Compensation Techniques

Dominant-pole: Add a large internal capacitor \(C_C\) to push the first pole to very low frequency so that by the unity-gain frequency the phase lag is still only ~90°. Done internally in the 741.
Pole-zero: Cancel an unwanted pole with a zero in the compensation network.
Feed-forward: Bypass a slow internal stage for high-frequency signals.
External compensation: Non-internally-compensated op-amps (e.g. 301A) let the designer tailor compensation for each application.

Bode plot of a single-pole compensated op-amp: magnitude plot showing constant open-loop gain then −20 dB per decade roll-off from f1 to fT; phase plot showing 0° at DC trending to −90° at high frequency, well clear of −180° — Bode plot of a dominant-pole compensated op-amp. The single-pole roll-off limits phase lag to −90° at the unity-gain frequency, giving a phase margin of 90° — ensuring unconditional stability for all closed-loop gains and feedback fractions.

Reading the Plot

A single-pole roll-off gives only 90° of phase lag at unity gain → PM = 90°, i.e. stable for any \(\beta\). This is why internally compensated op-amps are easy to use with arbitrary feedback networks.

Voltage-Feedback (VFA) vs. Current-Feedback (CFA) Op-Amps

Property	Voltage-Feedback (VFA)	Current-Feedback (CFA)
Internal topology	High-Z differential inputs; output ∝ differential voltage	Low-Z inverting input (transimpedance node); buffer between + and −
Open-loop quantity	Gain \(A_{OL}\) (V/V)	Transimpedance \(Z_T\) (Ω)
GBW behaviour	GBW = const; \(f_T\) trades linearly with gain	BW set by \(R_f\) alone; independent of closed-loop gain
Slew rate	Limited by tail current of input pair	Very high — internal node charges from a low-Z buffer
Stable feedback	Any resistor ratio; capacitor allowed in feedback	\(R_f\) must lie in a recommended range (~500 Ω–1.5 kΩ); no capacitor across \(R_f\)
Examples	741, OP07, OPA227	AD844, LT1223, OPA683

Rule of thumb: VFA — precision DC, low-frequency, low-noise, instrumentation work. CFA — video, high-speed line drivers, ADC drivers needing large bandwidth at high closed-loop gain.

Course Summary

Built from ideal to practical: golden rules → real DC/AC limitations
Mastered the differential pair and negative feedback core
Closed-loop topologies: inverting, non-inverting, follower
Linear blocks: summer, difference, instrumentation, integrator, differentiator, V–I/I–V, Howland, charge amplifier
Non-linear blocks: comparators, Schmitt trigger, oscillators, precision rectifiers, log/antilog, sample-and-hold, peak detector
Active filters: LPF, HPF, BPF, BSF, all-pass, state-variable (KHN biquad)
Special ICs: 555 timer, VCO, PLL, DAC (weighted and R-2R), ADC (Flash, SAR, Dual-slope, Sigma-Delta)
Noise, frequency response, stability margins, VFA vs. CFA

The op-amp is the universal analog building block. Once you internalise the two golden rules and the feedback equation \(A_f = A/(1+A\beta)\), every circuit in these notes becomes a short exercise in algebra.