Analog Electronics: From Fundamentals to GATE Mastery

Analog electronics studies how continuous voltage and current signals are generated, amplified, shaped and conditioned using semiconductor devices. This complete revision guide walks through eleven core modules — beginning with semiconductor physics and ending with advanced building blocks such as data converters and switching regulators — followed by a quick-reference formula sheet and worked GATE-style examples. Throughout, the emphasis is on the relationships and formulas that recur most often in examinations.

How to use these notes. Each module is self-contained: read the conceptual explanation, study the boxed formulas, then test yourself against the worked examples near the end. The suggested study sequence is semiconductor physics → diodes → BJT and FET → op-amp golden rules → feedback → frequency response → oscillators and power amplifiers.

Module 01

Semiconductor Physics

Energy Band Theory

The electrical behaviour of a material is set by the gap between its valence and conduction bands. Conductors have overlapping valence and conduction bands; insulators have a large band gap \(E_g > 3\) eV; semiconductors have a small, intermediate gap.

Silicon (Si): \(E_g = 1.12\) eV
Germanium (Ge): \(E_g = 0.67\) eV
Gallium Arsenide (GaAs): \(E_g = 1.43\) eV

Energy-band diagrams of a conductor with overlapping valence and conduction bands, a semiconductor with a small band gap, and an insulator with a wide band gap. — Figure 2. Why materials conduct, semiconduct or insulate — the size of the band gap separating the valence and conduction bands.

Key Formulas

\[ \begin{aligned} n_i^2 &= N_c N_v \, e^{-E_g/kT} \\ np &= n_i^2 \quad \text{(Mass-Action Law)} \\ E_{Fi} &= \tfrac{E_c + E_v}{2} + \tfrac{kT}{2}\ln\!\tfrac{N_v}{N_c} \end{aligned} \] \(E_{Fi}\) is the intrinsic Fermi level, which sits mid-gap when \(N_c = N_v\).

Intrinsic and Extrinsic Semiconductors

Intrinsic & N-type

Intrinsic: pure material, \(n = p = n_i\), conductivity \(\sigma = q\,n_i(\mu_n + \mu_p)\).
N-type (donor): Group V dopants (P, As, Sb); electrons are majority carriers; \(n \approx N_D\), \(p = n_i^2/N_D\).

P-type (Acceptor)

Group III dopants (B, Al, Ga).
Holes are the majority carriers.
\(p \approx N_A\), \(n = n_i^2/N_A\).

Carrier Transport

\[ \begin{aligned} J_{\text{drift}} &= q(n\mu_n + p\mu_p)\,E \\ J_{\text{diff}} &= qD_n\frac{dn}{dx} - qD_p\frac{dp}{dx} \\ \frac{D_n}{\mu_n} &= \frac{D_p}{\mu_p} = \frac{kT}{q} = V_T \end{aligned} \] Einstein relation links diffusion and mobility. At 300 K, \(V_T \approx 25.85\) mV \(\approx 26\) mV.

GATE Tip

At 300 K, \(n_i\) for silicon \(\approx 1.5\times10^{10}\ \text{cm}^{-3}\). Memorise this — it appears in many GATE numericals.

Hall Effect and the Continuity Equation

A magnetic field \(B_z\) applied to a current-carrying bar deflects carriers and produces a transverse Hall voltage \(V_H\). The sign of the Hall coefficient reveals the carrier type.

Hall-effect setup: a current Ix flows along a semiconductor bar while a magnetic field Bz points out of the page, deflecting carriers and producing a transverse Hall voltage VH. — Figure 3. Hall-effect measurement geometry used to find carrier type, concentration and mobility from the transverse voltage.

Hall Voltage & Coefficient

\[ V_H = \frac{I_x B_z}{n q t},\qquad R_H = \frac{1}{n q} \] A negative \(R_H\) indicates n-type, positive indicates p-type. Mobility follows from \(\mu = R_H \sigma\).

Continuity (Minority Carriers, p-type)

\[ \frac{\partial n_p}{\partial t} = D_n\frac{\partial^2 n_p}{\partial x^2} - \frac{n_p - n_{p0}}{\tau_n} + G_n \] In steady state with no generation, \(n_p(x) - n_{p0} = \Delta n(0)\,e^{-x/L_n}\) with diffusion length \(L_n = \sqrt{D_n \tau_n}\).

GATE Tip

Diffusion lengths \(L_n, L_p\) govern BJT base transport and the diode reverse-saturation current \(I_S \propto 1/L_{n,p}\). These appear frequently in numerical problems.

Module 02

PN Junction and Diodes

Built-in Potential

PN junction showing a depletion region of fixed charge at the metallurgical junction, the internal electric field pointing from the n-side to the p-side, and the potential rising across the junction to the built-in value Vbi. — Figure 4. The depletion region and built-in potential V(x) that form when p- and n-type material meet.

Built-in Voltage

\[ V_{bi} = V_T \ln\!\left(\frac{N_A N_D}{n_i^2}\right) \] Typical values: Si 0.6–0.7 V; Ge 0.2–0.3 V.

Depletion & Diffusion Capacitance

\[ \begin{aligned} W &= \sqrt{\tfrac{2\varepsilon_s}{q}\tfrac{N_A+N_D}{N_A N_D}(V_{bi}-V)} \\ C_j &= \frac{C_{j0}}{\sqrt{1 - V/V_{bi}}}, \quad C_d = \frac{\tau_T I_D}{\eta V_T} \end{aligned} \] Reverse bias uses \(C_j\); forward bias adds \(C_d\); total \(C = C_j + C_d\).

GATE Tip. Reverse bias widens the depletion region (\(W\uparrow\)) and lowers junction capacitance (\(C_j\downarrow\)) — exactly the mechanism a varactor diode exploits.

I–V Characteristics and the Shockley Equation

Diode current-voltage characteristic: exponential forward conduction beyond the cut-in voltage, a small reverse-leakage current, and a sharp reverse-breakdown knee. — Figure 5. Diode I–V curve, highlighting the forward, reverse-leakage and breakdown regions.

Shockley Diode Equation

\( I_D = I_S\!\left(e^{V_D/\eta V_T} - 1\right) \)

\(I_S\) is the reverse-saturation current; \(\eta\) the ideality factor (1 for Ge, 1–2 for Si); \(V_T = kT/q \approx 26\) mV at 300 K.

Dynamic Resistance

\[ r_d = \frac{\partial V_D}{\partial I_D} = \frac{\eta V_T}{I_D} \] At \(I_D = 1\) mA, \(r_d \approx 26\ \Omega\).

Three Diode Models

Ideal: \(V_\gamma = 0\), \(r_d = 0\).
Constant voltage drop: \(V_\gamma = 0.7\) V.
Piecewise-linear: \(V_\gamma + r_d\).

Rectifiers

Half-Wave Rectifier (HWR)

\[ \begin{aligned} V_{dc} &= \tfrac{V_m}{\pi}, \quad I_{dc} = \tfrac{V_m}{\pi R_L} \\ V_{rms} &= \tfrac{V_m}{2}, \quad \eta = 40.6\% \\ \gamma &= 1.21, \quad \text{PIV} = V_m \end{aligned} \]

Full-Wave Rectifier (FWR)

\[ \begin{aligned} V_{dc} &= \tfrac{2V_m}{\pi}, \quad I_{dc} = \tfrac{2V_m}{\pi R_L} \\ V_{rms} &= \tfrac{V_m}{\sqrt{2}}, \quad \eta = 81.2\% \\ \gamma &= 0.482, \quad \text{PIV} = V_m \end{aligned} \]

Zener Diode and Voltage Regulation

Zener shunt regulator schematic: input voltage Vin feeds a series resistor Rs into a Zener diode that clamps the output Vo across a parallel load RL. — Figure 7. Zener shunt regulator — the diode clamps the output voltage as line and load conditions vary.

Breakdown Mechanisms

Zener (heavy doping): \(V_Z < 5\) V, negative temperature coefficient.
Avalanche (light doping): \(V_Z > 7\) V, positive temperature coefficient.
Around 5–6 V both occur, giving near-zero TC.

Design Equations

\[ \begin{aligned} R_s &= \frac{V_{in,\min} - V_Z}{I_{Z,\min} + I_{L,\max}} \\ I_Z &= I_s - I_L, \quad I_s = \frac{V_{in}-V_Z}{R_s} \\ P_{Z,\max} &= V_Z\,I_{Z,\max} \end{aligned} \]

Line & Load Regulation

Line regulation: \(\Delta V_o = \dfrac{r_Z}{R_s + r_Z}\,\Delta V_{in}\). Load regulation: \(\Delta V_o = -(r_Z \| R_s)\,\Delta I_L\), where \(r_Z\) is the Zener dynamic resistance.

Special Diodes

Diode Type	Key Principle	Primary Application
Schottky	Metal–semiconductor junction; \(V_\gamma \approx 0.3\) V, no minority-carrier storage	High-speed switching, SMPS rectifiers
Zener	Reverse-breakdown regulation	Voltage references, regulators, clippers
Varactor	Voltage-variable capacitance, \(C_j \propto 1/\sqrt{V_R}\)	VCOs, tuned circuits, FM modulation
Tunnel	Quantum tunnelling; negative-resistance region	High-frequency oscillators and amplifiers
LED	Direct-bandgap recombination emits photons	Displays, indicators, optocouplers
Photodiode	Photons generate electron-hole pairs in the depletion region	Optical sensors, fibre-optic receivers
PIN	Intrinsic layer gives a wide depletion region	RF switches, high-voltage rectification

GATE Focus. A Schottky diode has essentially zero reverse-recovery time (\(t_{rr}\approx 0\)) because it stores no minority carriers — a classic multiple-choice point.

Clippers and Clampers

Clipper (Limiter)

Removes the portion of a waveform above or below a reference level.
Series or shunt configuration.
Positive, negative or biased variants.

Clamper (DC Restorer)

Shifts the DC level without distorting the waveform shape.
Uses a capacitor and diode, optionally with a bias.
Positive or negative clamper.

Clamper Key Result

Output swings 0 to \(2V_m\)

For an ideal positive clamper the capacitor charges to \(V_m\) and holds it, so the output ranges from 0 to \(2V_m\). A negative clamper produces an output from \(-2V_m\) to 0.

Module 03

Bipolar Junction Transistor (BJT)

Structure and Basic Operation

NPN transistor cross-section: a heavily doped N-plus emitter, a thin P-type base and an N-type collector, with electrons injected from emitter to collector across the narrow base. — Figure 8. NPN transistor cross-section, showing the thin base that makes transistor action possible.

Current Relationships

\[ \begin{aligned} I_E &= I_B + I_C \\ \alpha &= \frac{I_C}{I_E} \;(0.95\text{--}0.99), \quad \beta = \frac{I_C}{I_B}\;(50\text{--}400) \\ \beta &= \frac{\alpha}{1-\alpha}, \quad \alpha = \frac{\beta}{\beta+1} \end{aligned} \]

Ebers–Moll (Active Region)

\[ I_C \approx I_S\, e^{V_{BE}/V_T} \quad (V_{BC}\ll 0) \] Transconductance \(g_m = I_C/V_T\). In saturation both junctions are forward-biased and \(V_{CE,\text{sat}}\approx 0.2\) V.

Operating Regions

Region	EB Junction	CB Junction	Application
Cutoff	Reverse	Reverse	Switch OFF
Active	Forward	Reverse	Amplification
Saturation	Forward	Forward	Switch ON
Reverse Active	Reverse	Forward	Rarely used

BJT output characteristics: a family of IC-versus-VCE curves for several base currents IB1, IB2 and IB3, rising steeply in the saturation region then flattening through the active region. — Figure 9. BJT output characteristics and the saturation-to-active boundary that the DC load line crosses at the Q-point.

DC Load Line

\[ V_{CE} = V_{CC} - I_C R_C \] Saturation current \(I_{C,\text{sat}} = V_{CC}/R_C\); cutoff voltage \(V_{CE,\text{cutoff}} = V_{CC}\); the Q-point lies where the load line meets the chosen \(I_B\) curve. Maximum symmetric swing occurs at \(V_{CEQ} = V_{CC}/2\).

Biasing Techniques

Biasing Scheme	Key Equation	Stability Factor \(S\)
Fixed bias	\(I_B = \dfrac{V_{CC}-V_{BE}}{R_B}\)	\(S = 1+\beta\) (poor)
Emitter bias	\(I_B = \dfrac{V_{CC}-V_{BE}}{R_B+(1+\beta)R_E}\)	\(S = \dfrac{1+\beta}{1+\beta R_E/(R_B+R_E)}\)
Collector-to-base	\(I_B = \dfrac{V_{CC}-V_{BE}}{R_B+(1+\beta)R_C}\)	\(S = \dfrac{1+\beta}{1+\beta R_C/(R_B+R_C)}\)
Voltage divider	\(V_{Th}=\dfrac{R_2 V_{CC}}{R_1+R_2},\ R_{Th}=R_1\\|R_2\)	\(S = \dfrac{1+\beta}{1+\beta R_E/(R_{Th}+R_E)}\) (best)

Stability Factor Definitions

\[ S = \frac{\partial I_C}{\partial I_{CO}}\bigg|_{\beta,V_{BE}}, \quad S' = \frac{\partial I_C}{\partial V_{BE}}, \quad S'' = \frac{\partial I_C}{\partial \beta} \] The design goal is to minimise \(S\) so that \(I_C\) is insensitive to \(I_{CO}\), \(V_{BE}\) and \(\beta\).

GATE Tip. Voltage-divider bias is the most stable scheme and is the default choice for analog amplifier design.

Module 04

BJT Small-Signal Analysis

Hybrid-\(\pi\) Model

Hybrid-pi small-signal model of a BJT: input resistance r-pi between base and emitter, a dependent current source gm times v-pi, and output resistance ro between collector and emitter. — Figure 10. Low-frequency hybrid-pi small-signal equivalent of the BJT used for gain calculations.

Small-Signal Parameters

\[ \begin{aligned} g_m &= \frac{I_{CQ}}{V_T} &&\text{(transconductance)} \\ r_\pi &= \frac{\beta}{g_m} = \frac{\beta V_T}{I_{CQ}} &&\text{(input resistance)} \\ r_o &= \frac{V_A}{I_{CQ}} &&\text{(output resistance)} \\ r_e &= \frac{V_T}{I_{EQ}} \approx \frac{\alpha}{g_m} &&\text{(emitter resistance)} \end{aligned} \] \(V_A\) is the Early voltage.

Quick Numbers

At \(I_C = 1\) mA, \(g_m = 38.5\) mA/V. With \(\beta = 100\), \(r_\pi \approx 2.6\ \text{k}\Omega\).

Amplifier Configurations

Parameter	CE	CB	CC (Emitter Follower)
Voltage gain \(A_v\)	\(-g_m(R_C\\|r_o)\)	\(+g_m(R_C\\|r_o)\)	\(\approx 1\)
Current gain \(A_i\)	\(-\beta\) (high)	\(\alpha\;(\approx 1)\)	\(1+\beta\) (high)
Input resistance	\(r_\pi\) (medium)	\(r_e\) (low)	\(r_\pi + (1+\beta)R_E\) (high)
Output resistance	\(R_C\\|r_o\) (high)	Very high	Very low \((\approx 1/g_m)\)
Phase shift	\(180^\circ\)	\(0^\circ\)	\(0^\circ\)
Application	Voltage amplifier	RF, buffer, cascode	Impedance matching

CE with Emitter Degeneration

\[ \begin{aligned} A_v &= -\frac{g_m R_C}{1 + g_m R_E} \approx -\frac{R_C}{R_E}\ (g_m R_E \gg 1) \\ R_{in} &= r_\pi + (1+\beta)R_E \end{aligned} \]

Memory Aid

CE: high \(A_v\) and \(A_i\) — general purpose.
CB: low \(R_{in}\), high bandwidth — RF amplifier.
CC: high \(R_{in}\), low \(R_{out}\) — buffer.

Module 05

Field-Effect Transistors

JFET and MOSFET Structures

JFET (N-channel)

Normally-ON (depletion-mode) device.
\(V_{GS} \le 0\) (reverse bias on the PN gate).
Pinch-off occurs at \(V_{GS} = V_P\).

NMOS Enhancement

Normally-OFF (enhancement-mode) device.
Requires \(V_{GS} > V_{Tn}\) to form a channel.
Dominant device in modern integrated circuits.

FET versus BJT

FET: voltage-controlled, very high \(R_{in}\), unipolar, lower noise, no minority-carrier storage, smaller area. BJT: current-controlled, higher \(g_m\) per unit current, historically faster.

MOSFET I–V Characteristics

MOSFET output characteristics: ID-versus-VDS curves for increasing VGS, each rising parabolically through the triode region and flattening into saturation beyond VDS equal to the overdrive voltage. — Figure 12. NMOS output characteristics, with the dashed locus marking the triode-to-saturation boundary VDS = Vov.

Three Operating Regions (NMOS)

\[ \begin{aligned} \textbf{Cutoff:}\ & V_{GS} < V_{Tn} \Rightarrow I_D = 0 \\ \textbf{Triode:}\ & I_D = \mu_n C_{ox}\tfrac{W}{L}\!\left[V_{ov}V_{DS} - \tfrac{V_{DS}^2}{2}\right] \\ \textbf{Saturation:}\ & I_D = \tfrac{1}{2}\mu_n C_{ox}\tfrac{W}{L}V_{ov}^2(1+\lambda V_{DS}) \end{aligned} \] The overdrive voltage is \(V_{ov} = V_{GS} - V_{Tn}\).

GATE Tip. In saturation, transconductance can be written three equivalent ways: \(g_m = \mu_n C_{ox}\tfrac{W}{L}V_{ov} = \dfrac{2I_D}{V_{ov}} = \sqrt{2\mu_n C_{ox}\tfrac{W}{L}I_D}\).

Small-Signal Model and CS Amplifier

MOSFET small-signal model with an open gate, a dependent source gm times vgs and output resistance ro, shown beside a common-source amplifier with a gate-bias divider, drain resistor RD and bypassed source resistor. — Figure 13. MOSFET small-signal model (left) and the common-source amplifier it analyses (right).

Key Parameters

\[ g_m = \sqrt{2\mu_n C_{ox}\tfrac{W}{L}I_D}, \quad r_o \approx \frac{1}{\lambda I_D}, \quad R_{in}\to\infty \]

CS Amplifier Gain

\[ A_v = -g_m(R_D \| r_o \| R_L) \] With source degeneration, \(A_v = -\dfrac{g_m R_D}{1+g_m R_S}\).

MOSFET Configurations Summary

Parameter	CS	CG	CD (Source Follower)
\(A_v\)	\(-g_m(R_D\\|r_o)\) (high)	\(+g_m(R_D\\|r_o)\) (high)	\(\dfrac{g_m R_S}{1+g_m R_S}\approx 1\)
\(R_{in}\)	\(R_{G1}\\|R_{G2}\) (high)	\(1/g_m\) (low)	\(R_{G1}\\|R_{G2}\) (high)
\(R_{out}\)	\(R_D\\|r_o\) (high)	High	\(\approx 1/g_m\) (low)
Phase	\(180^\circ\)	\(0^\circ\)	\(0^\circ\)
Use	General amplifier	Cascode, RF	Buffer

Cascode Amplifier: CS + CG Stack

Cascode amplifier schematic: a common-source input transistor M1 driven by vi feeds its drain current into a common-gate transistor M2 biased at VB2, with drain resistor RD setting the output vo. — Figure 14. MOSFET cascode (CS + CG) — high output resistance and suppressed Miller effect for wideband, high-gain operation.

Why Cascode?

\(M_1\) sees a low load (\(\approx 1/g_{m2}\)), so Miller multiplication of \(C_{gd1}\) is suppressed.
Output resistance is boosted: \(R_{out}\approx g_{m2}\,r_{o2}\,r_{o1}\).
DC gain \(|A_v|\approx g_{m1}(R_D \| R_{out})\).
Bandwidth increases at constant gain.

Body Effect

When \(V_{SB}\neq 0\): \(V_{Tn} = V_{Tn0} + \gamma\!\left(\sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F}\right)\), which adds a body transconductance \(g_{mb}\) in parallel with \(g_m\). The folded cascode restores headroom at low \(V_{DD}\) and is standard in CMOS op-amps.

GATE Tip. The cascode is the single most exam-worthy high-gain stage. Remember its three signatures: high \(R_{out}\), broadband response and low Miller effect.

Module 06

Frequency Response

Amplifier Frequency Response

Amplifier Bode magnitude plot: gain rises to the lower cutoff fL, stays flat at the mid-band gain Am, then rolls off above the upper cutoff fH, with the half-power points sitting three decibels below Am. — Figure 15. Amplifier frequency response — the flat mid-band bounded by the lower and upper cutoff frequencies.

Key Frequencies

\[ \begin{aligned} f_L &= \frac{1}{2\pi R_{eq,L}\,C_L} \\ f_H &= \frac{1}{2\pi R_{eq,H}\,C_H} \\ BW &= f_H - f_L \approx f_H \end{aligned} \]

Capacitor Roles

Sets \(f_L\): coupling capacitors \(C_{C1}, C_{C2}\) and the bypass capacitor \(C_E\) or \(C_S\). Sets \(f_H\): device capacitances \(C_\pi, C_\mu, C_{gs}, C_{gd}\); the Miller effect amplifies \(C_\mu\) / \(C_{gd}\).

Miller Effect and Gain-Bandwidth Product

Miller's Theorem

\[ \begin{aligned} Z_{in,M} &= \frac{Z}{1-A_v}, \quad Z_{out,M} \approx Z \\ C_{in,M} &= C(1-A_v) = C(1+|A_v|) \end{aligned} \] The capacitor form applies to an inverting amplifier.

Gain-Bandwidth Product

\[ \text{GBW} = |A_m|\times f_H = \text{const (1-pole)} \] \[ f_T = \frac{g_m}{2\pi(C_\pi + C_\mu)} \approx \frac{g_m}{2\pi C_\pi} \]

Consequences of the Miller Effect

Input capacitance is multiplied by \((1+|A_v|)\).
The dominant pole shifts to a lower frequency.
Bandwidth is reduced.
This is the primary motivation for the cascode topology.

GATE Insight. In a single-pole system the GBW is invariant, so doubling \(A_v\) halves \(f_H\). Cascading \(n\) identical stages shrinks the overall bandwidth by the factor \(\sqrt{2^{1/n}-1}\).

Time-Constant Methods for \(f_L\) and \(f_H\)

Open-Circuit Time Constants (OCTC)

Estimates the upper cutoff \(f_H\) from device capacitances:

Set the input source to zero.
Open all other capacitors; for each \(C_i\), find the resistance \(R_{io}\) seen by it.
Sum the time constants: \(\tau_H = \sum_i R_{io}C_i\), so \(f_H \approx \dfrac{1}{2\pi\tau_H}\).

Short-Circuit Time Constants (SCTC)

Estimates the lower cutoff \(f_L\) from coupling and bypass capacitors:

Short every other capacitor; for each \(C_j\), find the resistance \(R_{js}\) seen by it.
Sum the inverse time constants: \(\omega_L \approx \sum_j \dfrac{1}{R_{js}C_j}\), so \(f_L \approx \dfrac{\omega_L}{2\pi}\).

GATE Shortcut. The capacitor with the smallest \(RC\) product sets \(f_L\); the one with the largest \(RC\) product sets \(f_H\). Single-capacitor dominance is common in multiple-choice questions.

Module 07

Feedback Amplifiers

Fundamental Concepts

Negative-feedback block diagram: input xi enters a summing junction, the error signal xe drives the forward amplifier A to produce output xo, and a feedback network beta returns xf to be subtracted at the summer. — Figure 16. Generic negative-feedback amplifier, the basis of the closed-loop gain expression Af = A/(1+A-beta).

The signals are: input \(x_i\) and output \(x_o\); the error signal \(x_e = x_i - x_f\); and the feedback signal \(x_f = \beta x_o\).

Closed-Loop Gain

\( A_f = \dfrac{A}{1+A\beta} \)

Here \(A\beta\) is the loop gain and \(1 + A\beta\) the return difference. For \(A\beta > 0\) feedback is negative (\(|A_f|<|A|\)); for \(A\beta < 0\) it is positive (\(|A_f|>|A|\)); and \(A\beta = -1\) gives sustained oscillation.

Benefits of Negative Feedback

Gain sensitivity is reduced by \((1+A\beta)\); distortion is divided by \((1+A\beta)\); bandwidth is multiplied by \((1+A\beta)\); and input/output impedances are modified in a topology-dependent way.

Four Feedback Topologies

Topology	Sampled	Mixed	Stabilises
Voltage-Series (Series-Shunt)	Voltage	Voltage	Voltage gain \(A_v\)
Current-Series (Series-Series)	Current	Voltage	Transconductance \(G_m\)
Voltage-Shunt (Shunt-Shunt)	Voltage	Current	Transresistance \(R_m\)
Current-Shunt (Shunt-Series)	Current	Current	Current gain \(A_i\)

Impedance Modification

\[ \begin{aligned} \textbf{Series in:}\ & R_{if} = R_i(1+A\beta)\ \uparrow \\ \textbf{Shunt in:}\ & R_{if} = \tfrac{R_i}{1+A\beta}\ \downarrow \\ \textbf{Voltage out:}\ & R_{of} = \tfrac{R_o}{1+A\beta}\ \downarrow \\ \textbf{Current out:}\ & R_{of} = R_o(1+A\beta)\ \uparrow \end{aligned} \]

Mnemonic

Series input ⇒ \(R_{in}\) increases.
Shunt input ⇒ \(R_{in}\) decreases.
Voltage output ⇒ \(R_{out}\) decreases.
Current output ⇒ \(R_{out}\) increases.

In short: "make it look like what you sample."

Module 08

Oscillators

Oscillator Fundamentals

Barkhausen Criterion

For sustained sinusoidal oscillation two conditions must hold simultaneously:

Magnitude: \(|A\beta| = 1\).
Phase: \(\angle A\beta = 0^\circ\) (or \(360^\circ\)).

At start-up \(|A\beta|\gtrsim 1\); circuit nonlinearity then settles the loop gain to unity.

Common Oscillator Frequencies

\[ \begin{aligned} \textbf{RC phase-shift:}\ & f = \tfrac{1}{2\pi RC\sqrt{6}}\ (|A|\ge 29) \\ \textbf{Wien bridge:}\ & f = \tfrac{1}{2\pi RC}\ (|A|\ge 3) \\ \textbf{Hartley:}\ & f = \tfrac{1}{2\pi\sqrt{(L_1+L_2)C}} \\ \textbf{Colpitts:}\ & f = \tfrac{1}{2\pi\sqrt{L\,C_{eq}}},\ C_{eq} = \tfrac{C_1 C_2}{C_1+C_2} \end{aligned} \]

Memory hook. Hart-L uses two inductors; Col-C uses two capacitors. Classifying further: RC oscillators serve audio (<1 MHz), LC oscillators serve RF, and crystals give the highest frequency stability.

Crystal Oscillator

Quartz crystal equivalent circuit: a motional arm of Ls, Cs and Rs in series, shunted by the package capacitance CP; the reactance is zero at the series resonance fs and diverges at the parallel resonance fp. — Figure 17. Piezoelectric crystal model and its reactance curve — inductive only in the narrow band between fs and fp.

Resonant Frequencies

\[ f_s = \frac{1}{2\pi\sqrt{L_s C_s}} \quad (\text{impedance minimum}) \] \[ f_p = \frac{1}{2\pi\sqrt{L_s C_{eq}}}, \quad C_{eq} = \frac{C_s C_P}{C_s + C_P} \] Since \(C_s \ll C_P\), \(f_p\) lies just above \(f_s\).

Why Crystals?

Quality factor \(Q \sim 10^4\)–\(10^6\), stability around 1 ppm, and an inductive reactance between \(f_s\) and \(f_p\) that oscillators exploit. Used in clocks, microcontrollers and communications.

Module 09

Operational Amplifiers

Ideal versus Practical Op-Amp

Ideal Op-Amp Properties

Open-loop gain \(A_{OL} = \infty\).
Input resistance \(R_{in} = \infty\) (no input current).
Output resistance \(R_{out} = 0\).
\(BW = \infty\), CMRR \(= \infty\), slew rate \(= \infty\).

Practical Non-idealities

Input offset voltage \(V_{OS}\) (mV).
Input bias current \(I_B = (I_{B+}+I_{B-})/2\).
Input offset current \(I_{OS} = |I_{B+}-I_{B-}|\).
CMRR \(= 20\log(A_d/A_{CM})\) dB; PSRR for supply rejection.
Slew rate \(SR = dV_o/dt|_{\max}\); finite GBW.

Full-Power Bandwidth

\[ f_{\max} = \frac{SR}{2\pi V_{o,\text{peak}}} \] For a µA741 (\(SR = 0.5\) V/µs, \(V_p = 10\) V), \(f_{\max} \approx 8\) kHz.

The Golden Rules

Two Golden Rules (with negative feedback)

\(I_+ = I_- = 0\) and \(v_+ = v_-\)

No current enters the inputs, and the output drives the input difference to zero (a virtual short). These two rules solve roughly 90% of GATE op-amp problems.

Inverting amplifier schematic: input vi through resistor R1 to the inverting input, feedback resistor Rf from output to that node, and the non-inverting input grounded. — Figure 18a. Inverting amplifier: gain Av = -Rf/R1 with input resistance R1 and a virtual ground at the inverting node.

Non-inverting amplifier schematic: input vi applied to the non-inverting terminal, resistor R1 from the inverting input to ground, and feedback resistor Rf from output to the inverting input. — Figure 18b. Non-inverting amplifier: gain Av = 1 + Rf/R1 with very high input resistance.

Op-Amp Circuit Zoo

Circuit	Transfer Function	Notes
Summing amplifier	\(v_o = -R_f\!\left(\tfrac{v_1}{R_1} + \tfrac{v_2}{R_2} + \cdots\right)\)	Inverting; scales and sums inputs
Difference amplifier	\(v_o = \dfrac{R_f}{R_1}(v_2 - v_1)\) (matched)	CMRR depends on resistor matching
Integrator	\(v_o = -\dfrac{1}{RC}\displaystyle\int v_i\,dt\)	Add \(R_f\) across \(C\) for DC stability
Differentiator	\(v_o = -RC\dfrac{dv_i}{dt}\)	Noise-sensitive; add input \(R_s\)
Instrumentation amp	\(A_v = \!\left(1+\tfrac{2R_1}{R_G}\right)\!\tfrac{R_3}{R_2}\)	Three-op-amp; very high CMRR
Voltage follower	\(v_o = v_i\)	\(A_v = 1\); highest buffer isolation
Schmitt trigger (inv.)	\(V_{TH} = \dfrac{R_1}{R_1+R_2}V_{sat}\)	Hysteresis \(= V_{TH} - V_{TL}\)
Log amplifier	\(v_o = -V_T \ln(v_i / I_S R)\)	Diode or BJT in feedback
Active first-order LPF	\(A(s) = -\dfrac{R_f/R_1}{1 + sR_fC_f}\)	\(f_c = \dfrac{1}{2\pi R_f C_f}\)

Integrator, Differentiator and Schmitt Trigger

Op-amp integrator schematic: an input resistor R drives the inverting node and a feedback capacitor C connects output to that node. — Figure 19a. Integrator — output is the negative time-integral of the input, vo = -(1/RC) integral of vi dt.

Op-amp differentiator schematic: an input capacitor C drives the inverting node and a feedback resistor R connects output to that node. — Figure 19b. Differentiator — output is proportional to the input slope, vo = -RC times dvi/dt.

Op-amp Schmitt trigger schematic: positive feedback through resistors R1 and R2 from the output to the non-inverting input sets two switching thresholds. — Figure 19c. Schmitt trigger — hysteresis between thresholds at plus/minus R1/(R1+R2) times Vsat rejects noise.

Slew-Rate-Limited Output

\[ 2\pi f V_p \le SR \quad\Rightarrow\quad f_{\max}(V_p) = \frac{SR}{2\pi V_p} \] For \(v_o = V_p\sin(2\pi f t)\), the maximum slope is \(2\pi f V_p\). Below \(f_{\max}\) the output follows linearly; above it, the waveform slew-distorts.

Active Filters

Filter Type	Transfer Function	Cutoff / Property
First-order LPF (inverting)	\(H(s) = -\dfrac{R_f/R_1}{1 + sR_fC}\)	\(f_c = \dfrac{1}{2\pi R_f C}\)
First-order HPF	\(H(s) = -\dfrac{sR_fC}{1 + sR_1C}\)	\(f_c = \dfrac{1}{2\pi R_1 C}\)
Sallen-Key LPF (2nd order)	\(H(s) = \dfrac{K\omega_o^2}{s^2 + (\omega_o/Q)s + \omega_o^2}\)	\(\omega_o = \dfrac{1}{\sqrt{R_1R_2C_1C_2}}\)
Butterworth	Maximally flat passband	\(Q = 1/\sqrt{2} = 0.707\)
Chebyshev	Equiripple passband	Sharper roll-off
Bessel	Linear phase	Best for pulse signals

Band-Pass Filter

\[ f_0 = \sqrt{f_L \cdot f_H}, \quad BW = f_H - f_L, \quad Q = \frac{f_0}{BW} \] \(Q > 10\) gives a narrow-band response; \(Q < 10\) is wideband. Filter order equals the number of independent reactive elements and sets a roll-off of \(20n\) dB/decade.

Module 10

Power Amplifiers and Building Blocks

Power Amplifier Classes

Class	Conduction	Max \(\eta\)	Distortion	Application
A	\(360^\circ\)	25% (RC), 50% (xfmr)	Low	Audio (Hi-Fi)
B	\(180^\circ\)	78.5% (\(\pi/4\))	Crossover	Push-pull audio
AB	\(180^\circ\)–\(360^\circ\)	~60–70%	Minimal	Most audio power stages
C	\(<180^\circ\)	85–90%	Very high	RF (tuned load)
D	Switching (PWM)	>90%	Depends on PWM/filter	Modern audio, SMPS

Class A (Transformer Coupled)

\[ \eta_{\max} = \frac{V_{CC}^2/(2R_L')}{V_{CC}^2/R_L'} = 50\% \] No-signal transistor dissipation \(P_D = V_{CC}I_{CQ}\).

Class B Push-Pull

\[ \eta_{\max} = \frac{\pi}{4} \approx 78.5\% \] \[ P_{out,\max} = \frac{V_{CC}^2}{2R_L}, \quad P_{D,\max} = \frac{2V_{CC}^2}{\pi^2 R_L} \] Crossover distortion appears near \(V_{BE}\approx 0\).

Differential Amplifier and Current Mirror

Emitter-coupled differential pair: two matched transistors with equal collector resistors RC, bases driven by v1 and v2, emitters joined to a tail current source IQ returning to the negative supply. — Figure 20a. BJT differential pair — amplifies the difference between its two inputs while rejecting common-mode signals.

Basic BJT current mirror: a diode-connected reference transistor sets Iref through resistor R, and a matched output transistor copies that current as Iout. — Figure 20b. Basic current mirror — replicates a reference current for biasing other stages.

Differential Pair Results

\[ A_d = -g_m R_C, \quad A_{CM} \approx -\frac{R_C}{2R_{EE}} \] \[ \text{CMRR} = 20\log\!\frac{A_d}{A_{CM}} = 20\log(g_m R_{EE}) \]

Current Mirror

\[ I_{ref} = \frac{V_{CC} - V_{BE}}{R}, \quad I_{out} \approx I_{ref}\!\left(1 - \tfrac{2}{\beta}\right) \] For matched transistors with large \(\beta\), \(I_{out}\approx I_{ref}\).

Differential Pair with Active Load

Single-Ended Output Gain

\[ A_d = g_{m1}(r_{o2}\,\|\,r_{o4}) \] Far larger than the resistive-load value \(g_m R_C\) because \(r_o \gg R_C\).

Common-Mode & CMRR

\[ \text{CMRR}\approx 2g_{m1}g_{m3}R_{\text{tail}}(r_{o2}\,\|\,r_{o4}) \] A high tail resistance (cascode tail) gives very high CMRR. This stage sets the GBW: \(\text{GBW}=g_{m1}/(2\pi C_c)\).

Advanced Current Mirrors

Widlar Current Source

An emitter resistor \(R_E\) on the output transistor scales the current down: \(V_T \ln(I_{ref}/I_{out}) = I_{out}R_E\). It generates microamp bias currents without huge resistors.

Cascode Mirror

Stacking a second mirror multiplies the output resistance: \(R_{out} \approx g_{m2}r_{o2}r_{o1}\). The penalty is an extra \(V_{BE}\) of headroom.

Wilson Mirror

A three-transistor topology with feedback: \(I_{out} \approx I_{ref}(1 - 2/\beta^2)\), giving strong \(\beta\)-error compensation and \(R_{out}\approx \beta r_o/2\).

Mirror	\(R_{out}\)	Headroom
Basic	\(r_o\)	1 \(V_{BE}\)
Widlar	\(\sim r_o(1+g_m R_E)\)	1 \(V_{BE}\)
Wilson	\(\beta r_o/2\)	2 \(V_{BE}\)
Cascode	\(g_m r_o^2\)	2 \(V_{BE}\)

555 Timer and Voltage Regulators

555 Astable Mode

\[ \begin{aligned} t_H &= 0.693(R_A + R_B)C, \quad t_L = 0.693R_B C \\ T &= 0.693(R_A + 2R_B)C, \quad f = \frac{1.44}{(R_A + 2R_B)C} \\ \text{Duty} &= \frac{R_A + R_B}{R_A + 2R_B}\ (>50\%) \end{aligned} \] Add a diode across \(R_B\) to allow a duty cycle below 50%. Monostable mode: \(T = 1.1RC\).

Linear Voltage Regulators

Series pass: transistor in series with the load; feedback adjusts \(V_o\) (78xx, LM317).
Shunt: transistor in parallel with the load (less efficient).
LDO: low-dropout regulator with a PMOS pass element.

LM317 Adjustable Regulator

\[ V_o = 1.25\!\left(1 + \frac{R_2}{R_1}\right) + I_{adj}R_2 \] With \(I_{adj}\approx 100\) µA (usually negligible). Linear-regulator efficiency \(\eta = V_o/V_{in}\).

Bandgap Reference and CMOS Transmission Gate

Bandgap Reference

Sum two voltages with opposite temperature coefficients for a near-zero-TC reference: \(V_{BE}\) is CTAT (TC \(\approx -2\) mV/°C) and \(\Delta V_{BE} = V_T\ln(N)\) is PTAT. The result \(V_{ref} = V_{BE} + K V_T\ln(N) \approx 1.25\) V — the silicon bandgap extrapolated to 0 K. It anchors regulators (LM317, TL431) and ADC references.

CMOS Transmission Gate

An NMOS passes a clean logic 0 but loses \(V_{Tn}\) near the high rail; a PMOS does the opposite. Together they give a rail-to-rail pass with near-constant on-resistance. \(C=1\): both ON (closed switch); \(C=0\): both OFF (open switch). Used in sample-and-hold, multiplexers and ADC sampling.

Module 11

Advanced Topics and GATE Extras

Capacitor Filter and Voltage Multipliers

Capacitor-input filter: a rectifier diode charges a reservoir capacitor C placed in parallel with the output, smoothing the pulsating DC waveform. — Figure 22. Capacitor (reservoir) filter — reduces ripple after rectification.

Ripple with Capacitor Filter

\[ V_{r(pp)} \approx \frac{I_{dc}}{fC}, \quad V_{r(rms)} = \frac{I_{dc}}{2\sqrt{3}\,fC} \] Ripple factor \(\gamma = \dfrac{1}{2\sqrt{3}\,fCR_L}\). For a full-wave rectifier \(f\to 2f\), halving the ripple.

Voltage Multipliers

A half-wave doubler uses two diodes and two capacitors: \(C_1\) charges to \(V_m\), then \(C_2\) charges to \(2V_m\) via \(C_1\) and \(D_2\), giving \(V_{out} = 2V_m\) with PIV \(= 2V_m\). General \(N\)-stage output: \(V_o = N V_m\) (tripler, quadrupler, and so on).

Voltage multipliers produce high DC from a low AC input and appear in CRT/X-ray supplies and Cockcroft–Walton accelerators.

Reverse Recovery and Second-Order BJT Effects

Reverse Recovery

\[ t_{rr} = t_s + t_t \] \(t_s\) is the storage time (minority carriers) and \(t_t\) the transition time. Schottky diodes have \(t_{rr}\approx 0\). Reverse recovery limits the maximum switching frequency.

Early Effect

\[ I_C = I_S e^{V_{BE}/V_T}\!\left(1 + \frac{V_{CE}}{V_A}\right), \quad r_o = \frac{V_A}{I_C} \] Base-width modulation; \(V_A\) is typically 50–150 V.

Thermal Runaway

A positive-feedback loop \(T\uparrow \to I_C\uparrow \to P_D\uparrow \to T\uparrow\). Stability requires \(\partial P_C/\partial T_J < 1/\theta_{JA}\). Mitigations include emitter degeneration \(R_E\) and heat sinks; germanium is worse than silicon because of higher \(I_{CBO}\).

BJT h-Parameter Model

Two-Port Defining Equations

\[ v_1 = h_i i_1 + h_r v_2, \quad i_2 = h_f i_1 + h_o v_2 \] \(h_i\): input impedance; \(h_r\): reverse voltage gain; \(h_f\): forward current gain; \(h_o\): output admittance.

CE h-Parameters & Gains

\[ h_{ie}\approx r_\pi, \ h_{fe}=\beta, \ h_{re}\approx10^{-4}, \ h_{oe}=1/r_o \] \[ A_i \approx -h_{fe}, \quad A_v \approx -\frac{h_{fe}R_L}{h_{ie}} \] \(h_{re}\) and \(h_{oe}\) are usually neglected; this reduces to \(A_v = -g_m R_L\) in hybrid-\(\pi\) form.

Darlington Pair and Multistage Coupling

Darlington pair: the emitter of input transistor Q1 drives the base of output transistor Q2, with their collectors tied together so the combination behaves as one very-high-gain transistor. — Figure 23. Darlington pair — two transistors give an effective current gain of roughly beta1 times beta2.

Darlington Results

\[ \beta_{tot} = \beta_1\beta_2 + \beta_1 + \beta_2 \approx \beta_1\beta_2 \] \(V_{BE,tot}\approx 1.4\) V; \(R_{in}\approx \beta_1\beta_2 R_E\) (very high). Used in high-current switching, audio output stages and buffering.

Cascaded Amplifier Gain & BW

\[ A_{v,tot} = \prod_i A_{vi}, \quad A_{dB,tot} = \sum_i A_{dB,i} \] \[ BW_{tot} = BW_1\sqrt{2^{1/n}-1} \] Bandwidth shrinks as stages are added.

Coupling Type	Characteristics	Use
RC	Simple and cheap; DC blocked	Audio
Transformer	Impedance matching; bulky	RF, power
Direct	Passes DC; has drift	Op-amps, ICs
Tuned	Selective; narrow-band	RF stages

Class AB Biasing and Power-Amp Refinements

Class AB push-pull output stage: a bias chain of resistors and two diodes D1 and D2 holds an NPN and a PNP transistor slightly conducting, with the joined emitters delivering the output vo. — Figure 24. Diode-biased Class AB output stage — the diode bias removes the crossover distortion of Class B.

Class AB Key Points

Diodes bias both transistors slightly ON, eliminating crossover distortion.
Each transistor conducts more than \(180^\circ\) but less than \(360^\circ\).
A \(V_{BE}\)-multiplier gives adjustable bias; efficiency is roughly 60–70%.

Heat-Sink / Thermal Resistance

\[ T_J - T_A = P_D(\theta_{JC} + \theta_{CS} + \theta_{SA}) \] \[ P_{D,\max} = \frac{T_{J,\max} - T_A}{\theta_{JA}} \]

Precision Rectifier and Waveform Generators

Precision rectifier schematic: an op-amp with a diode in its feedback path, so the loop divides the diode forward drop by the open-loop gain. — Figure 25. Precision (super) diode — rectifies millivolt-level signals by hiding the diode drop inside the feedback loop.

Why "Precision"?

\[ V_\gamma^{\text{eff}} \approx \frac{V_\gamma}{A_{OL}} \approx 0 \] The op-amp inside the loop divides the diode drop by \(A_{OL}\), allowing rectification of millivolt-level signals. A second diode gives full-wave operation.

Square–Triangle Generator

\[ f = \frac{1}{4RC}\cdot\frac{R_2}{R_1} \] A Schmitt trigger produces the square wave and an integrator converts it to a triangle of amplitude \(V_{tri,p} = V_{sat}R_1/R_2\).

Converters & Sample-and-Hold

V-to-I (grounded load): \(I_L = V_i/R_s\), independent of \(R_L\). I-to-V (transimpedance): \(V_o = -I_i R_f\), used with photodiodes. A sample-and-hold uses a buffer, a MOSFET switch and a hold capacitor: \(V_o(t)=V_i(t_s)\) with droop rate \(\Delta V/\Delta t = I_{leak}/C_H\).

Two-Stage Op-Amp Architecture

Two-stage operational amplifier block diagram: a differential-pair input stage, a common-source gain stage bridged by a Miller capacitor Cc, and an output buffer providing low output resistance. — Figure 26. Two-stage Miller-compensated op-amp — the Miller capacitor splits the poles for stable operation.

Open-Loop DC Gain & Poles

\[ A_{OL} = (g_{m1}R_1)(g_{m2}R_2) \] \[ f_{p1} \approx \frac{1}{2\pi R_1 C_c(g_{m2}R_2)}, \quad f_{p2} \approx \frac{g_{m2}}{2\pi C_L} \] \[ \text{GBW} \approx \frac{g_{m1}}{2\pi C_c} \]

Pole Splitting

Stage 1 sets \(g_{m1}\) and the differential input; Stage 2 provides bulk gain; the buffer delivers low \(R_{out}\). The Miller capacitor \(C_c\) splits the poles, pushing \(f_{p1}\) down and \(f_{p2}\) up. The µA741 uses a 30 pF Miller capacitor giving a ~1 MHz GBW.

Stability, Phase Margin and Compensation

Combined Bode plot of an op-amp: the open-loop gain falls through 0 dB at the gain-crossover frequency while the phase approaches minus 180 degrees, the gap between them defining the phase margin. — Figure 27. Open-loop gain and phase versus frequency — the phase margin at the gain-crossover frequency sets stability.

Bode Stability Criterion

Gain crossover \(f_{GX}\): \(|A\beta| = 1\) (0 dB).
Phase crossover \(f_{PX}\): \(\angle A\beta = -180^\circ\).
Phase Margin: \(\text{PM} = 180^\circ + \angle A\beta|_{f_{GX}}\).
Gain Margin: \(\text{GM} = -20\log|A\beta|_{f_{PX}}\) dB.

Stability Thresholds

Stable if PM \(> 0^\circ\) and GM \(> 0\) dB. A good design has PM \(= 45^\circ\)–\(70^\circ\). Below \(45^\circ\) gives ringing and overshoot; \(0^\circ\) means oscillation.

Frequency Compensation

Dominant pole: add a large \(C_c\) to lower the first pole.
Pole-zero: add an \(R_c\)–\(C_c\) network to insert a compensating zero.
Miller (pole-splitting): place \(C_c\) across the high-gain stage to push \(f_{p1}\) down and \(f_{p2}\) up.

Noise in Amplifiers

Types of Electronic Noise

\[ \overline{v_n^2} = 4kTR\,\Delta f \quad \text{(thermal)} \] \[ \overline{i_n^2} = 2qI_{DC}\,\Delta f \quad \text{(shot)} \] \[ S(f) \propto 1/f \quad \text{(flicker)} \] Thermal (Johnson–Nyquist) noise is white and present in every resistor; shot noise arises from discrete carriers at junctions; flicker (1/f) noise dominates at low frequency, especially in MOSFETs.

Noise Figure & SNR

\[ \text{SNR} = 10\log\frac{P_{signal}}{P_{noise}}, \quad \text{NF} = 10\log\frac{\text{SNR}_{in}}{\text{SNR}_{out}} \] \[ F_{tot} = F_1 + \frac{F_2-1}{G_1} + \frac{F_3-1}{G_1 G_2} + \cdots \] Friis' formula shows the first stage dominates — use a low-noise amplifier (LNA) front-end.

Phase-Locked Loop (PLL)

Phase-locked loop block diagram: a phase detector compares input frequency fi with the fed-back VCO output fo, a low-pass filter converts the error to a DC control voltage vc, and the VCO adjusts until it locks. — Figure 28. Phase-locked loop — feedback forces the VCO to track the input frequency and phase.

Building Blocks

Phase detector: compares the phases of \(f_i\) and \(f_o\).
LPF: smooths the error into a DC control voltage.
VCO: output frequency \(f_o \propto v_c\).
Lock: \(f_o = f_i\) with a constant phase offset.

Key Parameters & Uses

Lock range (kept-locked span), capture range (acquire-lock span, a subset of lock range), free-running frequency, and loop gain \(K_v = K_{PD}K_{VCO}\). Applications include FM demodulation, clock recovery, frequency synthesis, tone decoding and motor control.

Comparators, Log/Antilog and Analog Multipliers

Comparator (Open-Loop)

\[ v_o = \begin{cases} +V_{sat} & v_+ > v_- \\ -V_{sat} & v_+ < v_- \end{cases} \] Issues: slow slew and threshold chatter. Fix with a Schmitt trigger (hysteresis) or a dedicated IC (LM311/339).

Log, Antilog & Multiplier

\[ v_o = -V_T\ln\!\left(\frac{v_i}{I_S R}\right), \quad v_o = -RI_S e^{v_i/V_T} \] \[ V_z = K V_x V_y \] Combining log, sum and antilog blocks gives a four-quadrant analog multiplier (AD633, Gilbert cell) for mixing, RMS-to-DC and AM.

Data Converters: ADC and DAC

DAC Topologies

Weighted resistor: simple but needs \(R, 2R, \ldots, 2^{N-1}R\).
R–2R ladder: only two resistor values; most popular.
Current-steering: fastest, GHz update rates.
\(\Sigma\)–\(\Delta\) DAC: oversampling plus noise shaping for Hi-Fi audio.

Resolution & R–2R Output

\[ V_{LSB} = \frac{V_{ref}}{2^N}, \quad V_o = -V_{ref}\!\sum_{k=0}^{N-1}\frac{b_k}{2^{N-k}} \]

ADC Type	Speed	Note
Flash	Fastest	\(2^N-1\) comparators
SAR	Medium	One comparator, \(N\) clocks
Pipeline	Fast	Multi-stage SAR
Dual-slope	Slow	Best noise rejection (DMM)
\(\Sigma\)–\(\Delta\)	Slow	24-bit audio

Quantisation Error & SNR

\[ e_{rms} = \frac{Q}{\sqrt{12}}, \quad Q = V_{LSB} \] \[ \text{SNR}_{ideal} = 6.02N + 1.76 \ \text{dB} \] Memorise: about 6 dB per bit. A 12-bit ADC gives ~74 dB SNR.

Switching Regulators (Buck and Boost)

Buck (step-down) converter schematic: a switch S, a freewheeling diode, a series inductor L and an output capacitor C feeding the load RL. — Figure 29a. Buck converter — output equals the duty cycle times the input, Vout = D times Vin.

Boost (step-up) converter schematic: a series inductor L, a switch S to ground, a diode to the output capacitor C and the load RL. — Figure 29b. Boost converter — output exceeds the input, Vout = Vin/(1 - D).

Buck Converter

\[ V_{out} = D \cdot V_{in} \quad (D < 1) \] \(D\) is the switch duty cycle, assuming continuous conduction mode; efficiency is typically above 90%.

Boost Converter

\[ V_{out} = \frac{V_{in}}{1 - D} \quad (D < 1) \] Always steps up. Buck-boost: \(V_o = -D V_{in}/(1-D)\).

CMOS Inverter and Special Devices

CMOS inverter schematic: a PMOS pull-up and an NMOS pull-down with their gates tied to the input Vin and their drains tied to the output Vout, drawing negligible static current. — Figure 30. CMOS inverter — complementary devices give a rail-to-rail output with near-zero static power.

CMOS Operation

\(V_{in}\) LOW: PMOS ON, NMOS OFF, so \(V_{out} = V_{DD}\).
\(V_{in}\) HIGH: NMOS ON, PMOS OFF, so \(V_{out} = 0\).
Near-zero static current; dynamic power \(P = C_L V_{DD}^2 f\).
Switching point \(V_{in}\approx V_{DD}/2\) when matched.

UJT and SCR

UJT: a three-terminal negative-resistance device with intrinsic standoff ratio \(\eta = \tfrac{R_{B1}}{R_{B1}+R_{B2}}\) and peak voltage \(V_P = \eta V_{BB} + V_D\); used in relaxation oscillators and SCR triggering. SCR: a four-layer PNPN device that latches ON when gate-triggered and turns OFF only when \(I_A < I_H\); used in AC power control and motor drives.

Reference

GATE Formula Quick Reference

Topic	Formula	Remarks
Thermal voltage	\(V_T = kT/q = 26\) mV @ 300 K	Constant — memorise
Diode current	\(I_D = I_S(e^{V_D/\eta V_T}-1)\)	\(\eta = 1\) (Ge), 1–2 (Si)
HWR	\(V_{dc} = V_m/\pi\), \(\eta = 40.6\%\)	\(\gamma = 1.21\)
FWR	\(V_{dc} = 2V_m/\pi\), \(\eta = 81.2\%\)	\(\gamma = 0.482\)
BJT currents	\(I_E = I_B + I_C\), \(\alpha = \beta/(1+\beta)\)	Fundamental
BJT \(g_m\)	\(g_m = I_C/V_T\)	Transconductance
BJT \(r_\pi\)	\(r_\pi = \beta/g_m = \beta V_T/I_C\)	Input resistance
CE gain	\(A_v = -g_m(R_C\\|r_o)\)	Inverts signal
MOSFET sat. \(I_D\)	\(I_D = \tfrac{1}{2}\mu_n C_{ox}\tfrac{W}{L}V_{ov}^2\)	\(V_{ov} = V_{GS}-V_{Tn}\)
MOSFET \(g_m\)	\(g_m = \sqrt{2\mu_n C_{ox}(W/L)I_D} = 2I_D/V_{ov}\)	Three forms
Miller cap.	\(C_M = C(1 + \|A_v\|)\)	At input
Feedback	\(A_f = A/(1+A\beta)\)	Loop gain \(A\beta\)
Barkhausen	\(\|A\beta\| = 1\), \(\angle A\beta = 0^\circ\)	Oscillation condition
Wien bridge	\(f = 1/(2\pi RC)\), \(\|A\| \ge 3\)	RC oscillator
Colpitts	\(f = 1/(2\pi\sqrt{LC_{eq}})\), \(C_{eq} = C_1C_2/(C_1+C_2)\)	Two capacitors
Inverting op-amp	\(A_v = -R_f/R_1\)	Virtual ground
Non-inverting op-amp	\(A_v = 1 + R_f/R_1\)	\(\ge 1\)
Slew rate	\(f_{\max} = SR/(2\pi V_p)\)	Full-power BW
Class B	\(\eta_{\max} = \pi/4 = 78.5\%\)	Push-pull
555 astable	\(f = 1.44/((R_A+2R_B)C)\)	Duty \(> 50\%\)

Common Pitfalls and Winning Strategies

Pitfalls to Avoid

Confusing the \(\alpha\) and \(\beta\) formulas.
Forgetting the Early effect in high-accuracy analysis.
Ignoring the Miller effect at high frequencies.
Wrong sign in the inverting op-amp gain.
Mixing up HWR/FWR ripple factors.
Using \(V_T = 26\) mV without checking the temperature.
Overlooking the body effect in MOSFETs.
Neglecting crossover distortion in Class B.

Winning Strategies

Always draw the small-signal model.
Use the virtual-ground concept for op-amp problems.
Apply KCL at nodes and KVL around loops.
Simplify with Thévenin/Norton at bias level.
Verify units at every step.
Estimate the order of magnitude before solving.
For feedback, identify the topology, then \(A\) and \(\beta\).

High-yield GATE topics: op-amp circuits (3–4 questions), BJT/MOSFET biasing and small-signal gain (2–3), diode clippers/clampers/rectifiers (1–2), feedback and oscillators (1–2), and frequency response including GBW and the Miller effect (about 1 question).

Practice

Worked GATE-Style Examples

Example 1 — BJT Voltage-Divider Bias

Problem

Given \(V_{CC}=12\) V, \(R_1=47\) k\(\Omega\), \(R_2=10\) k\(\Omega\), \(R_C=3.3\) k\(\Omega\), \(R_E=1\) k\(\Omega\), \(\beta=100\) and \(V_{BE}=0.7\) V, find (a) \(I_{CQ}\) and \(V_{CEQ}\); (b) \(g_m\) and \(r_\pi\); (c) \(A_v\) with \(C_E\) across \(R_E\).

Solution

Step 1 — Thévenin at the base. \(V_{Th} = \tfrac{R_2}{R_1+R_2}V_{CC} = \tfrac{10}{57}(12) \approx 2.10\) V; \(R_{Th} = R_1\|R_2 \approx 8.25\) k\(\Omega\).

Step 2 — DC Q-point. \(I_B = \dfrac{V_{Th}-V_{BE}}{R_{Th}+(1+\beta)R_E} = \dfrac{1.40}{109.25\,\text{k}}\approx 12.8\ \mu\text{A}\); hence \(I_{CQ} = \beta I_B \approx 1.28\) mA and \(V_{CEQ} = V_{CC} - I_{CQ}(R_C+R_E) \approx 6.5\) V.

Step 3 — Small-signal parameters. \(g_m = I_{CQ}/V_T \approx 49.2\) mA/V; \(r_\pi = \beta/g_m \approx 2.03\) k\(\Omega\); \(r_e = V_T/I_{EQ} \approx 20\ \Omega\).

Step 4 — Voltage gain. With \(C_E\) shorting \(R_E\): \(A_v = -g_m R_C \approx -162\) V/V. Without \(C_E\) (full degeneration): \(A_v\approx -R_C/R_E = -3.3\) V/V — a 49× difference in swing.

Lesson. The bypass capacitor \(C_E\) recovers the full \(g_m R_C\) gain that emitter degeneration would otherwise sacrifice — a direct trade-off between bias stability \(S\) and gain.

Example 2 — Op-Amp Inverting Summer

Problem

An ideal op-amp has \(V_1 = +1\) V applied through \(R_1 = 10\) k\(\Omega\) and \(V_2 = +2\) V through \(R_2 = 20\) k\(\Omega\), both feeding the inverting input. The feedback resistor is \(R_f = 40\) k\(\Omega\) and \(v_+\) is grounded. Find \(V_o\).

Solution

Apply the golden rules (virtual ground \(v_- = 0\), \(I_- = 0\)) and KCL at the inverting node:

\[ \frac{V_1}{R_1} + \frac{V_2}{R_2} + \frac{V_o}{R_f} = 0 \] \[ V_o = -R_f\!\left(\frac{V_1}{R_1}+\frac{V_2}{R_2}\right) = -40\text{k}\!\left(\frac{1}{10\text{k}}+\frac{2}{20\text{k}}\right) = -8\ \text{V} \]

Pattern. An inverting summer scales each input by its own \(-R_f/R_i\) and adds — the direct basis for binary-weighted DACs. Trap: verify \(|V_o|\le V_{sat}\) to avoid output saturation.

Example 3 — Feedback Amplifier Sensitivity

Problem

A voltage-series feedback amplifier has \(A=10^4\) and \(\beta=0.01\). The open-loop gain \(A\) drops by 20% due to ageing. Find (a) \(A_f\) before and after, and (b) the percentage change in \(A_f\).

Solution

Using \(A_f = \dfrac{A}{1+A\beta}\): before, \(A\beta = 100\) so \(A_f^{(1)} = \dfrac{10^4}{101}\approx 99.01\). After a 20% drop, \(A' = 8000\), \(A'\beta = 80\), so \(A_f^{(2)} = \dfrac{8000}{81}\approx 98.77\). The change is \(\dfrac{\Delta A_f}{A_f}=\dfrac{99.01-98.77}{99.01}\approx 0.24\%\). A 20% drop in \(A\) produces only a 0.24% drop in \(A_f\).

Sensitivity Formula

\[ \frac{dA_f/A_f}{dA/A} = \frac{1}{1+A\beta} \] Variations in \(A\) are reduced by the return difference \((1+A\beta)\approx 100\) — a 100× desensitisation, matching the 20% → 0.24% result. If \(A\beta\gg 1\), then \(A_f \approx 1/\beta\), set by passive components alone, with bandwidth multiplied by \((1+A\beta)\) and distortion divided by it.

Resources

Further Study and References

Classical Textbooks

Sedra & Smith, Microelectronic Circuits
Boylestad & Nashelsky, Electronic Devices and Circuit Theory
Millman & Halkias, Integrated Electronics
Razavi, Fundamentals of Microelectronics
Gray & Meyer, Analysis and Design of Analog ICs

For GATE Preparation

Previous-year GATE papers (solved)
NPTEL lectures on analog electronics
ACE / Made Easy practice books

Simulation Tools

LTspice (free, by Analog Devices)
NI Multisim
Cadence Virtuoso (industry IC design)
Proteus (beginner-friendly)

Suggested study sequence: semiconductor physics → diodes → BJT and FET DC and small-signal → op-amp golden rules → feedback topologies → frequency response → oscillators and power amplifiers. Spend extra time on Modules 3–5 and 9 for GATE.

Mastering analog electronics is ultimately about recognising recurring building blocks — the biased transistor, the small-signal model, the feedback loop and the op-amp golden rules — and applying them consistently. As the closing thought of this course puts it: the best way to learn analog electronics is to build it.