Power Semiconductor Devices for GATE Exam Comprehensive Revision

Introduction

Power Semiconductor Devices - Overview

  • Electronic switches used in power electronic circuits

  • Control and convert electrical power efficiently

  • Operate at high voltage and current levels

  • Key parameters: Voltage rating, Current rating, Switching speed, Power losses

Classification:

  • Uncontrolled: Power Diodes

  • Semi-controlled: Thyristors (SCR, TRIAC)

  • Fully controlled: MOSFET, IGBT, GTO, BJT

Important Ratings:

  • Peak Forward/Reverse Voltage, Average/RMS Current

  • \(dI/dt\) and \(dV/dt\) ratings, Safe Operating Area (SOA)

Power Diodes

Power Diodes - Detailed Analysis

Types:

  • PN Junction Diodes: General purpose, \(V_f \approx 0.7V\)

  • Schottky Diodes: Fast switching, \(V_f \approx 0.3V\), low \(t_{rr}\)

  • Fast Recovery Diodes: Optimized for \(t_{rr} < 500ns\)

Key Parameters:

  • Forward voltage drop: \(V_f\)

  • Reverse recovery time: \(t_{rr} = t_s + t_f\) (storage + fall time)

  • Reverse recovery charge: \(Q_{rr} = \frac{1}{2} \times I_{RRM} \times t_{rr}\)

  • Peak Inverse Voltage (PIV) rating

  • Surge current rating: \(I_{FSM}\)

Reverse Recovery Process:

  • Storage time: \(t_s\) (charge removal)

  • Fall time: \(t_f\) (current decay)

  • Softness factor: \(S = \frac{t_f}{t_s}\) (ideal: 0.5-1.0)

Diode Losses and Thermal Design

Power Losses:

  • Conduction Loss: \(P_{cond} = V_f \times I_{avg}\)

  • Switching Loss: \(P_{sw} = \frac{1}{2} \times V_R \times I_{RRM} \times t_{rr} \times f\)

  • Leakage Loss: \(P_{leak} = V_R \times I_R\) (reverse bias)

Series/Parallel Operation:

  • Series: Voltage sharing resistors needed

  • Parallel: Current sharing inductors recommended

Thermal Considerations:

  • Junction temperature: \(T_j = T_a + P_{loss} \times R_{th(j-a)}\)

  • Thermal time constant: \(\tau = R_{th} \times C_{th}\)

  • Derating factor typically 2-3 for safety

Thyristors

SCR - Extended Characteristics

Two-Transistor Model:

  • SCR = PNP + NPN transistors

  • Turn-on condition: \(\alpha_1 + \alpha_2 \geq 1\)

  • \(\alpha\) increases with current and temperature

Critical Parameters:

  • Latching current: \(I_L\) (minimum to maintain conduction)

  • Holding current: \(I_H\) (minimum to stay ON) - typically \(I_H < I_L\)

  • Critical rate of rise: \(dV/dt\) (max without false triggering)

  • Critical rate of current rise: \(dI/dt\) (max during turn-on)

  • Circuit fusing: \(I^2t\) rating

Turn-off Process:

  • Circuit turn-off time: \(t_q\) (time for \(I_A = 0\))

  • Reverse recovery charge removal

  • Gate recovery time: \(t_{gr}\)

SCR - Commutation Techniques

Natural Commutation:

  • AC supply naturally reverses current

  • Used in: Phase-controlled rectifiers, AC voltage controllers

Forced Commutation:

  • Self-commutation: LC resonant circuit

  • Impulse commutation: Capacitor discharge

  • Complementary commutation: Auxiliary SCR

  • Load commutation: Load current reversal

Commutation Circuit Design:

  • Commutation capacitor: \(C = \frac{I_L \times t_q}{V_C}\)

  • Commutation inductor: \(L = \frac{V_C \times t_q}{I_L}\)

  • Circuit turn-off time: \(t_c > t_q\) (safety margin)

Thyristor Family - Extended

TRIAC (Triode AC Switch):

  • Bidirectional SCR, MT1, MT2, Gate terminals

  • Four quadrant operation modes

  • Quadrant I: MT2(+), G(+); Quadrant III: MT2(-), G(-)

  • dV/dt and dI/dt ratings critical

GTO (Gate Turn-Off Thyristor):

  • Turn-off gain: \(\beta_{off} = \frac{I_A}{I_G}\) (typically 3-5)

  • Negative gate current for turn-off: \(I_G = -\frac{I_A}{\beta_{off}}\)

  • Tail current during turn-off

  • Snubber circuits essential

DIAC & Other Devices:

  • DIAC: Bidirectional breakover, \(V_{BO} \approx 30V\)

  • LASCR: Light-activated SCR

  • RCT: Reverse Conducting Thyristor

Power BJTs

Power BJTs - Characteristics

Structure & Operation:

  • Current-controlled device: \(I_C = \beta \times I_B\)

  • Darlington configuration for high current gain

  • Triple-diffused structure for high voltage rating

Key Parameters:

  • Current gain: \(\beta = \frac{I_C}{I_B}\) (decreases with current)

  • Saturation voltage: \(V_{CE(sat)}\) (typically 1-2V)

  • Base-emitter voltage: \(V_{BE}\) (0.7V for Si)

  • Safe Operating Area (SOA): Forward bias and Reverse bias

Switching Characteristics:

  • Turn-on time: \(t_{on} = t_d + t_r\) (delay + rise time)

  • Turn-off time: \(t_{off} = t_s + t_f\) (storage + fall time)

  • Storage time depends on base overdrive factor

BJT - Drive Circuits & Second Breakdown

Base Drive Requirements:

  • Base current: \(I_B = \frac{I_C}{\beta}\) (plus overdrive)

  • Turn-on: Positive base current pulse

  • Turn-off: Negative base current (speed-up capacitor)

  • Base drive power: \(P_B = V_{BE} \times I_B\)

Second Breakdown:

  • Thermal instability leading to device failure

  • Current concentration in hot spots

  • Forward bias SOA limited by second breakdown

  • Reverse bias SOA limited by avalanche breakdown

Protection & Snubbers:

  • RC snubber across collector-emitter

  • Base-emitter clamp diode

  • Current limiting in base drive

Power MOSFETs

Power MOSFETs - Enhanced Analysis

Structure Types:

  • Vertical MOSFET (VMOS): High voltage, low \(R_{DS(on)}\)

  • Double-diffused MOS (DMOS): Most common structure

  • Trench MOSFET: Lower \(R_{DS(on)}\), higher gate charge

Body Diode:

  • Inherent antiparallel diode (source to drain)

  • Forward voltage: \(V_{SD} \approx 0.7V\)

  • Reverse recovery time: \(t_{rr}\) (important in switching)

  • Used as freewheeling diode in some applications

Temperature Effects:

  • \(V_{th}\) has negative temperature coefficient

  • \(R_{DS(on)}\) increases with temperature (positive coefficient)

  • Thermal runaway not possible (unlike BJT)

MOSFET - Capacitances & Switching

Parasitic Capacitances:

  • Gate-source capacitance: \(C_{gs}\) (constant)

  • Gate-drain capacitance: \(C_{gd}\) (Miller capacitance, voltage-dependent)

  • Drain-source capacitance: \(C_{ds}\) (junction capacitance)

  • Input capacitance: \(C_{iss} = C_{gs} + C_{gd}\)

  • Output capacitance: \(C_{oss} = C_{ds} + C_{gd}\)

Switching Analysis:

  • Gate charge: \(Q_g = Q_{gs} + Q_{gd}\) (total charge to turn on)

  • Miller charge: \(Q_{gd}\) (causes plateau in \(V_{gs}\))

  • Switching energy: \(E_{sw} = \frac{1}{2} \times V_{DS} \times I_D \times t_{sw}\)

  • Gate drive current: \(I_g = \frac{Q_g}{t_{sw}}\)

Parallel Operation:

  • Positive temperature coefficient helps current sharing

  • Gate resistors for oscillation prevention

IGBTs

IGBT - Structure & Advanced Characteristics

Structure Types:

  • Punch-Through (PT): Lower \(V_{CE(sat)}\), faster switching

  • Non-Punch-Through (NPT): Higher ruggedness, slower switching

  • Trench Gate: Lower \(V_{CE(sat)}\), higher transconductance

Equivalent Circuit:

  • MOSFET driving a PNP transistor

  • Parasitic NPN transistor (latch-up concern)

  • Collector-emitter diode (antiparallel)

Latch-up Phenomenon:

  • Parasitic thyristor formation (PNPN)

  • Triggered by high \(dI/dt\) or overcurrent

  • Prevention: Optimized base resistance, \(dI/dt\) control

Current Tailing:

  • Stored charge in drift region

  • Causes turn-off losses

  • Dependent on collector current and temperature

IGBT - Gate Drive & Protection

Gate Drive Design:

  • Turn-on gate voltage: \(+15V\) (typical)

  • Turn-off gate voltage: \(-8V\) to \(-15V\) (noise immunity)

  • Gate resistor: \(R_g\) (controls \(dI/dt\), \(dV/dt\))

  • Miller clamp for reduced switching losses

Protection Schemes:

  • Desaturation Protection: \(V_{CE}\) monitoring for overcurrent

  • Short Circuit Protection: Current limiting, soft turn-off

  • Under-voltage Lockout (UVLO): Gate drive supply monitoring

  • Active Clamping: \(dV/dt\) control during turn-off

Soft Switching Techniques:

  • Zero Voltage Switching (ZVS)

  • Zero Current Switching (ZCS)

  • Resonant gate drive

Device Comparison

Power Device Comparison - Comprehensive

Parameter Diode SCR BJT MOSFET IGBT
Control Type None Gate ON Base ON/OFF Gate ON/OFF Gate ON/OFF
Input Impedance - Medium Low High High
Switching Speed Fast Slow Medium Very Fast Fast
Conduction Loss Low Low Low Medium Low
Switching Loss Medium High Medium Low Medium
Drive Power None Low High Low Low
Voltage Rating High High Medium Medium High
Current Rating High High High Medium High
Frequency (max) - 1kHz 10kHz 1MHz 100kHz

Selection Criteria & Applications

Application-wise Selection:

  • Rectifiers: Diodes (uncontrolled), SCR (controlled)

  • Inverters: IGBT (medium power), MOSFET (high frequency)

  • Choppers: MOSFET (high freq), IGBT (high power)

  • Motor Drives: IGBT (preferred), MOSFET (small motors)

Power vs Frequency Trade-off:

  • High Power + Low Frequency: SCR, GTO

  • Medium Power + Medium Frequency: IGBT, BJT

  • Low Power + High Frequency: MOSFET

Cost Considerations:

  • Device cost: Diode \(<\) SCR \(<\) MOSFET \(<\) BJT \(<\) IGBT

  • Drive circuit cost: SCR \(<\) MOSFET \(<\) IGBT \(<\) BJT

  • Total system cost depends on application

Snubber Circuits

Snubber Circuits - Design & Analysis

Purpose:

  • Limit \(dV/dt\) and \(dI/dt\) during switching

  • Reduce switching losses and EMI

  • Prevent device failure due to excessive stress

Types of Snubbers:

  • RC Snubber: Limits \(dV/dt\) - \(R = \sqrt{\frac{L}{C}}\), \(C = \frac{I \times dt}{dV}\)

  • RCD Snubber: Energy recovery type

  • LC Snubber: Limits \(dI/dt\) - \(L = \frac{V \times dt}{dI}\)

  • RLC Snubber: Combined protection

Design Equations:

  • Snubber capacitor: \(C = \frac{I_L \times t_{off}}{V_{DC}}\)

  • Snubber resistor: \(R = \frac{1}{2} \sqrt{\frac{L}{C}}\) (critical damping)

  • Energy dissipated: \(E = \frac{1}{2} \times C \times V^2\) per switching cycle

Thermal Management

Thermal Design & Heat Sinks

Thermal Equivalent Circuit:

  • Junction to case: \(R_{th(j-c)}\) (device parameter)

  • Case to heat sink: \(R_{th(c-h)}\) (interface material)

  • Heat sink to ambient: \(R_{th(h-a)}\) (heat sink design)

  • Total: \(R_{th(j-a)} = R_{th(j-c)} + R_{th(c-h)} + R_{th(h-a)}\)

Junction Temperature:

  • Steady state: \(T_j = T_a + P_{loss} \times R_{th(j-a)}\)

  • Transient: \(T_j(t) = T_a + P_{loss} \times R_{th} \times (1 - e^{-t/\tau})\)

  • Thermal time constant: \(\tau = R_{th} \times C_{th}\)

Heat Sink Design:

  • Required thermal resistance: \(R_{th(h-a)} = \frac{T_{j(max)} - T_a}{P_{loss}} - R_{th(j-c)} - R_{th(c-h)}\)

  • Forced air cooling: \(R_{th} \propto \frac{1}{\sqrt{velocity}}\)

  • Heat sink surface area: \(A = \frac{P_{loss}}{h \times \Delta T}\)

Important Formulas

Key Formulas for GATE - Part I

Power Losses:

  • Conduction Loss: \(P_{cond} = I_{avg}^2 \times R_{on} + V_{sat} \times I_{avg}\)

  • Switching Loss: \(P_{sw} = \frac{1}{2} \times V \times I \times (t_{on} + t_{off}) \times f\)

  • Total Loss: \(P_{total} = P_{cond} + P_{sw} + P_{gate}\)

MOSFET Specific:

  • Drain Current: \(I_D = K(V_{GS} - V_{th})^2\) (saturation region)

  • Transconductance: \(g_m = \frac{\partial I_D}{\partial V_{GS}} = 2K(V_{GS} - V_{th})\)

  • Gate charge: \(Q_g = C_{gs} \times V_{GS} + C_{gd} \times V_{DS}\)

SCR Specific:

  • Two-transistor model: \(\alpha_1 + \alpha_2 = 1\) (turn-on condition)

  • Gate trigger power: \(P_G = V_{GT} \times I_{GT}\)

  • Commutation: \(t_c = \pi \sqrt{LC}\) (for LC commutation)

Key Formulas for GATE - Part II

Thermal Design:

  • Junction Temperature: \(T_j = T_a + P_{loss} \times R_{th(j-a)}\)

  • Thermal resistance: \(R_{th} = \frac{\Delta T}{P_{loss}}\)

  • Transient thermal impedance: \(Z_{th}(t) = R_{th} \times (1 - e^{-t/\tau})\)

Snubber Design:

  • RC snubber: \(R = \sqrt{\frac{L}{C}}\), \(C = \frac{I \times dt}{dV}\)

  • Energy per cycle: \(E = \frac{1}{2} \times C \times V^2\)

  • Power dissipation: \(P_R = E \times f = \frac{1}{2} \times C \times V^2 \times f\)

Safe Operating Area:

  • Power limit: \(P_{max} = V_{DS} \times I_D \leq P_{rated}\)

  • Thermal limit: \(I_{max} = \frac{T_{j(max)} - T_a}{R_{th(j-a)} \times V_{DS}}\)

GATE Specific Topics

GATE Important Concepts

Frequently Asked Topics:

  • Device characteristics and V-I curves

  • Switching waveforms and timing diagrams

  • Commutation circuits for SCR

  • Snubber circuit design and analysis

  • Thermal management calculations

Problem-solving Approach:

  • Identify device type and operating conditions

  • Apply appropriate equivalent circuit

  • Use device ratings and parameters

  • Calculate losses and efficiency

  • Verify thermal and electrical stress limits

Common GATE Questions:

  • SCR firing angle and commutation analysis

  • MOSFET/IGBT switching loss calculations

  • Device selection for specific applications

  • Snubber component value determination

Summary

Summary - Power Semiconductor Devices

Key Points for GATE:

  • Understand device physics and equivalent circuits

  • Master switching characteristics and timing

  • Learn application-specific advantages/limitations

  • Practice numerical problems on losses and thermal design

Device Selection Strategy:

  • Match device ratings to application requirements

  • Consider switching frequency and power level

  • Evaluate drive circuit complexity and cost

  • Account for thermal management requirements

Essential Formulas to Remember:

  • Power loss calculations for all devices

  • Thermal resistance and junction temperature

  • Switching time relationships

  • Snubber design equations