Introduction
Power Semiconductor Devices - Overview
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Electronic switches used in power electronic circuits
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Control and convert electrical power efficiently
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Operate at high voltage and current levels
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Key parameters: Voltage rating, Current rating, Switching speed, Power losses
Classification:
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Uncontrolled: Power Diodes
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Semi-controlled: Thyristors (SCR, TRIAC)
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Fully controlled: MOSFET, IGBT, GTO, BJT
Important Ratings:
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Peak Forward/Reverse Voltage, Average/RMS Current
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\(dI/dt\) and \(dV/dt\) ratings, Safe Operating Area (SOA)
Power Diodes
Power Diodes - Detailed Analysis
Types:
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PN Junction Diodes: General purpose, \(V_f \approx 0.7V\)
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Schottky Diodes: Fast switching, \(V_f \approx 0.3V\), low \(t_{rr}\)
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Fast Recovery Diodes: Optimized for \(t_{rr} < 500ns\)
Key Parameters:
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Forward voltage drop: \(V_f\)
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Reverse recovery time: \(t_{rr} = t_s + t_f\) (storage + fall time)
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Reverse recovery charge: \(Q_{rr} = \frac{1}{2} \times I_{RRM} \times t_{rr}\)
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Peak Inverse Voltage (PIV) rating
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Surge current rating: \(I_{FSM}\)
Reverse Recovery Process:
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Storage time: \(t_s\) (charge removal)
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Fall time: \(t_f\) (current decay)
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Softness factor: \(S = \frac{t_f}{t_s}\) (ideal: 0.5-1.0)
Diode Losses and Thermal Design
Power Losses:
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Conduction Loss: \(P_{cond} = V_f \times I_{avg}\)
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Switching Loss: \(P_{sw} = \frac{1}{2} \times V_R \times I_{RRM} \times t_{rr} \times f\)
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Leakage Loss: \(P_{leak} = V_R \times I_R\) (reverse bias)
Series/Parallel Operation:
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Series: Voltage sharing resistors needed
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Parallel: Current sharing inductors recommended
Thermal Considerations:
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Junction temperature: \(T_j = T_a + P_{loss} \times R_{th(j-a)}\)
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Thermal time constant: \(\tau = R_{th} \times C_{th}\)
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Derating factor typically 2-3 for safety
Thyristors
SCR - Extended Characteristics
Two-Transistor Model:
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SCR = PNP + NPN transistors
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Turn-on condition: \(\alpha_1 + \alpha_2 \geq 1\)
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\(\alpha\) increases with current and temperature
Critical Parameters:
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Latching current: \(I_L\) (minimum to maintain conduction)
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Holding current: \(I_H\) (minimum to stay ON) - typically \(I_H < I_L\)
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Critical rate of rise: \(dV/dt\) (max without false triggering)
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Critical rate of current rise: \(dI/dt\) (max during turn-on)
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Circuit fusing: \(I^2t\) rating
Turn-off Process:
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Circuit turn-off time: \(t_q\) (time for \(I_A = 0\))
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Reverse recovery charge removal
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Gate recovery time: \(t_{gr}\)
SCR - Commutation Techniques
Natural Commutation:
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AC supply naturally reverses current
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Used in: Phase-controlled rectifiers, AC voltage controllers
Forced Commutation:
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Self-commutation: LC resonant circuit
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Impulse commutation: Capacitor discharge
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Complementary commutation: Auxiliary SCR
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Load commutation: Load current reversal
Commutation Circuit Design:
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Commutation capacitor: \(C = \frac{I_L \times t_q}{V_C}\)
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Commutation inductor: \(L = \frac{V_C \times t_q}{I_L}\)
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Circuit turn-off time: \(t_c > t_q\) (safety margin)
Thyristor Family - Extended
TRIAC (Triode AC Switch):
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Bidirectional SCR, MT1, MT2, Gate terminals
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Four quadrant operation modes
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Quadrant I: MT2(+), G(+); Quadrant III: MT2(-), G(-)
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dV/dt and dI/dt ratings critical
GTO (Gate Turn-Off Thyristor):
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Turn-off gain: \(\beta_{off} = \frac{I_A}{I_G}\) (typically 3-5)
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Negative gate current for turn-off: \(I_G = -\frac{I_A}{\beta_{off}}\)
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Tail current during turn-off
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Snubber circuits essential
DIAC & Other Devices:
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DIAC: Bidirectional breakover, \(V_{BO} \approx 30V\)
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LASCR: Light-activated SCR
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RCT: Reverse Conducting Thyristor
Power BJTs
Power BJTs - Characteristics
Structure & Operation:
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Current-controlled device: \(I_C = \beta \times I_B\)
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Darlington configuration for high current gain
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Triple-diffused structure for high voltage rating
Key Parameters:
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Current gain: \(\beta = \frac{I_C}{I_B}\) (decreases with current)
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Saturation voltage: \(V_{CE(sat)}\) (typically 1-2V)
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Base-emitter voltage: \(V_{BE}\) (0.7V for Si)
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Safe Operating Area (SOA): Forward bias and Reverse bias
Switching Characteristics:
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Turn-on time: \(t_{on} = t_d + t_r\) (delay + rise time)
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Turn-off time: \(t_{off} = t_s + t_f\) (storage + fall time)
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Storage time depends on base overdrive factor
BJT - Drive Circuits & Second Breakdown
Base Drive Requirements:
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Base current: \(I_B = \frac{I_C}{\beta}\) (plus overdrive)
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Turn-on: Positive base current pulse
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Turn-off: Negative base current (speed-up capacitor)
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Base drive power: \(P_B = V_{BE} \times I_B\)
Second Breakdown:
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Thermal instability leading to device failure
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Current concentration in hot spots
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Forward bias SOA limited by second breakdown
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Reverse bias SOA limited by avalanche breakdown
Protection & Snubbers:
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RC snubber across collector-emitter
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Base-emitter clamp diode
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Current limiting in base drive
Power MOSFETs
Power MOSFETs - Enhanced Analysis
Structure Types:
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Vertical MOSFET (VMOS): High voltage, low \(R_{DS(on)}\)
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Double-diffused MOS (DMOS): Most common structure
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Trench MOSFET: Lower \(R_{DS(on)}\), higher gate charge
Body Diode:
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Inherent antiparallel diode (source to drain)
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Forward voltage: \(V_{SD} \approx 0.7V\)
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Reverse recovery time: \(t_{rr}\) (important in switching)
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Used as freewheeling diode in some applications
Temperature Effects:
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\(V_{th}\) has negative temperature coefficient
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\(R_{DS(on)}\) increases with temperature (positive coefficient)
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Thermal runaway not possible (unlike BJT)
MOSFET - Capacitances & Switching
Parasitic Capacitances:
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Gate-source capacitance: \(C_{gs}\) (constant)
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Gate-drain capacitance: \(C_{gd}\) (Miller capacitance, voltage-dependent)
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Drain-source capacitance: \(C_{ds}\) (junction capacitance)
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Input capacitance: \(C_{iss} = C_{gs} + C_{gd}\)
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Output capacitance: \(C_{oss} = C_{ds} + C_{gd}\)
Switching Analysis:
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Gate charge: \(Q_g = Q_{gs} + Q_{gd}\) (total charge to turn on)
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Miller charge: \(Q_{gd}\) (causes plateau in \(V_{gs}\))
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Switching energy: \(E_{sw} = \frac{1}{2} \times V_{DS} \times I_D \times t_{sw}\)
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Gate drive current: \(I_g = \frac{Q_g}{t_{sw}}\)
Parallel Operation:
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Positive temperature coefficient helps current sharing
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Gate resistors for oscillation prevention
IGBTs
IGBT - Structure & Advanced Characteristics
Structure Types:
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Punch-Through (PT): Lower \(V_{CE(sat)}\), faster switching
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Non-Punch-Through (NPT): Higher ruggedness, slower switching
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Trench Gate: Lower \(V_{CE(sat)}\), higher transconductance
Equivalent Circuit:
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MOSFET driving a PNP transistor
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Parasitic NPN transistor (latch-up concern)
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Collector-emitter diode (antiparallel)
Latch-up Phenomenon:
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Parasitic thyristor formation (PNPN)
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Triggered by high \(dI/dt\) or overcurrent
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Prevention: Optimized base resistance, \(dI/dt\) control
Current Tailing:
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Stored charge in drift region
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Causes turn-off losses
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Dependent on collector current and temperature
IGBT - Gate Drive & Protection
Gate Drive Design:
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Turn-on gate voltage: \(+15V\) (typical)
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Turn-off gate voltage: \(-8V\) to \(-15V\) (noise immunity)
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Gate resistor: \(R_g\) (controls \(dI/dt\), \(dV/dt\))
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Miller clamp for reduced switching losses
Protection Schemes:
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Desaturation Protection: \(V_{CE}\) monitoring for overcurrent
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Short Circuit Protection: Current limiting, soft turn-off
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Under-voltage Lockout (UVLO): Gate drive supply monitoring
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Active Clamping: \(dV/dt\) control during turn-off
Soft Switching Techniques:
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Zero Voltage Switching (ZVS)
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Zero Current Switching (ZCS)
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Resonant gate drive
Device Comparison
Power Device Comparison - Comprehensive
Parameter | Diode | SCR | BJT | MOSFET | IGBT |
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Control Type | None | Gate ON | Base ON/OFF | Gate ON/OFF | Gate ON/OFF |
Input Impedance | - | Medium | Low | High | High |
Switching Speed | Fast | Slow | Medium | Very Fast | Fast |
Conduction Loss | Low | Low | Low | Medium | Low |
Switching Loss | Medium | High | Medium | Low | Medium |
Drive Power | None | Low | High | Low | Low |
Voltage Rating | High | High | Medium | Medium | High |
Current Rating | High | High | High | Medium | High |
Frequency (max) | - | 1kHz | 10kHz | 1MHz | 100kHz |
Selection Criteria & Applications
Application-wise Selection:
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Rectifiers: Diodes (uncontrolled), SCR (controlled)
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Inverters: IGBT (medium power), MOSFET (high frequency)
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Choppers: MOSFET (high freq), IGBT (high power)
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Motor Drives: IGBT (preferred), MOSFET (small motors)
Power vs Frequency Trade-off:
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High Power + Low Frequency: SCR, GTO
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Medium Power + Medium Frequency: IGBT, BJT
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Low Power + High Frequency: MOSFET
Cost Considerations:
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Device cost: Diode \(<\) SCR \(<\) MOSFET \(<\) BJT \(<\) IGBT
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Drive circuit cost: SCR \(<\) MOSFET \(<\) IGBT \(<\) BJT
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Total system cost depends on application
Snubber Circuits
Snubber Circuits - Design & Analysis
Purpose:
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Limit \(dV/dt\) and \(dI/dt\) during switching
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Reduce switching losses and EMI
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Prevent device failure due to excessive stress
Types of Snubbers:
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RC Snubber: Limits \(dV/dt\) - \(R = \sqrt{\frac{L}{C}}\), \(C = \frac{I \times dt}{dV}\)
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RCD Snubber: Energy recovery type
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LC Snubber: Limits \(dI/dt\) - \(L = \frac{V \times dt}{dI}\)
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RLC Snubber: Combined protection
Design Equations:
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Snubber capacitor: \(C = \frac{I_L \times t_{off}}{V_{DC}}\)
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Snubber resistor: \(R = \frac{1}{2} \sqrt{\frac{L}{C}}\) (critical damping)
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Energy dissipated: \(E = \frac{1}{2} \times C \times V^2\) per switching cycle
Thermal Management
Thermal Design & Heat Sinks
Thermal Equivalent Circuit:
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Junction to case: \(R_{th(j-c)}\) (device parameter)
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Case to heat sink: \(R_{th(c-h)}\) (interface material)
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Heat sink to ambient: \(R_{th(h-a)}\) (heat sink design)
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Total: \(R_{th(j-a)} = R_{th(j-c)} + R_{th(c-h)} + R_{th(h-a)}\)
Junction Temperature:
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Steady state: \(T_j = T_a + P_{loss} \times R_{th(j-a)}\)
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Transient: \(T_j(t) = T_a + P_{loss} \times R_{th} \times (1 - e^{-t/\tau})\)
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Thermal time constant: \(\tau = R_{th} \times C_{th}\)
Heat Sink Design:
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Required thermal resistance: \(R_{th(h-a)} = \frac{T_{j(max)} - T_a}{P_{loss}} - R_{th(j-c)} - R_{th(c-h)}\)
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Forced air cooling: \(R_{th} \propto \frac{1}{\sqrt{velocity}}\)
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Heat sink surface area: \(A = \frac{P_{loss}}{h \times \Delta T}\)
Important Formulas
Key Formulas for GATE - Part I
Power Losses:
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Conduction Loss: \(P_{cond} = I_{avg}^2 \times R_{on} + V_{sat} \times I_{avg}\)
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Switching Loss: \(P_{sw} = \frac{1}{2} \times V \times I \times (t_{on} + t_{off}) \times f\)
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Total Loss: \(P_{total} = P_{cond} + P_{sw} + P_{gate}\)
MOSFET Specific:
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Drain Current: \(I_D = K(V_{GS} - V_{th})^2\) (saturation region)
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Transconductance: \(g_m = \frac{\partial I_D}{\partial V_{GS}} = 2K(V_{GS} - V_{th})\)
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Gate charge: \(Q_g = C_{gs} \times V_{GS} + C_{gd} \times V_{DS}\)
SCR Specific:
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Two-transistor model: \(\alpha_1 + \alpha_2 = 1\) (turn-on condition)
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Gate trigger power: \(P_G = V_{GT} \times I_{GT}\)
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Commutation: \(t_c = \pi \sqrt{LC}\) (for LC commutation)
Key Formulas for GATE - Part II
Thermal Design:
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Junction Temperature: \(T_j = T_a + P_{loss} \times R_{th(j-a)}\)
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Thermal resistance: \(R_{th} = \frac{\Delta T}{P_{loss}}\)
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Transient thermal impedance: \(Z_{th}(t) = R_{th} \times (1 - e^{-t/\tau})\)
Snubber Design:
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RC snubber: \(R = \sqrt{\frac{L}{C}}\), \(C = \frac{I \times dt}{dV}\)
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Energy per cycle: \(E = \frac{1}{2} \times C \times V^2\)
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Power dissipation: \(P_R = E \times f = \frac{1}{2} \times C \times V^2 \times f\)
Safe Operating Area:
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Power limit: \(P_{max} = V_{DS} \times I_D \leq P_{rated}\)
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Thermal limit: \(I_{max} = \frac{T_{j(max)} - T_a}{R_{th(j-a)} \times V_{DS}}\)
GATE Specific Topics
GATE Important Concepts
Frequently Asked Topics:
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Device characteristics and V-I curves
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Switching waveforms and timing diagrams
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Commutation circuits for SCR
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Snubber circuit design and analysis
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Thermal management calculations
Problem-solving Approach:
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Identify device type and operating conditions
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Apply appropriate equivalent circuit
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Use device ratings and parameters
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Calculate losses and efficiency
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Verify thermal and electrical stress limits
Common GATE Questions:
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SCR firing angle and commutation analysis
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MOSFET/IGBT switching loss calculations
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Device selection for specific applications
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Snubber component value determination
Summary
Summary - Power Semiconductor Devices
Key Points for GATE:
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Understand device physics and equivalent circuits
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Master switching characteristics and timing
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Learn application-specific advantages/limitations
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Practice numerical problems on losses and thermal design
Device Selection Strategy:
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Match device ratings to application requirements
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Consider switching frequency and power level
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Evaluate drive circuit complexity and cost
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Account for thermal management requirements
Essential Formulas to Remember:
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Power loss calculations for all devices
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Thermal resistance and junction temperature
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Switching time relationships
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Snubber design equations