Binary: Base 2 (0,1)

Octal: Base 8 (0-7)

Hexadecimal: Base 16 (0-9, A-F)

Conversion: Binary \(\leftrightarrow\) Decimal \(\leftrightarrow\) Octal \(\leftrightarrow\) Hex

Signed representations: Sign-magnitude, 1’s complement, 2’s complement

2’s complement: Most common for negative numbers

Range: For n-bit 2’s complement: \(-2^{n-1}\) to \(2^{n-1}-1\)

BCD (Binary Coded Decimal): Each decimal digit → 4 bits

Gray Code: Adjacent codes differ by 1 bit only

Excess-3 Code: BCD + 3, self-complementing

ASCII: 7-bit character encoding

Error Detection: Parity bits (even/odd)

Hamming Code: Error detection and correction

Hamming Distance: Minimum distance for error detection = d+1, correction = 2d+1

IEEE 754 Standard: Single (32-bit) and Double (64-bit) precision

Single Precision: 1 sign + 8 exponent + 23 mantissa bits

Double Precision: 1 sign + 11 exponent + 52 mantissa bits

Normalized Form: \((-1)^S \times 1.M \times 2^{E-127}\) (single precision)

Bias: 127 for single, 1023 for double precision

Special Cases: Zero, Infinity, NaN (Not a Number)

Basic Operations: AND (\(\cdot\)), OR (\(+\)), NOT (\(\overline{A}\))

Commutative: \(A + B = B + A\), \(A \cdot B = B \cdot A\)

Associative: \((A + B) + C = A + (B + C)\)

Distributive: \(A(B + C) = AB + AC\), \(A + BC = (A+B)(A+C)\)

Identity: \(A + 0 = A\), \(A \cdot 1 = A\)

Complement: \(A + \overline{A} = 1\), \(A \cdot \overline{A} = 0\)

Idempotent: \(A + A = A\), \(A \cdot A = A\)

De Morgan’s Laws:

• \(\overline{A + B} = \overline{A} \cdot \overline{B}\)

• \(\overline{A \cdot B} = \overline{A} + \overline{B}\)

Absorption Laws:

• \(A + AB = A\)

• \(A(A + B) = A\)

Consensus Theorem: \(AB + \overline{A}C + BC = AB + \overline{A}C\)

Duality: Replace AND with OR, OR with AND, 0 with 1, 1 with 0

AND Gate: Output = 1 only when all inputs = 1

OR Gate: Output = 1 when any input = 1

NOT Gate: Output = complement of input

NAND Gate: NOT-AND, Universal gate

NOR Gate: NOT-OR, Universal gate

XOR Gate: Exclusive OR, output = 1 when inputs differ

XNOR Gate: Exclusive NOR, output = 1 when inputs same

NAND as Universal Gate:

• NOT: \(\overline{A} = A \uparrow A\)

• AND: \(A \cdot B = \overline{(A \uparrow A) \uparrow (B \uparrow B)}\)

• OR: \(A + B = (A \uparrow A) \uparrow (B \uparrow B)\)

NOR as Universal Gate:

• NOT: \(\overline{A} = A \downarrow A\)

• OR: \(A + B = \overline{(A \downarrow A) \downarrow (B \downarrow B)}\)

• AND: \(A \cdot B = (A \downarrow A) \downarrow (B \downarrow B)\)

Purpose: Simplify Boolean expressions graphically

Gray Code Ordering: Adjacent cells differ by 1 bit

Grouping Rules:

• Group 1s for SOP (Sum of Products)

• Group 0s for POS (Product of Sums)

• Groups must be powers of 2 (1, 2, 4, 8, 16)

• Larger groups give simpler expressions

Don’t Cares (X): Can be treated as 0 or 1 for optimization

Prime Implicants: Largest possible groups

Essential Prime Implicants: Must be included in final expression

Half Adder: Adds two 1-bit numbers

• Sum = \(A \oplus B\)

• Carry = \(A \cdot B\)

Full Adder: Adds three 1-bit numbers (A, B, Cin)

• Sum = \(A \oplus B \oplus C_{in}\)

• Carry = \(AB + C_{in}(A \oplus B)\)

Ripple Carry Adder: Cascade of full adders

Carry Look-ahead Adder: Faster addition using generate/propagate

Half Subtractor: Subtracts two 1-bit numbers

• Difference = \(A \oplus B\)

• Borrow = \(\overline{A} \cdot B\)

Full Subtractor: Subtracts with borrow input

• Difference = \(A \oplus B \oplus B_{in}\)

• Borrow = \(\overline{A}B + B_{in}(\overline{A \oplus B})\)

2’s Complement Subtraction: \(A - B = A + \overline{B} + 1\)

Function: Select one of many inputs based on select lines

2:1 MUX: 2 inputs, 1 select line

• \(Y = \overline{S} \cdot I_0 + S \cdot I_1\)

4:1 MUX: 4 inputs, 2 select lines

8:1 MUX: 8 inputs, 3 select lines

Function Implementation: Can implement any Boolean function

Expansion: Smaller MUX can build larger MUX

DEMUX Function: Route single input to one of many outputs

1:2 DEMUX: 1 input, 2 outputs, 1 select line

Decoder: \(n\) inputs → \(2^n\) outputs

• 2:4 decoder, 3:8 decoder

• Only one output active at a time

Encoder: \(2^n\) inputs → \(n\) outputs

• 4:2 encoder, 8:3 encoder

• Priority encoder handles multiple inputs

1-bit Comparator: Compare two 1-bit numbers

• \(A > B\): \(A \cdot \overline{B}\)

• \(A = B\): \(A \odot B\) (XNOR)

• \(A < B\): \(\overline{A} \cdot B\)

Multi-bit Comparator: Cascade 1-bit comparators

Magnitude Comparator: Compare magnitudes of binary numbers

SR Latch: Set-Reset using NOR gates

• S=1, R=0: Set (Q=1)

• S=0, R=1: Reset (Q=0)

• S=R=1: Invalid state

• S=R=0: No change

Gated SR Latch: SR latch with enable

D Latch: Data latch, eliminates invalid state

• \(D = S\), \(\overline{D} = R\)

Level-triggered: Output follows input when enabled

Edge-triggered: Change state on clock edge

D Flip-Flop: Data flip-flop

• \(Q^+ = D\)

JK Flip-Flop: J=Set, K=Reset

• \(Q^+ = J\overline{Q} + \overline{K}Q\)

• J=K=1: Toggle

• No invalid state (advantage over SR)

T Flip-Flop: Toggle flip-flop

• \(Q^+ = T \oplus Q\)

Race-around condition: In JK flip-flops with pulse triggering

D Flip-Flop: \(Q \to Q^+\) requires \(D = Q^+\)

JK Flip-Flop:

• \(0 \to 0\): J=0, K=X

• \(0 \to 1\): J=1, K=X

• \(1 \to 0\): J=X, K=1

• \(1 \to 1\): J=X, K=0

T Flip-Flop:

• \(0 \to 0\): T=0

• \(0 \to 1\): T=1

• \(1 \to 0\): T=1

• \(1 \to 1\): T=0

Moore Machine: Output depends only on current state

Mealy Machine: Output depends on current state and input

State Diagram: Graphical representation with states and transitions

State Table: Tabular representation of next state and output

State Assignment: Assign binary codes to states

State Reduction: Minimize number of states by merging equivalent states

Equivalence: Two states are equivalent if they produce same output sequence

Asynchronous (Ripple) Counter: Clock cascaded through FFs

• Slower due to propagation delay

• Simple design

Synchronous Counter: Common clock to all FFs

• Faster operation

• More complex design

Up Counter: Count 0, 1, 2, 3, ...

Down Counter: Count ..., 3, 2, 1, 0

Ring Counter: Circular shift register

Johnson Counter: Twisted ring counter (2n states for n FFs)

Modulo-N Counter: Count from 0 to N-1

Serial In Serial Out (SISO): Data enters and exits serially

Serial In Parallel Out (SIPO): Data enters serially, exits in parallel

Parallel In Serial Out (PISO): Data enters in parallel, exits serially

Parallel In Parallel Out (PIPO): Data enters and exits in parallel

Bidirectional Shift Register: Left and right shift capability

Universal Shift Register: All operations possible

Applications: Data storage, serial communication, multiplication/division by 2

ROM (Read Only Memory): Non-volatile, permanent storage

• Mask ROM, PROM, EPROM, EEPROM, Flash

RAM (Random Access Memory): Volatile storage

• SRAM (Static): Faster, uses flip-flops, no refresh

• DRAM (Dynamic): Slower, uses capacitors, needs refresh

Memory Organization: Address lines (A), data lines (D), control lines

Memory Capacity: \(2^A \times D\) bits

Memory Expansion: Increase word size or word count

PLA (Programmable Logic Array): Programmable AND and OR arrays

PAL (Programmable Array Logic): Programmable AND, fixed OR

FPGA (Field Programmable Gate Array): Most flexible

CPLD (Complex Programmable Logic Device): Between PAL and FPGA

Applications: Custom logic implementation, prototyping

Propagation Delay: Time for output to change after input change

Setup Time: Data must be stable before clock edge

Hold Time: Data must be stable after clock edge

Clock-to-Q Delay: Time for FF output to change after clock

Clock Skew: Difference in clock arrival times

Maximum Frequency: \(f_{max} = \frac{1}{t_{prop} + t_{setup} + t_{skew}}\)

Static-1 Hazard: Output momentarily goes to 0 when it should remain 1

Static-0 Hazard: Output momentarily goes to 1 when it should remain 0

Dynamic Hazard: Multiple transitions when only one expected

Cause: Different path delays in combinational circuits

Detection: Using timing diagrams and K-maps

Elimination: Add redundant terms to cover transition gaps

TTL (Transistor-Transistor Logic): Bipolar technology

• Fast switching, moderate power

• Totem-pole output

CMOS (Complementary MOS): NMOS + PMOS

• Very low static power

• High noise immunity

• Rail-to-rail output

ECL (Emitter Coupled Logic): High speed, constant current

Parameters: Fan-in, fan-out, noise margin, propagation delay, power

Static Power: Nearly zero (only leakage)

Dynamic Power: \(P = \alpha \cdot C \cdot V_{DD}^2 \cdot f\)

Noise Margins: High (typically 30-40% of VDD)

Fan-out: Very high (driven by capacitive loading)

Propagation Delay: \(t_{pd} = \frac{C \cdot V_{DD}}{I_{avg}}\)

Power-Delay Product: Figure of merit for logic families

Flash ADC: Parallel comparison, fastest but expensive

Successive Approximation ADC: Binary search method, moderate speed

Dual Slope ADC: High accuracy, slow speed

Parameters: Resolution (bits), conversion time, accuracy

Quantization Error: \(\pm \frac{1}{2}\) LSB

LSB: \(\frac{V_{FS}}{2^n}\) where \(V_{FS}\) is full scale, n is bits

Binary Weighted DAC: Resistor values in binary ratios

R-2R Ladder DAC: Uses only two resistor values

Parameters: Resolution, settling time, monotonicity

Output: \(V_{out} = V_{ref} \times \frac{D}{2^n}\) where D is digital input

Applications: Control systems, audio, waveform generation

Fan-out: \(\frac{I_{OL}}{I_{IL}}\) or \(\frac{I_{OH}}{I_{IH}}\)

Noise Margin High: \(V_{NMH} = V_{OH} - V_{IH}\)

Noise Margin Low: \(V_{NML} = V_{IL} - V_{OL}\)

Power-Delay Product: \(PDP = P_{avg} \times t_{pd}\)

Setup Time Constraint: \(T_{clk} \geq t_{pd} + t_{setup} + t_{skew}\)

Hold Time Constraint: \(t_{hold} \leq t_{cd} + t_{skew}\)

Dynamic Power: \(P = \alpha \cdot C \cdot V_{DD}^2 \cdot f\)

K-map simplification and Boolean algebra

Flip-flop excitation tables and conversions

Counter design (especially irregular sequences)

State machine design (sequence detectors)

Timing analysis and constraints

Logic family characteristics and interfacing

Memory organization and addressing

ADC/DAC numerical problems

Master K-map techniques for 3, 4, and 5 variables

Practice state machine design extensively

Understand timing analysis thoroughly

Memorize flip-flop excitation tables

Focus on counter design problems

Practice numerical problems on logic families

Solve previous 10 years’ GATE questions

Time management: allocate 2-3 minutes per question