Amplifiers: Biasing, Equivalent Circuits, and Frequency Response - GATE Preparation

Amplifier Fundamentals

Amplifier Basics

  • Purpose: Increase amplitude of input signal

  • Gain: \(A = \dfrac{V_{out}}{V_{in}}\) (voltage gain)

  • Power Gain: \(G_p = \dfrac{P_{out}}{P_{in}}\)

  • Current Gain: \(A_i = \dfrac{I_{out}}{I_{in}}\)

  • Decibel Gain: \(A_{dB} = 20\log_{10}|A|\)

  • Input Resistance: \(R_i = \dfrac{V_{in}}{I_{in}}\)

  • Output Resistance: \(R_o\) (Thevenin equivalent)

  • Slew Rate: Maximum rate of change of output voltage

Amplifier Classifications

  • By Signal Level: Small signal, Large signal

  • By Frequency: DC, Audio, RF, Microwave

  • By Coupling: Direct, RC, Transformer

  • By Configuration: CE, CB, CC (BJT); CS, CG, CD (FET)

  • By Class: Class A, B, AB, C, D

  • By Stages: Single-stage, Multi-stage

  • By Feedback: Open-loop, Closed-loop

Amplifier Performance Parameters

  • Bandwidth: \(BW = f_H - f_L\)

  • Rise Time: \(t_r = \dfrac{0.35}{f_H}\)

  • Settling Time: Time to reach within specified error

  • THD: Total Harmonic Distortion

  • SNR: Signal-to-Noise Ratio

  • Dynamic Range: Ratio of maximum to minimum signal

  • PSRR: Power Supply Rejection Ratio

BJT Biasing

Need for Biasing

  • Purpose: Set proper DC operating point (Q-point)

  • Q-Point: \((I_{CQ}, V_{CEQ})\) for linear operation

  • Load Line: \(V_{CE} = V_{CC} - I_C R_C\)

  • Stability: Maintain Q-point against temperature variations

  • Thermal Runaway: Avoided by proper biasing

  • Active Region: \(V_{BE} = 0.7V\), \(I_C = \beta I_B\)

  • Saturation: \(V_{CE(sat)} \approx 0.2V\)

  • Cutoff: \(I_B = 0\), \(I_C = I_{CEO}\)

Fixed Bias (Base Bias)

  • Circuit: Single resistor \(R_B\) from \(V_{CC}\) to base

  • Base Current: \(I_B = \dfrac{V_{CC} - V_{BE}}{R_B}\)

  • Collector Current: \(I_C = \beta I_B\)

  • Collector-Emitter Voltage: \(V_{CE} = V_{CC} - I_C R_C\)

  • Stability Factor: \(S = \dfrac{dI_C}{dI_{CO}} = 1 + \beta\)

  • Disadvantage: Poor thermal stability

  • Design: Choose \(R_B\) such that \(V_{CE} = \dfrac{V_{CC}}{2}\)

Collector Feedback Bias

  • Circuit: \(R_B\) connected between collector and base

  • Feedback: Negative feedback improves stability

  • Base Current: \(I_B = \dfrac{V_{CC} - V_{BE}}{R_B + \beta R_C}\)

  • Stability Factor: \(S = \dfrac{1 + \beta}{1 + \beta \dfrac{R_C}{R_B + R_C}}\)

  • Advantage: Better stability than fixed bias

  • Disadvantage: Gain reduction due to feedback

Self Bias (Emitter Bias)

  • Circuit: Emitter resistor \(R_E\) with dual supply

  • Emitter Current: \(I_E = \dfrac{V_{EE} - V_{BE}}{R_E}\)

  • Collector Current: \(I_C \approx I_E\) (since \(\beta >> 1\))

  • Stability Factor: \(S = \dfrac{1 + \beta}{1 + \beta \dfrac{R_E}{R_E + R_B}}\)

  • Advantage: Excellent stability

  • Disadvantage: Requires dual power supply

Voltage Divider Bias

  • Circuit: \(R_1\), \(R_2\) form voltage divider, \(R_E\) for stability

  • Thevenin Equivalent: \(V_{TH} = \dfrac{R_2 V_{CC}}{R_1 + R_2}\), \(R_{TH} = R_1 || R_2\)

  • Condition: \(R_{TH} << \beta R_E\) (stiff voltage divider)

  • Emitter Current: \(I_E = \dfrac{V_{TH} - V_{BE}}{R_E}\)

  • Stability Factor: \(S = \dfrac{1 + \beta}{1 + \beta \dfrac{R_E}{R_E + R_{TH}}}\)

  • Advantage: Best practical biasing method

  • Design Rule: \(I_2 = 10 I_B\) for stiff divider

Bias Stability Analysis

  • Stability Factor: \(S = \dfrac{dI_C}{dI_{CO}}\)

  • Temperature Coefficient: \(\dfrac{dI_C}{dT} = S \dfrac{dI_{CO}}{dT} + \dfrac{dI_C}{dV_{BE}} \dfrac{dV_{BE}}{dT}\)

  • Typical Values: \(\dfrac{dI_{CO}}{dT} = 2^{(T-25)/10}\), \(\dfrac{dV_{BE}}{dT} = -2mV/°C\)

  • Design Rule: \(S < 10\) for good stability

  • Compensation: Use temperature-sensitive components

  • Stability Factor S’: \(S' = \dfrac{dI_C}{dV_{BE}}\)

  • Stability Factor S”: \(S'' = \dfrac{dI_C}{d\beta}\)

FET Biasing

JFET Biasing

  • Operating Equation: \(I_D = I_{DSS}(1 - \dfrac{V_{GS}}{V_P})^2\)

  • Self Bias: Source resistor \(R_S\) provides bias

  • Gate Current: \(I_G = 0\) (ideal)

  • Source Current: \(I_S = I_D\)

  • Gate-Source Voltage: \(V_{GS} = -I_D R_S\)

  • Transconductance: \(g_m = \dfrac{2I_{DSS}}{|V_P|}(1 - \dfrac{V_{GS}}{V_P})\)

  • Pinch-off Voltage: \(V_P\) (negative for n-channel)

  • Voltage Divider Bias: Similar to BJT but with \(I_G = 0\)

MOSFET Biasing

  • Enhancement Mode: \(I_D = k(V_{GS} - V_T)^2\)

  • Depletion Mode: \(I_D = I_{DSS}(1 - \dfrac{V_{GS}}{V_P})^2\)

  • Voltage Divider Bias: Similar to BJT voltage divider

  • Drain Feedback: \(R_D\) connected to gate

  • Transconductance: \(g_m = 2k(V_{GS} - V_T)\)

  • Body Effect: \(g_{mb} = \eta g_m\) (bulk transconductance)

  • Threshold Voltage: \(V_T\) (positive for n-channel enhancement)

  • Process Parameter: \(k = \dfrac{1}{2}\mu_n C_{ox} \dfrac{W}{L}\)

Small Signal Equivalent Circuits

BJT Small Signal Model

  • Hybrid-\(\pi\) Model : Most commonly used

  • Input Resistance: \(r_\pi = \dfrac{\beta}{g_m} = \dfrac{\beta V_T}{I_C}\)

  • Transconductance: \(g_m = \dfrac{I_C}{V_T}\) where \(V_T = 26mV\)

  • Output Resistance: \(r_o = \dfrac{V_A}{I_C}\) (Early voltage effect)

  • Current Gain: \(\beta = h_{fe}\)

  • Miller Capacitance: \(C_\mu\) (base-collector capacitance)

  • Base Spreading Resistance: \(r_x\) (usually neglected)

  • Emitter Resistance: \(r_e = \dfrac{1}{g_m}\)

FET Small Signal Model

  • Transconductance: \(g_m = \dfrac{2I_D}{V_{GS} - V_T}\) (MOSFET)

  • Input Resistance: \(r_i = \infty\) (ideal)

  • Output Resistance: \(r_o = \dfrac{1}{\lambda I_D}\) (channel length modulation)

  • Gate-Source Capacitance: \(C_{gs}\)

  • Gate-Drain Capacitance: \(C_{gd}\) (Miller effect)

  • Body Transconductance: \(g_{mb}\) (if body not connected to source)

  • Channel Length Modulation: \(\lambda\) parameter

  • Substrate Bias Effect: \(\gamma\) parameter

Common Emitter Amplifier

  • Voltage Gain: \(A_v = -g_m R_L'\) where \(R_L' = R_C || R_L || r_o\)

  • Current Gain: \(A_i = \dfrac{\beta R_C}{R_C + R_L}\)

  • Input Resistance: \(R_i = R_1 || R_2 || r_\pi\)

  • Output Resistance: \(R_o = R_C || r_o\)

  • Power Gain: \(G_p = A_v \times A_i\)

  • Phase Shift: \(180°\) (inverting)

  • With Emitter Degeneration: \(A_v = -\dfrac{g_m R_L'}{1 + g_m R_E}\)

  • Bypassed Emitter: Higher gain, lower input resistance

Common Collector Amplifier (Emitter Follower)

  • Voltage Gain: \(A_v = \dfrac{R_L'}{R_L' + r_e}\) where \(r_e = \dfrac{1}{g_m}\)

  • Typical Gain: \(A_v \approx 1\) (unity gain)

  • Input Resistance: \(R_i = r_\pi + \beta R_L'\)

  • Output Resistance: \(R_o = r_e || \dfrac{R_s + r_\pi}{\beta}\)

  • Current Gain: \(A_i = \beta + 1\)

  • Application: Buffer amplifier, impedance matching

  • Advantage: High input impedance, low output impedance

  • Bootstrap Circuit: Further increases input impedance

Common Base Amplifier

  • Voltage Gain: \(A_v = g_m R_L'\)

  • Current Gain: \(A_i = \dfrac{\beta}{\beta + 1} \approx 1\)

  • Input Resistance: \(R_i = r_e = \dfrac{1}{g_m}\)

  • Output Resistance: \(R_o = R_C || r_o\)

  • Phase Shift: \(0°\) (non-inverting)

  • Application: High frequency amplifiers, current buffers

  • Advantage: High voltage gain, good high frequency response

  • Cascode Configuration: CB stage after CE stage

FET Amplifier Configurations

  • Common Source: \(A_v = -g_m R_L'\), \(R_i = R_G\), \(R_o = R_D || r_o\)

  • Common Drain (Source Follower): \(A_v = \dfrac{g_m R_L'}{1 + g_m R_L'}\)

  • Common Gate: \(A_v = g_m R_L'\), \(R_i = \dfrac{1}{g_m}\)

  • Cascode Amplifier: CS followed by CG

  • Folded Cascode: Modified cascode for single supply

  • Current Mirror: Active load for high gain

Frequency Response

Frequency Response Overview

  • Bandwidth: Range of frequencies over which gain remains constant

  • 3-dB Frequency: \(f_{3dB}\) where gain drops to \(\dfrac{A_{mid}}{\sqrt{2}}\)

  • Lower Cutoff: \(f_L\) (due to coupling and bypass capacitors)

  • Upper Cutoff: \(f_H\) (due to junction capacitances)

  • Midband: Frequency range where all capacitors are short/open

  • Gain-Bandwidth Product: \(GBW = A_{mid} \times BW\)

  • Dominant Pole: Pole that determines bandwidth

  • Pole-Zero Analysis: Complete frequency response

Low Frequency Response

  • Coupling Capacitors: \(C_{in}\), \(C_{out}\) cause gain reduction

  • Bypass Capacitor: \(C_E\) (emitter bypass) affects gain

  • Lower Cutoff: \(f_L = \dfrac{1}{2\pi RC}\)

  • Input Coupling: \(f_{L1} = \dfrac{1}{2\pi C_{in}(R_s + R_i)}\)

  • Output Coupling: \(f_{L2} = \dfrac{1}{2\pi C_{out}(R_o + R_L)}\)

  • Emitter Bypass: \(f_{L3} = \dfrac{1}{2\pi C_E R_E'}\)

  • Overall Lower Cutoff: \(f_L = \sqrt{f_{L1}^2 + f_{L2}^2 + f_{L3}^2}\)

  • Short Circuit Time Constants: For accurate analysis

High Frequency Response

  • Junction Capacitances: \(C_\pi\), \(C_\mu\) limit high frequency response

  • Miller Effect: \(C_\mu\) appears amplified at input

  • Miller Capacitance: \(C_M = C_\mu(1 + g_m R_L')\)

  • Upper Cutoff: \(f_H = \dfrac{1}{2\pi \tau}\) where \(\tau\) is time constant

  • Gain-Bandwidth Product: \(f_T = g_m/(2\pi C_\pi)\)

  • Stray Capacitances: Wiring and component capacitances

  • Open Circuit Time Constants: For accurate analysis

  • Unity Gain Frequency: \(f_T = \dfrac{g_m}{2\pi(C_\pi + C_\mu)}\)

Bode Plot Analysis

  • Magnitude Plot: \(|A(j\omega)|\) vs frequency (log scale)

  • Phase Plot: \(\angle A(j\omega)\) vs frequency

  • Decade: 10:1 frequency ratio

  • Octave: 2:1 frequency ratio

  • Roll-off Rate: 20 dB/decade or 6 dB/octave per pole

  • Asymptotic Approximation: Straight line approximations

  • Corner Frequency: Where asymptotes meet

  • Phase Margin: For stability analysis

Multi-stage Amplifiers

Cascade Amplifiers

  • Overall Gain: \(A_v = A_{v1} \times A_{v2} \times ... \times A_{vn}\)

  • dB Addition: \(A_{v(dB)} = A_{v1(dB)} + A_{v2(dB)} + ... + A_{vn(dB)}\)

  • Bandwidth: \(BW_{overall} < BW_{individual}\) (narrower)

  • Input Resistance: \(R_i = R_{i1}\)

  • Output Resistance: \(R_o = R_{on}\)

  • Loading Effect: Each stage loads the previous stage

  • Interstage Coupling: RC, direct, transformer

  • Buffer Stages: Prevent loading between stages

Feedback in Amplifiers

  • Negative Feedback: Reduces gain but improves stability

  • Feedback Factor: \(\beta = \dfrac{V_f}{V_o}\)

  • Loop Gain: \(A\beta\)

  • Closed Loop Gain: \(A_f = \dfrac{A}{1 + A\beta}\)

  • Advantages: Stable gain, reduced distortion, improved bandwidth

  • Disadvantages: Reduced gain, possibility of oscillation

  • Feedback Types: Voltage-series, Current-shunt, etc.

  • Barkhausen Criterion: \(A\beta = 1\) for oscillation

Feedback Topologies

  • Voltage-Series Feedback: \(A_f = \dfrac{A}{1 + A\beta}\), \(R_{if} = R_i(1 + A\beta)\)

  • Current-Shunt Feedback: \(A_{if} = \dfrac{A_i}{1 + A_i\beta}\), \(R_{if} = \dfrac{R_i}{1 + A_i\beta}\)

  • Voltage-Shunt Feedback: Transresistance amplifier

  • Current-Series Feedback: Transconductance amplifier

  • Desensitivity: \(D = 1 + A\beta\)

  • Bandwidth Extension: \(BW_f = BW \times D\)

Operational Amplifiers

Op-Amp Characteristics

  • Open Loop Gain: \(A_{OL} > 10^5\)

  • Input Impedance: \(R_i > 10^6 \Omega\)

  • Output Impedance: \(R_o < 100 \Omega\)

  • CMRR: \(> 80\) dB

  • Slew Rate: \(> 1\) V/\(\mu\)s

  • Bandwidth: Unity gain bandwidth

  • Input Bias Current: \(I_B < 1\) nA

  • Input Offset Voltage: \(V_{os} < 1\) mV

Op-Amp Configurations

  • Inverting Amplifier: \(A_v = -\dfrac{R_f}{R_i}\)

  • Non-inverting Amplifier: \(A_v = 1 + \dfrac{R_f}{R_i}\)

  • Unity Gain Buffer: \(A_v = 1\)

  • Summing Amplifier: \(V_o = -R_f(\dfrac{V_1}{R_1} + \dfrac{V_2}{R_2})\)

  • Difference Amplifier: \(V_o = \dfrac{R_f}{R_i}(V_2 - V_1)\)

  • Instrumentation Amplifier: High CMRR, high input impedance

  • Integrator: \(V_o = -\dfrac{1}{RC}\int V_i dt\)

  • Differentiator: \(V_o = -RC\dfrac{dV_i}{dt}\)

Differential Amplifiers

Differential Amplifier

  • Configuration: Two identical transistors with common emitter resistor

  • Differential Gain: \(A_d = \dfrac{g_m R_C}{2}\)

  • Common Mode Gain: \(A_{cm} = \dfrac{-g_m R_C}{2(1 + g_m R_E)}\)

  • CMRR: \(CMRR = \dfrac{A_d}{A_{cm}} = 1 + g_m R_E\)

  • Input Resistance: \(R_i = 2r_\pi\) (differential)

  • Applications: Op-amp input stage, instrumentation amplifiers

  • Tail Current: \(I_E = I_1 + I_2\)

  • Current Mirror Load: Improves gain and CMRR

Differential Amplifier Analysis

  • Half Circuit Analysis: For differential mode

  • Common Mode Analysis: Both inputs at same potential

  • Differential Input Resistance: \(R_{id} = 2r_\pi\)

  • Common Mode Input Resistance: \(R_{icm} = r_\pi + (1+\beta)R_E\)

  • Output Resistance: \(R_o = R_C || r_o\)

  • Offset Voltage: Due to component mismatch

  • Drift: Temperature variation of offset

  • Active Load: Current mirror as collector load

Current Mirrors and Active Loads

Current Mirror

  • Basic Current Mirror: Two matched transistors

  • Current Ratio: \(\dfrac{I_o}{I_{ref}} = \dfrac{W_2/L_2}{W_1/L_1}\) (MOSFET)

  • Output Resistance: \(r_o = \dfrac{1}{\lambda I_o}\)

  • Cascode Current Mirror: Improved output resistance

  • Wilson Current Mirror: Better current matching

  • Widlar Current Mirror: Different current ratios

  • Temperature Coefficient: \(\dfrac{1}{I_o}\dfrac{dI_o}{dT}\)

  • Compliance Voltage: Minimum voltage for proper operation

Active Loads

  • Purpose: Replace passive resistors with active devices

  • Advantages: Higher gain, better integration

  • Current Source Load: Provides high output resistance

  • Diode Connected Load: Simple but lower resistance

  • Differential Pair with Active Load: High gain amplifier

  • Folded Cascode: Single-ended output from differential pair

  • Output Swing: Limited by compliance voltage

  • Small Signal Resistance: \(r_o\) of current source

Power Amplifiers

Power Amplifier Classes

  • Class A: Conducts for full cycle, \(\eta_{max} = 25\%\) (RC), \(50\%\) (transformer)

  • Class B: Conducts for half cycle, \(\eta_{max} = 78.5\%\)

  • Class AB: Conducts for more than half cycle, \(\eta < 78.5\%\)

  • Class C: Conducts for less than half cycle, \(\eta > 78.5\%\)

  • Class D: Switching amplifier, \(\eta > 90\%\)

  • Crossover Distortion: Problem in Class B amplifiers

  • Heat Dissipation: Major concern in power amplifiers

  • Thermal Resistance: Junction to ambient

Class A Power Amplifier

  • Efficiency: \(\eta = \dfrac{P_{ac}}{P_{dc}} = \dfrac{P_L}{P_{dc}}\)

  • Resistive Load: \(\eta_{max} = 25\%\)

  • Transformer Coupled: \(\eta_{max} = 50\%\)

  • Power Dissipation: \(P_{dc} = V_{CC} I_{CQ}\)

  • Output Power: \(P_o = \dfrac{V_{rms}^2}{R_L}\)

  • Transistor Dissipation: \(P_T = P_{dc} - P_o\)

  • Heat Sink: Required for high power applications

  • Thermal Runaway: Prevented by proper biasing

  • Distortion: Low due to linear operation

Class B Push-Pull Amplifier

  • Configuration: Complementary pair (NPN-PNP)

  • Efficiency: \(\eta_{max} = \dfrac{\pi}{4} = 78.5\%\)

  • Power Output: \(P_o = \dfrac{V_{pp}^2}{8R_L}\)

  • DC Power: \(P_{dc} = \dfrac{2V_{CC}V_{pp}}{\pi R_L}\)

  • Transistor Dissipation: \(P_T = \dfrac{2V_{CC}^2}{\pi^2 R_L}\)

  • Crossover Distortion: Due to \(V_{BE}\) threshold

  • Solution: Class AB biasing with small forward bias

  • Thermal Coupling: Prevents thermal runaway

Class AB Amplifier

  • Bias Voltage: \(V_{bias} = 2V_{BE} = 1.4V\)

  • Quiescent Current: Small \(I_{CQ}\) flows in both transistors

  • Diode Bias: Two diodes provide bias voltage

  • \(V_{BE}\) Multiplier : Adjustable bias voltage

  • Thermal Stability: Bias circuit tracks temperature

  • Efficiency: Between Class A and Class B

  • Distortion: Much lower than Class B

  • Bootstrap Circuit: Improves performance

Power Amplifier Design Considerations

  • Thermal Management: Heat sinks, thermal resistance

  • Safe Operating Area: SOA limits

  • Current Limiting: Protect against overload

  • Voltage Limiting: Prevent breakdown

  • Protection Circuits: Fuses, current limiters

  • Stability: Compensation networks

  • EMI/RFI: Shielding and filtering

  • PCB Layout: Thermal vias, ground planes

Noise in Amplifiers

Noise Sources

  • Thermal Noise: \(v_n^2 = 4kTR\Delta f\)

  • Shot Noise: \(i_n^2 = 2qI\Delta f\)

  • Flicker Noise: \(1/f\) noise, \(v_n^2 \propto \dfrac{1}{f}\)

  • Generation-Recombination Noise: In semiconductors

  • Burst Noise: Popcorn noise

  • Avalanche Noise: In reverse-biased junctions

  • External Noise: Power line, digital switching

  • Noise Figure: \(NF = 10\log_{10}(F)\)

Noise Analysis

  • Noise Factor: \(F = \dfrac{S_i/N_i}{S_o/N_o}\)

  • Noise Temperature: \(T_e = (F-1)T_0\)

  • Equivalent Input Noise: \(v_{ni}^2\), \(i_{ni}^2\)

  • Cascaded Noise Factor: \(F_{total} = F_1 + \dfrac{F_2-1}{A_1} + \dfrac{F_3-1}{A_1A_2}\)

  • Friis Formula: For noise in cascaded systems

  • Noise Bandwidth: \(B_n = \dfrac{\pi}{2} \times 3dB \text{ bandwidth}\)

  • Signal-to-Noise Ratio: \(SNR = \dfrac{S}{N}\)

  • Noise Matching: Optimize source resistance

Stability and Compensation

Stability Criteria

  • Barkhausen Criterion: \(A\beta = 1\) for oscillation

  • Nyquist Criterion: Plot of \(A\beta\) in complex plane

  • Gain Margin: \(GM = 20\log_{10}|A\beta|\) at \(\phi = 180°\)

  • Phase Margin: \(PM = 180° - \phi\) at \(|A\beta| = 1\)

  • Stability Requirements: \(GM > 6dB\), \(PM > 45°\)

  • Conditional Stability: Stable for some source impedances

  • Unconditional Stability: Stable for all passive loads

  • Rollett Stability Factor: \(K = \dfrac{1-|S_{11}|^2-|S_{22}|^2+|\Delta|^2}{2|S_{12}||S_{21}|}\)

Compensation Techniques

  • Dominant Pole Compensation: Single pole dominates

  • Miller Compensation: Capacitor across high-gain stage

  • Pole Splitting: Creates two widely separated poles

  • Lead Compensation: Zero before dominant pole

  • Lag Compensation: Pole at low frequency

  • Pole-Zero Cancellation: Cancel unwanted poles

  • Feedforward Compensation: Bypass high-gain stage

  • Nested Miller Compensation: For multi-stage amplifiers

GATE Preparation Tips

Important GATE Topics

  • Biasing Circuits: All configurations, stability factors

  • Small Signal Analysis: Equivalent circuits, gain calculations

  • Frequency Response: Bode plots, bandwidth calculations

  • Feedback Systems: Types, effects, stability

  • Op-Amp Circuits: All configurations, non-ideal effects

  • Differential Amplifiers: CMRR, offset voltage

  • Power Amplifiers: Efficiency, classes, thermal design

  • Current Mirrors: Types, output resistance

Key Formulas for GATE

  • BJT: \(g_m = \dfrac{I_C}{V_T}\), \(r_\pi = \dfrac{\beta}{g_m}\), \(r_o = \dfrac{V_A}{I_C}\)

  • FET: \(g_m = \dfrac{2I_D}{V_{GS}-V_T}\), \(r_o = \dfrac{1}{\lambda I_D}\)

  • Amplifier Gain: \(A_v = -g_m R_L'\) (CE/CS)

  • Bandwidth: \(BW = f_H - f_L\), \(GBW = A_{mid} \times BW\)

  • Feedback: \(A_f = \dfrac{A}{1+A\beta}\), \(BW_f = BW(1+A\beta)\)

  • Op-Amp: \(A_v = -\dfrac{R_f}{R_i}\) (inverting)

  • Differential: \(CMRR = \dfrac{A_d}{A_{cm}}\)

  • Power: \(\eta = \dfrac{P_o}{P_{dc}}\), Class A: \(25\%\), Class B: \(78.5\%\)

Problem-Solving Strategy

  • DC Analysis: Find Q-point first

  • Small Signal: Replace with equivalent circuit

  • Frequency Response: Identify dominant poles/zeros

  • Numerical Problems: Use approximations when appropriate

  • Circuit Analysis: KVL, KCL, nodal analysis

  • Design Problems: Start with specifications

  • Multiple Choice: Eliminate wrong options

  • Time Management: Solve easier problems first

Common GATE Mistakes

  • Sign Errors: Especially in gain calculations

  • Wrong Models: Using inappropriate equivalent circuits

  • Approximations: When to use and when to avoid

  • Units: Always check dimensional consistency

  • Frequency Response: Confusing poles and zeros

  • Feedback: Wrong identification of feedback type

  • Op-Amp: Ignoring non-ideal effects when required

  • Power Calculations: Mixing RMS and peak values

Summary

  • Amplifiers: Fundamental building blocks of electronics

  • Biasing: Critical for proper operation and stability

  • Small Signal: Essential for linear analysis

  • Frequency Response: Determines bandwidth and applications

  • Feedback: Improves performance at cost of gain

  • Op-Amps: Versatile and widely used

  • Power Amplifiers: Efficiency and thermal management

  • Practice: Solve numerical problems regularly