Amplifier Fundamentals
Amplifier Basics
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Purpose: Increase amplitude of input signal
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Gain: \(A = \dfrac{V_{out}}{V_{in}}\) (voltage gain)
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Power Gain: \(G_p = \dfrac{P_{out}}{P_{in}}\)
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Current Gain: \(A_i = \dfrac{I_{out}}{I_{in}}\)
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Decibel Gain: \(A_{dB} = 20\log_{10}|A|\)
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Input Resistance: \(R_i = \dfrac{V_{in}}{I_{in}}\)
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Output Resistance: \(R_o\) (Thevenin equivalent)
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Slew Rate: Maximum rate of change of output voltage
Amplifier Classifications
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By Signal Level: Small signal, Large signal
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By Frequency: DC, Audio, RF, Microwave
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By Coupling: Direct, RC, Transformer
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By Configuration: CE, CB, CC (BJT); CS, CG, CD (FET)
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By Class: Class A, B, AB, C, D
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By Stages: Single-stage, Multi-stage
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By Feedback: Open-loop, Closed-loop
Amplifier Performance Parameters
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Bandwidth: \(BW = f_H - f_L\)
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Rise Time: \(t_r = \dfrac{0.35}{f_H}\)
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Settling Time: Time to reach within specified error
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THD: Total Harmonic Distortion
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SNR: Signal-to-Noise Ratio
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Dynamic Range: Ratio of maximum to minimum signal
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PSRR: Power Supply Rejection Ratio
BJT Biasing
Need for Biasing
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Purpose: Set proper DC operating point (Q-point)
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Q-Point: \((I_{CQ}, V_{CEQ})\) for linear operation
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Load Line: \(V_{CE} = V_{CC} - I_C R_C\)
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Stability: Maintain Q-point against temperature variations
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Thermal Runaway: Avoided by proper biasing
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Active Region: \(V_{BE} = 0.7V\), \(I_C = \beta I_B\)
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Saturation: \(V_{CE(sat)} \approx 0.2V\)
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Cutoff: \(I_B = 0\), \(I_C = I_{CEO}\)
Fixed Bias (Base Bias)
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Circuit: Single resistor \(R_B\) from \(V_{CC}\) to base
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Base Current: \(I_B = \dfrac{V_{CC} - V_{BE}}{R_B}\)
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Collector Current: \(I_C = \beta I_B\)
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Collector-Emitter Voltage: \(V_{CE} = V_{CC} - I_C R_C\)
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Stability Factor: \(S = \dfrac{dI_C}{dI_{CO}} = 1 + \beta\)
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Disadvantage: Poor thermal stability
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Design: Choose \(R_B\) such that \(V_{CE} = \dfrac{V_{CC}}{2}\)
Collector Feedback Bias
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Circuit: \(R_B\) connected between collector and base
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Feedback: Negative feedback improves stability
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Base Current: \(I_B = \dfrac{V_{CC} - V_{BE}}{R_B + \beta R_C}\)
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Stability Factor: \(S = \dfrac{1 + \beta}{1 + \beta \dfrac{R_C}{R_B + R_C}}\)
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Advantage: Better stability than fixed bias
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Disadvantage: Gain reduction due to feedback
Self Bias (Emitter Bias)
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Circuit: Emitter resistor \(R_E\) with dual supply
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Emitter Current: \(I_E = \dfrac{V_{EE} - V_{BE}}{R_E}\)
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Collector Current: \(I_C \approx I_E\) (since \(\beta >> 1\))
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Stability Factor: \(S = \dfrac{1 + \beta}{1 + \beta \dfrac{R_E}{R_E + R_B}}\)
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Advantage: Excellent stability
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Disadvantage: Requires dual power supply
Voltage Divider Bias
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Circuit: \(R_1\), \(R_2\) form voltage divider, \(R_E\) for stability
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Thevenin Equivalent: \(V_{TH} = \dfrac{R_2 V_{CC}}{R_1 + R_2}\), \(R_{TH} = R_1 || R_2\)
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Condition: \(R_{TH} << \beta R_E\) (stiff voltage divider)
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Emitter Current: \(I_E = \dfrac{V_{TH} - V_{BE}}{R_E}\)
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Stability Factor: \(S = \dfrac{1 + \beta}{1 + \beta \dfrac{R_E}{R_E + R_{TH}}}\)
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Advantage: Best practical biasing method
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Design Rule: \(I_2 = 10 I_B\) for stiff divider
Bias Stability Analysis
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Stability Factor: \(S = \dfrac{dI_C}{dI_{CO}}\)
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Temperature Coefficient: \(\dfrac{dI_C}{dT} = S \dfrac{dI_{CO}}{dT} + \dfrac{dI_C}{dV_{BE}} \dfrac{dV_{BE}}{dT}\)
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Typical Values: \(\dfrac{dI_{CO}}{dT} = 2^{(T-25)/10}\), \(\dfrac{dV_{BE}}{dT} = -2mV/°C\)
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Design Rule: \(S < 10\) for good stability
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Compensation: Use temperature-sensitive components
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Stability Factor S’: \(S' = \dfrac{dI_C}{dV_{BE}}\)
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Stability Factor S”: \(S'' = \dfrac{dI_C}{d\beta}\)
FET Biasing
JFET Biasing
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Operating Equation: \(I_D = I_{DSS}(1 - \dfrac{V_{GS}}{V_P})^2\)
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Self Bias: Source resistor \(R_S\) provides bias
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Gate Current: \(I_G = 0\) (ideal)
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Source Current: \(I_S = I_D\)
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Gate-Source Voltage: \(V_{GS} = -I_D R_S\)
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Transconductance: \(g_m = \dfrac{2I_{DSS}}{|V_P|}(1 - \dfrac{V_{GS}}{V_P})\)
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Pinch-off Voltage: \(V_P\) (negative for n-channel)
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Voltage Divider Bias: Similar to BJT but with \(I_G = 0\)
MOSFET Biasing
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Enhancement Mode: \(I_D = k(V_{GS} - V_T)^2\)
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Depletion Mode: \(I_D = I_{DSS}(1 - \dfrac{V_{GS}}{V_P})^2\)
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Voltage Divider Bias: Similar to BJT voltage divider
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Drain Feedback: \(R_D\) connected to gate
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Transconductance: \(g_m = 2k(V_{GS} - V_T)\)
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Body Effect: \(g_{mb} = \eta g_m\) (bulk transconductance)
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Threshold Voltage: \(V_T\) (positive for n-channel enhancement)
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Process Parameter: \(k = \dfrac{1}{2}\mu_n C_{ox} \dfrac{W}{L}\)
Small Signal Equivalent Circuits
BJT Small Signal Model
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Hybrid-\(\pi\) Model : Most commonly used
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Input Resistance: \(r_\pi = \dfrac{\beta}{g_m} = \dfrac{\beta V_T}{I_C}\)
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Transconductance: \(g_m = \dfrac{I_C}{V_T}\) where \(V_T = 26mV\)
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Output Resistance: \(r_o = \dfrac{V_A}{I_C}\) (Early voltage effect)
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Current Gain: \(\beta = h_{fe}\)
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Miller Capacitance: \(C_\mu\) (base-collector capacitance)
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Base Spreading Resistance: \(r_x\) (usually neglected)
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Emitter Resistance: \(r_e = \dfrac{1}{g_m}\)
FET Small Signal Model
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Transconductance: \(g_m = \dfrac{2I_D}{V_{GS} - V_T}\) (MOSFET)
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Input Resistance: \(r_i = \infty\) (ideal)
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Output Resistance: \(r_o = \dfrac{1}{\lambda I_D}\) (channel length modulation)
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Gate-Source Capacitance: \(C_{gs}\)
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Gate-Drain Capacitance: \(C_{gd}\) (Miller effect)
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Body Transconductance: \(g_{mb}\) (if body not connected to source)
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Channel Length Modulation: \(\lambda\) parameter
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Substrate Bias Effect: \(\gamma\) parameter
Common Emitter Amplifier
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Voltage Gain: \(A_v = -g_m R_L'\) where \(R_L' = R_C || R_L || r_o\)
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Current Gain: \(A_i = \dfrac{\beta R_C}{R_C + R_L}\)
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Input Resistance: \(R_i = R_1 || R_2 || r_\pi\)
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Output Resistance: \(R_o = R_C || r_o\)
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Power Gain: \(G_p = A_v \times A_i\)
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Phase Shift: \(180°\) (inverting)
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With Emitter Degeneration: \(A_v = -\dfrac{g_m R_L'}{1 + g_m R_E}\)
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Bypassed Emitter: Higher gain, lower input resistance
Common Collector Amplifier (Emitter Follower)
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Voltage Gain: \(A_v = \dfrac{R_L'}{R_L' + r_e}\) where \(r_e = \dfrac{1}{g_m}\)
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Typical Gain: \(A_v \approx 1\) (unity gain)
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Input Resistance: \(R_i = r_\pi + \beta R_L'\)
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Output Resistance: \(R_o = r_e || \dfrac{R_s + r_\pi}{\beta}\)
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Current Gain: \(A_i = \beta + 1\)
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Application: Buffer amplifier, impedance matching
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Advantage: High input impedance, low output impedance
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Bootstrap Circuit: Further increases input impedance
Common Base Amplifier
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Voltage Gain: \(A_v = g_m R_L'\)
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Current Gain: \(A_i = \dfrac{\beta}{\beta + 1} \approx 1\)
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Input Resistance: \(R_i = r_e = \dfrac{1}{g_m}\)
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Output Resistance: \(R_o = R_C || r_o\)
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Phase Shift: \(0°\) (non-inverting)
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Application: High frequency amplifiers, current buffers
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Advantage: High voltage gain, good high frequency response
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Cascode Configuration: CB stage after CE stage
FET Amplifier Configurations
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Common Source: \(A_v = -g_m R_L'\), \(R_i = R_G\), \(R_o = R_D || r_o\)
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Common Drain (Source Follower): \(A_v = \dfrac{g_m R_L'}{1 + g_m R_L'}\)
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Common Gate: \(A_v = g_m R_L'\), \(R_i = \dfrac{1}{g_m}\)
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Cascode Amplifier: CS followed by CG
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Folded Cascode: Modified cascode for single supply
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Current Mirror: Active load for high gain
Frequency Response
Frequency Response Overview
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Bandwidth: Range of frequencies over which gain remains constant
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3-dB Frequency: \(f_{3dB}\) where gain drops to \(\dfrac{A_{mid}}{\sqrt{2}}\)
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Lower Cutoff: \(f_L\) (due to coupling and bypass capacitors)
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Upper Cutoff: \(f_H\) (due to junction capacitances)
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Midband: Frequency range where all capacitors are short/open
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Gain-Bandwidth Product: \(GBW = A_{mid} \times BW\)
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Dominant Pole: Pole that determines bandwidth
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Pole-Zero Analysis: Complete frequency response
Low Frequency Response
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Coupling Capacitors: \(C_{in}\), \(C_{out}\) cause gain reduction
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Bypass Capacitor: \(C_E\) (emitter bypass) affects gain
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Lower Cutoff: \(f_L = \dfrac{1}{2\pi RC}\)
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Input Coupling: \(f_{L1} = \dfrac{1}{2\pi C_{in}(R_s + R_i)}\)
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Output Coupling: \(f_{L2} = \dfrac{1}{2\pi C_{out}(R_o + R_L)}\)
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Emitter Bypass: \(f_{L3} = \dfrac{1}{2\pi C_E R_E'}\)
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Overall Lower Cutoff: \(f_L = \sqrt{f_{L1}^2 + f_{L2}^2 + f_{L3}^2}\)
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Short Circuit Time Constants: For accurate analysis
High Frequency Response
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Junction Capacitances: \(C_\pi\), \(C_\mu\) limit high frequency response
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Miller Effect: \(C_\mu\) appears amplified at input
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Miller Capacitance: \(C_M = C_\mu(1 + g_m R_L')\)
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Upper Cutoff: \(f_H = \dfrac{1}{2\pi \tau}\) where \(\tau\) is time constant
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Gain-Bandwidth Product: \(f_T = g_m/(2\pi C_\pi)\)
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Stray Capacitances: Wiring and component capacitances
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Open Circuit Time Constants: For accurate analysis
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Unity Gain Frequency: \(f_T = \dfrac{g_m}{2\pi(C_\pi + C_\mu)}\)
Bode Plot Analysis
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Magnitude Plot: \(|A(j\omega)|\) vs frequency (log scale)
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Phase Plot: \(\angle A(j\omega)\) vs frequency
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Decade: 10:1 frequency ratio
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Octave: 2:1 frequency ratio
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Roll-off Rate: 20 dB/decade or 6 dB/octave per pole
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Asymptotic Approximation: Straight line approximations
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Corner Frequency: Where asymptotes meet
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Phase Margin: For stability analysis
Multi-stage Amplifiers
Cascade Amplifiers
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Overall Gain: \(A_v = A_{v1} \times A_{v2} \times ... \times A_{vn}\)
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dB Addition: \(A_{v(dB)} = A_{v1(dB)} + A_{v2(dB)} + ... + A_{vn(dB)}\)
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Bandwidth: \(BW_{overall} < BW_{individual}\) (narrower)
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Input Resistance: \(R_i = R_{i1}\)
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Output Resistance: \(R_o = R_{on}\)
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Loading Effect: Each stage loads the previous stage
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Interstage Coupling: RC, direct, transformer
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Buffer Stages: Prevent loading between stages
Feedback in Amplifiers
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Negative Feedback: Reduces gain but improves stability
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Feedback Factor: \(\beta = \dfrac{V_f}{V_o}\)
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Loop Gain: \(A\beta\)
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Closed Loop Gain: \(A_f = \dfrac{A}{1 + A\beta}\)
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Advantages: Stable gain, reduced distortion, improved bandwidth
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Disadvantages: Reduced gain, possibility of oscillation
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Feedback Types: Voltage-series, Current-shunt, etc.
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Barkhausen Criterion: \(A\beta = 1\) for oscillation
Feedback Topologies
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Voltage-Series Feedback: \(A_f = \dfrac{A}{1 + A\beta}\), \(R_{if} = R_i(1 + A\beta)\)
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Current-Shunt Feedback: \(A_{if} = \dfrac{A_i}{1 + A_i\beta}\), \(R_{if} = \dfrac{R_i}{1 + A_i\beta}\)
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Voltage-Shunt Feedback: Transresistance amplifier
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Current-Series Feedback: Transconductance amplifier
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Desensitivity: \(D = 1 + A\beta\)
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Bandwidth Extension: \(BW_f = BW \times D\)
Operational Amplifiers
Op-Amp Characteristics
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Open Loop Gain: \(A_{OL} > 10^5\)
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Input Impedance: \(R_i > 10^6 \Omega\)
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Output Impedance: \(R_o < 100 \Omega\)
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CMRR: \(> 80\) dB
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Slew Rate: \(> 1\) V/\(\mu\)s
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Bandwidth: Unity gain bandwidth
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Input Bias Current: \(I_B < 1\) nA
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Input Offset Voltage: \(V_{os} < 1\) mV
Op-Amp Configurations
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Inverting Amplifier: \(A_v = -\dfrac{R_f}{R_i}\)
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Non-inverting Amplifier: \(A_v = 1 + \dfrac{R_f}{R_i}\)
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Unity Gain Buffer: \(A_v = 1\)
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Summing Amplifier: \(V_o = -R_f(\dfrac{V_1}{R_1} + \dfrac{V_2}{R_2})\)
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Difference Amplifier: \(V_o = \dfrac{R_f}{R_i}(V_2 - V_1)\)
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Instrumentation Amplifier: High CMRR, high input impedance
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Integrator: \(V_o = -\dfrac{1}{RC}\int V_i dt\)
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Differentiator: \(V_o = -RC\dfrac{dV_i}{dt}\)
Differential Amplifiers
Differential Amplifier
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Configuration: Two identical transistors with common emitter resistor
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Differential Gain: \(A_d = \dfrac{g_m R_C}{2}\)
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Common Mode Gain: \(A_{cm} = \dfrac{-g_m R_C}{2(1 + g_m R_E)}\)
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CMRR: \(CMRR = \dfrac{A_d}{A_{cm}} = 1 + g_m R_E\)
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Input Resistance: \(R_i = 2r_\pi\) (differential)
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Applications: Op-amp input stage, instrumentation amplifiers
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Tail Current: \(I_E = I_1 + I_2\)
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Current Mirror Load: Improves gain and CMRR
Differential Amplifier Analysis
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Half Circuit Analysis: For differential mode
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Common Mode Analysis: Both inputs at same potential
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Differential Input Resistance: \(R_{id} = 2r_\pi\)
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Common Mode Input Resistance: \(R_{icm} = r_\pi + (1+\beta)R_E\)
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Output Resistance: \(R_o = R_C || r_o\)
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Offset Voltage: Due to component mismatch
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Drift: Temperature variation of offset
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Active Load: Current mirror as collector load
Current Mirrors and Active Loads
Current Mirror
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Basic Current Mirror: Two matched transistors
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Current Ratio: \(\dfrac{I_o}{I_{ref}} = \dfrac{W_2/L_2}{W_1/L_1}\) (MOSFET)
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Output Resistance: \(r_o = \dfrac{1}{\lambda I_o}\)
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Cascode Current Mirror: Improved output resistance
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Wilson Current Mirror: Better current matching
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Widlar Current Mirror: Different current ratios
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Temperature Coefficient: \(\dfrac{1}{I_o}\dfrac{dI_o}{dT}\)
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Compliance Voltage: Minimum voltage for proper operation
Active Loads
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Purpose: Replace passive resistors with active devices
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Advantages: Higher gain, better integration
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Current Source Load: Provides high output resistance
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Diode Connected Load: Simple but lower resistance
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Differential Pair with Active Load: High gain amplifier
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Folded Cascode: Single-ended output from differential pair
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Output Swing: Limited by compliance voltage
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Small Signal Resistance: \(r_o\) of current source
Power Amplifiers
Power Amplifier Classes
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Class A: Conducts for full cycle, \(\eta_{max} = 25\%\) (RC), \(50\%\) (transformer)
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Class B: Conducts for half cycle, \(\eta_{max} = 78.5\%\)
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Class AB: Conducts for more than half cycle, \(\eta < 78.5\%\)
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Class C: Conducts for less than half cycle, \(\eta > 78.5\%\)
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Class D: Switching amplifier, \(\eta > 90\%\)
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Crossover Distortion: Problem in Class B amplifiers
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Heat Dissipation: Major concern in power amplifiers
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Thermal Resistance: Junction to ambient
Class A Power Amplifier
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Efficiency: \(\eta = \dfrac{P_{ac}}{P_{dc}} = \dfrac{P_L}{P_{dc}}\)
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Resistive Load: \(\eta_{max} = 25\%\)
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Transformer Coupled: \(\eta_{max} = 50\%\)
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Power Dissipation: \(P_{dc} = V_{CC} I_{CQ}\)
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Output Power: \(P_o = \dfrac{V_{rms}^2}{R_L}\)
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Transistor Dissipation: \(P_T = P_{dc} - P_o\)
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Heat Sink: Required for high power applications
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Thermal Runaway: Prevented by proper biasing
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Distortion: Low due to linear operation
Class B Push-Pull Amplifier
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Configuration: Complementary pair (NPN-PNP)
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Efficiency: \(\eta_{max} = \dfrac{\pi}{4} = 78.5\%\)
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Power Output: \(P_o = \dfrac{V_{pp}^2}{8R_L}\)
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DC Power: \(P_{dc} = \dfrac{2V_{CC}V_{pp}}{\pi R_L}\)
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Transistor Dissipation: \(P_T = \dfrac{2V_{CC}^2}{\pi^2 R_L}\)
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Crossover Distortion: Due to \(V_{BE}\) threshold
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Solution: Class AB biasing with small forward bias
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Thermal Coupling: Prevents thermal runaway
Class AB Amplifier
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Bias Voltage: \(V_{bias} = 2V_{BE} = 1.4V\)
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Quiescent Current: Small \(I_{CQ}\) flows in both transistors
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Diode Bias: Two diodes provide bias voltage
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\(V_{BE}\) Multiplier : Adjustable bias voltage
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Thermal Stability: Bias circuit tracks temperature
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Efficiency: Between Class A and Class B
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Distortion: Much lower than Class B
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Bootstrap Circuit: Improves performance
Power Amplifier Design Considerations
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Thermal Management: Heat sinks, thermal resistance
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Safe Operating Area: SOA limits
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Current Limiting: Protect against overload
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Voltage Limiting: Prevent breakdown
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Protection Circuits: Fuses, current limiters
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Stability: Compensation networks
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EMI/RFI: Shielding and filtering
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PCB Layout: Thermal vias, ground planes
Noise in Amplifiers
Noise Sources
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Thermal Noise: \(v_n^2 = 4kTR\Delta f\)
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Shot Noise: \(i_n^2 = 2qI\Delta f\)
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Flicker Noise: \(1/f\) noise, \(v_n^2 \propto \dfrac{1}{f}\)
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Generation-Recombination Noise: In semiconductors
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Burst Noise: Popcorn noise
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Avalanche Noise: In reverse-biased junctions
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External Noise: Power line, digital switching
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Noise Figure: \(NF = 10\log_{10}(F)\)
Noise Analysis
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Noise Factor: \(F = \dfrac{S_i/N_i}{S_o/N_o}\)
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Noise Temperature: \(T_e = (F-1)T_0\)
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Equivalent Input Noise: \(v_{ni}^2\), \(i_{ni}^2\)
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Cascaded Noise Factor: \(F_{total} = F_1 + \dfrac{F_2-1}{A_1} + \dfrac{F_3-1}{A_1A_2}\)
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Friis Formula: For noise in cascaded systems
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Noise Bandwidth: \(B_n = \dfrac{\pi}{2} \times 3dB \text{ bandwidth}\)
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Signal-to-Noise Ratio: \(SNR = \dfrac{S}{N}\)
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Noise Matching: Optimize source resistance
Stability and Compensation
Stability Criteria
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Barkhausen Criterion: \(A\beta = 1\) for oscillation
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Nyquist Criterion: Plot of \(A\beta\) in complex plane
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Gain Margin: \(GM = 20\log_{10}|A\beta|\) at \(\phi = 180°\)
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Phase Margin: \(PM = 180° - \phi\) at \(|A\beta| = 1\)
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Stability Requirements: \(GM > 6dB\), \(PM > 45°\)
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Conditional Stability: Stable for some source impedances
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Unconditional Stability: Stable for all passive loads
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Rollett Stability Factor: \(K = \dfrac{1-|S_{11}|^2-|S_{22}|^2+|\Delta|^2}{2|S_{12}||S_{21}|}\)
Compensation Techniques
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Dominant Pole Compensation: Single pole dominates
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Miller Compensation: Capacitor across high-gain stage
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Pole Splitting: Creates two widely separated poles
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Lead Compensation: Zero before dominant pole
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Lag Compensation: Pole at low frequency
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Pole-Zero Cancellation: Cancel unwanted poles
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Feedforward Compensation: Bypass high-gain stage
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Nested Miller Compensation: For multi-stage amplifiers
GATE Preparation Tips
Important GATE Topics
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Biasing Circuits: All configurations, stability factors
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Small Signal Analysis: Equivalent circuits, gain calculations
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Frequency Response: Bode plots, bandwidth calculations
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Feedback Systems: Types, effects, stability
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Op-Amp Circuits: All configurations, non-ideal effects
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Differential Amplifiers: CMRR, offset voltage
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Power Amplifiers: Efficiency, classes, thermal design
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Current Mirrors: Types, output resistance
Key Formulas for GATE
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BJT: \(g_m = \dfrac{I_C}{V_T}\), \(r_\pi = \dfrac{\beta}{g_m}\), \(r_o = \dfrac{V_A}{I_C}\)
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FET: \(g_m = \dfrac{2I_D}{V_{GS}-V_T}\), \(r_o = \dfrac{1}{\lambda I_D}\)
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Amplifier Gain: \(A_v = -g_m R_L'\) (CE/CS)
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Bandwidth: \(BW = f_H - f_L\), \(GBW = A_{mid} \times BW\)
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Feedback: \(A_f = \dfrac{A}{1+A\beta}\), \(BW_f = BW(1+A\beta)\)
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Op-Amp: \(A_v = -\dfrac{R_f}{R_i}\) (inverting)
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Differential: \(CMRR = \dfrac{A_d}{A_{cm}}\)
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Power: \(\eta = \dfrac{P_o}{P_{dc}}\), Class A: \(25\%\), Class B: \(78.5\%\)
Problem-Solving Strategy
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DC Analysis: Find Q-point first
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Small Signal: Replace with equivalent circuit
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Frequency Response: Identify dominant poles/zeros
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Numerical Problems: Use approximations when appropriate
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Circuit Analysis: KVL, KCL, nodal analysis
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Design Problems: Start with specifications
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Multiple Choice: Eliminate wrong options
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Time Management: Solve easier problems first
Common GATE Mistakes
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Sign Errors: Especially in gain calculations
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Wrong Models: Using inappropriate equivalent circuits
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Approximations: When to use and when to avoid
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Units: Always check dimensional consistency
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Frequency Response: Confusing poles and zeros
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Feedback: Wrong identification of feedback type
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Op-Amp: Ignoring non-ideal effects when required
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Power Calculations: Mixing RMS and peak values
Summary
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Amplifiers: Fundamental building blocks of electronics
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Biasing: Critical for proper operation and stability
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Small Signal: Essential for linear analysis
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Frequency Response: Determines bandwidth and applications
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Feedback: Improves performance at cost of gain
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Op-Amps: Versatile and widely used
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Power Amplifiers: Efficiency and thermal management
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Practice: Solve numerical problems regularly