By the end of this chapter you should be able to:
- Redraw the four-layer PNPN structure as two interconnected transistors and derive \(I_A = (\alpha_2I_G + I_{CBO})/(1 - \alpha_1 - \alpha_2)\).
- Identify every named point on the SCR characteristic: \(V_{BO}\), \(V_{RRM}\), \(I_L\) and \(I_H\), and distinguish latching from holding current.
- Design a gate trigger circuit and check it against the gate characteristic and the gate power limit.
- Quantify \(dV/dt\) triggering and design an RC snubber to prevent it.
- Distinguish natural from forced commutation and size a commutating capacitor from the turn-off time \(t_q\).
- Explain DIAC and TRIAC operation, name the four TRIAC trigger quadrants, and compute the output of a phase controller.
- Analyse a UJT relaxation oscillator using the intrinsic standoff ratio and compute its frequency.
Every device so far has been an amplifier or a rectifier: its output follows its input continuously, and removing the input removes the output. The devices in this chapter do something different. A thyristor is a four-layer PNPN structure that has two stable states — blocking and conducting — and a positive-feedback mechanism inside it that drives it from one to the other. Once it has been triggered into conduction it latches: the trigger can be removed entirely and the device stays on until the load current itself falls below a threshold. It is a switch, not an amplifier, and the whole of its usefulness follows from that.
The advantage is enormous. A silicon controlled rectifier that carries 12 A at 600 V can be turned on by 15 mA at 1.5 V — a control power of 22 mW commanding a load power of several kilowatts, with no continuous drive current at all because the device holds itself on. That is why thyristors run motor drives, lamp dimmers, heater controllers, welding sets, high-voltage DC transmission and every crowbar overvoltage protector. The corresponding difficulty is that a device which latches must be persuaded to unlatch, and the whole subject of commutation exists to solve that.
Four members of the family appear here. The SCR is the unidirectional thyristor with a gate. The DIAC is a symmetrical two-terminal trigger with no gate at all, which breaks over at about 32 V in either direction. The TRIAC is two SCRs in inverse parallel on one die, so it controls both halves of an AC cycle from one gate. The UJT is not a thyristor but belongs with them, because its negative-resistance characteristic makes the relaxation oscillator that has triggered more thyristors than any other circuit. The chapter derives the latching condition from a two-transistor model, works through the V-I characteristic point by point, treats triggering and commutation quantitatively, and finishes with a phase-control design.
1 The PNPN Structure and the Two-Transistor Model
An SCR is four alternating layers, \(p\)-\(n\)-\(p\)-\(n\), with the anode on the outer \(p\) layer, the cathode on the outer \(n\) layer and the gate on the inner \(p\) layer. That gives three junctions in series: \(J_1\) at the anode end, \(J_2\) in the middle and \(J_3\) at the cathode end. With the anode positive, \(J_1\) and \(J_3\) are forward biased and \(J_2\) is reverse biased, so the structure blocks — the whole applied voltage stands across one junction. With the anode negative, \(J_1\) and \(J_3\) block instead, which is why an SCR withstands voltage in both directions.
Why the device should suddenly stop blocking is not obvious from the four layers, and becomes obvious the moment they are split. Cut the structure diagonally so that the two inner layers are each shared between two halves, and it becomes a PNP transistor and an NPN transistor with the collector of each driving the base of the other.
Figure 15.1 carries out that split. Now write the currents: for a transistor in the common-base connection, \(I_C = \alpha I_E + I_{CBO}\). In the equivalent circuit the emitter of \(Q_1\) is the anode and the emitter of \(Q_2\) is the cathode, so both emitter currents are the anode current \(I_A\) (plus the gate current for \(Q_2\)). At the base node of \(Q_1\), which is also the collector of \(Q_2\):
Collecting the \(I_A\) terms and solving:
This single expression contains the entire behaviour of the device. The denominator is what matters: as \(\alpha_1 + \alpha_2\) approaches unity, \(I_A\) grows without bound, limited in a real circuit only by the external load. The latching condition is therefore \(\alpha_1 + \alpha_2 = 1\).
What makes the condition reachable is that \(\alpha\) is not a constant. At the very low currents that flow in the blocking state, recombination in the base consumes most of the injected carriers and \(\alpha\) may be 0.1 or less; as the current rises the base transport becomes more efficient and \(\alpha\) climbs towards 0.99. So anything that raises the current raises the loop gain, and once the sum passes unity the process is self-sustaining. Substituting numbers with \(I_{CBO1} = I_{CBO2} = 1\) µA:
| \(\alpha_1\) | \(\alpha_2\) | Sum | \(I_A\) with \(I_G = 0\) | \(I_A\) with \(I_G = 5\) mA |
|---|---|---|---|---|
| 0.10 | 0.15 | 0.25 | 2.7 µA | 1.0 mA |
| 0.30 | 0.35 | 0.65 | 5.7 µA | 5.0 mA |
| 0.45 | 0.50 | 0.95 | 40 µA | 50.0 mA |
| 0.49 | 0.50 | 0.99 | 200 µA | 250 mA |
| 0.50 | 0.50 | 1.00 | ∞ — latched | ∞ — latched |
Two observations close the argument. First, the gate current appears in the numerator multiplied by \(\alpha_2\), so a modest gate current produces a large anode current even before the loop gain reaches unity — and that larger anode current raises both \(\alpha\) values, which raises the current further. The regeneration is what does the work; the gate merely starts it. Second, once the device has latched, the anode current is set entirely by the external circuit and the gate has no influence at all, because the loop is now supplying its own base drive. That is the fundamental difference between a thyristor and a transistor.
2 The SCR Characteristic and Its Named Points
Figure 15.2 shows the complete V-I characteristic. It has three distinct regions and a set of named points, every one of which appears on a datasheet.
Reverse blocking region. With the anode negative, \(J_1\) and \(J_3\) block and only a leakage current of microamperes flows. This continues up to the reverse repetitive peak voltage \(V_{RRM}\), beyond which the junctions avalanche. Unlike a Zener, an SCR is not designed to survive reverse breakdown, and exceeding \(V_{RRM}\) usually destroys it.
Forward blocking region. With the anode positive, \(J_2\) blocks and again only leakage flows. The device behaves as an open switch, but the loop gain is quietly rising with the leakage current. At the forward breakover voltage \(V_{BO}\) the multiplication of leakage across \(J_2\) has raised \(\alpha_1+\alpha_2\) to unity and the device snaps into conduction with no gate current at all. Breaking over is a legitimate turn-on mechanism — it is exactly how a DIAC works — but for an SCR it is a fault condition, because it is uncontrolled and the resulting current surge is unlimited.
Forward conducting region. Once latched, the SCR behaves as a forward-biased diode: the on-state voltage \(V_T\) is 1 to 2 V almost independently of current, and the current is set entirely by the external circuit. The characteristic between breakover and the on-state, drawn dashed in Figure 15.2, is a negative-resistance region that the device traverses in a few microseconds and never rests in.
Two currents define the boundary of the latched state, and confusing them is the commonest error in this subject.
- The latching current \(I_L\) is the minimum anode current that must be reached while the gate signal is still present for the device to stay on when the gate is removed. It is the current at which the regenerative loop becomes self-sustaining.
- The holding current \(I_H\) is the minimum anode current needed to keep an already-latched device conducting. It is measured with no gate drive and it is smaller than \(I_L\), typically by a factor of two or three.
For a 12 A, 600 V device, typical figures are \(I_L = 40\) mA and \(I_H = 20\) mA. The practical consequence is that a highly inductive load, whose current rises slowly, may not reach \(I_L\) during a short gate pulse and will fail to latch — the reason inductive loads need a pulse train or a longer gate pulse. And a lamp dimmer driving a 60 W lamp at 230 V draws 261 mA at full conduction but only 44 mA at a firing angle of 150°, which is why dimmers become unstable and flicker near the bottom of their range: the load current is approaching \(I_H\).
The conduction loss is the one thermal figure that must always be computed. It has a constant-voltage part and a resistive part, exactly as for the diode of Chapter 8:
With \(V_{T0} = 0.9\) V, \(r_T = 8\) m\(\Omega\), \(I_{T(AV)} = 8\) A and \(I_{T(RMS)} = 12.6\) A, the loss is \(7.2 + 1.27 = 8.47\) W. With a junction-to-case thermal resistance of 1.5 K/W the junction sits 12.7 K above the case, so the heatsink must hold the case below about 112 °C for a 125 °C junction limit.
3 Triggering, and the Ways a Thyristor Turns On Uninvited
The intended way to turn an SCR on is gate triggering, and the gate is a p-n junction like any other. The gate characteristic on a datasheet is not a line but a region, because gate parameters vary enormously between devices and with temperature: the manufacturer guarantees only that any device will trigger somewhere inside it. Four limits bound the design.
- \(V_{GT}\) and \(I_{GT}\), the minimum gate voltage and current that will trigger the least sensitive device — typically 1.5 V and 15 mA.
- \(V_{GD}\), the maximum gate voltage that will not trigger the most sensitive device, typically 0.25 V. The drive must be below this in the off state, so noise on the gate lead matters.
- \(P_{GM}\), the peak gate power, and \(P_{G(AV)}\), the average — typically 5 W peak and 0.5 W average.
- The load line of the gate drive circuit, which must intersect the guaranteed-trigger region while staying inside the power limits.
An SCR has \(V_{GT} = 1.5\) V, \(I_{GT} = 15\) mA and \(P_{G(AV)} = 0.5\) W. Drive it from a 12 V pulse source at twice the guaranteed trigger current.
Target current. \(I_G = 2I_{GT} = 30\) mA, which gives margin for temperature (\(I_{GT}\) rises as the device cools) and for device spread.
Series resistor. \(R_G = (V_S - V_{GT})/I_G = (12 - 1.5)/0.030 = 350\ \Omega\). Choose 330 \(\Omega\), giving \(I_G = (12-1.5)/330 = 31.8\) mA.
Gate power. \(P_G = V_{GT}I_G = 1.5\times0.0318 = 47.7\) mW, a factor of ten below the average limit, so a continuous drive would even be permissible.
Resistor rating. \(P_R = I_G^2R_G = (0.0318)^2\times330 = 0.334\) W if driven continuously, so specify 0.5 W — or, if the gate is pulsed at low duty cycle, a 0.125 W part suffices.
Pulse width. The pulse must last long enough for the anode current to exceed \(I_L = 40\) mA. For a resistive load that is a few microseconds; for a load with \(L/R = 5\) ms it takes \(-\tau\ln(1 - I_L/I_{final})\), which for a 5 A final current is 40 µs. Specify a 100 µs pulse, or a burst of short pulses, and the design works for either load.
Gate triggering is not the only way in, and the other four routes are all failure modes.
- Forward voltage triggering. Exceeding \(V_{BO}\) turns the device on without a gate signal. Uncontrolled, and the surge often destroys the device.
- Thermal triggering. Leakage across \(J_2\) roughly doubles every 10 °C, and more leakage means higher \(\alpha\). A hot SCR breaks over at a lower voltage, so \(V_{BO}\) is a temperature-dependent rating.
- Light triggering. Photons absorbed in the depletion region of \(J_2\) generate carriers exactly as in the photodiode of Chapter 14. This is a deliberate mechanism in light-activated SCRs, used in high-voltage DC converters where the gate drive must be optically isolated.
- \(dV/dt\) triggering. The most important of the four in practice, and the one that must be designed against.
The junction \(J_2\) has capacitance \(C_j\), and a capacitance carries current when the voltage across it changes: \(i = C_j\,dV/dt\). That current arrives at the internal base regions and is indistinguishable from gate current. With \(C_j = 50\) pF, the numbers are alarming:
| \(dV/dt\) | Injected current \(C_j\,dV/dt\) | Compare with \(I_{GT} = 15\) mA |
|---|---|---|
| 10 V/µs | 0.5 mA | Safe |
| 100 V/µs | 5 mA | Marginal on a sensitive device |
| 300 V/µs | 15 mA | Triggers |
| 1000 V/µs | 50 mA | Certain false turn-on |
A mains transient, the turn-off of a neighbouring inductive load, or simply the closing of the supply switch can present hundreds of volts per microsecond. The remedy is an RC snubber across the device, which limits the initial rate of rise to \(V/RC\):
With \(R = 100\ \Omega\), \(C = 0.1\) µF and a 340 V peak supply, the initial rate is \(340/(100\times10^{-7}) = 34\) V/µs — comfortably below the device's 500 V/µs rating and below the level that triggers it. The resistor is not optional: without it the capacitor would discharge through the SCR at turn-on with a peak current of \(V/R\), here 3.4 A, which the resistor limits. The snubber dissipates \(CV^2f = 0.1\ \mu\text{F}\times340^2\times50 = 0.58\) W, so the resistor must be rated for it.
4 Turn-Off and Commutation
Turning a thyristor off is harder than turning it on, because the gate has no authority over a latched device. The only way out of the conducting state is to break the regenerative loop, and that means reducing the anode current below \(I_H\) for long enough that the stored charge in the four layers recombines.
The time required is the circuit turn-off time \(t_q\), typically 10 to 100 µs for a converter-grade device and 5 to 20 µs for an inverter-grade one. During \(t_q\) the device must be held at zero or reverse voltage; reapplying forward voltage too soon finds the stored charge still present, \(\alpha_1+\alpha_2\) still near unity, and the SCR simply turns on again without any gate signal.
Natural (line) commutation is the easy case and needs no extra components. In any AC circuit the supply reverses every half-cycle, so the anode current passes through zero of its own accord and the device turns off. At 50 Hz the reverse voltage is applied for the whole of a 10 ms half-cycle, which is a hundred times \(t_q\), so the margin is generous. Every phase-controlled rectifier, lamp dimmer and AC motor controller relies on this, and it is the reason thyristors dominate mains-frequency power control and have been displaced by transistors almost everywhere else.
Forced commutation is needed whenever the supply is DC — choppers, inverters, DC motor drives — and it requires an auxiliary circuit to do what the mains does for free. The commonest scheme charges a capacitor to a voltage \(V_C\) and then, when turn-off is wanted, switches it across the conducting SCR so that it drives the anode current to zero and holds the device in reverse for long enough. The capacitor must supply the load current \(I_T\) for at least \(t_q\):
For \(I_T = 10\) A, \(t_q = 50\) µs and \(V_C = 100\) V, \(C \ge 5\) µF. Doubling the capacitor voltage to 200 V halves the capacitance to 2.5 µF, which is why forced-commutation circuits charge the capacitor as high as the device ratings allow. A safety factor of 1.5 to 2 on \(t_q\) is normal practice.
A commutating circuit needs a capacitor, an inductor, a diode and a second SCR to charge and fire it, and the energy stored in that capacitor is dumped every switching cycle: \(\tfrac12CV_C^2f = \tfrac12\times5\ \mu\text{F}\times100^2\times1\ \text{kHz} = 25\) W at just 1 kHz. The loss scales with frequency, so forced-commutated thyristor inverters were limited to a few hundred hertz. A power MOSFET or IGBT turns off simply by removing its gate drive, at any frequency, which is why every modern inverter uses one. Thyristors survive precisely where natural commutation is available and the currents are very large: HVDC converters, large motor soft-starters and mains phase control.
Two variants deserve a mention. The gate turn-off thyristor (GTO) is built so that a large negative gate current — typically a fifth of the anode current, so 2 A to turn off 10 A — can starve the NPN section and break the loop. It removes the need for a commutating circuit at the cost of a demanding gate drive, and it was the workhorse of traction inverters before the IGBT. And the reverse recovery of the SCR's own junctions means that at turn-off a reverse current flows briefly, exactly as in the rectifier of Chapter 13; the \(di/dt\) of that recovery is what the snubber inductor in a series string is there to limit.
One more rating belongs here. At turn-on, conduction starts in a small area next to the gate and spreads across the die at about 0.1 mm/µs. If the anode current rises faster than the conducting area grows, the current crowds into a small region and melts it. The \(di/dt\) rating — typically 100 A/µs — expresses this limit, and it is enforced with a small series inductor. Note that a hard gate drive, with a fast-rising pulse well above \(I_{GT}\), turns on a larger initial area and improves the \(di/dt\) capability, so overdriving the gate is good practice for reasons beyond reliability of triggering.
5 The DIAC, the TRIAC and Phase Control
An SCR conducts in one direction only, so controlling an AC load with one wastes half the cycle. Two devices solve this.
A DIAC is a symmetrical three-layer device with two terminals and no gate. It blocks in both directions until the applied voltage reaches its breakover voltage \(V_{BO}\), typically 32 V, at which point it switches into conduction and its terminal voltage drops by a breakback of about 5 V. That negative-resistance step is the point of the device: it converts a slowly rising voltage into an abrupt pulse of current, which is exactly what a thyristor gate wants. A DIAC and a capacitor form the trigger circuit of nearly every mains lamp dimmer ever built.
A TRIAC is two SCRs in inverse parallel sharing one gate and one die, so it conducts in both directions and can be triggered in both. Its characteristic is the SCR's rotated through 180° about the origin: a breakover point in each quadrant, latching, holding current and all. Because the terminals are symmetric they are called MT1 and MT2 rather than anode and cathode, and the gate is referenced to MT1.
Triggering a TRIAC is more subtle than triggering an SCR, because both MT2 and the gate can be of either polarity. The four combinations are the trigger quadrants, and they are not equally sensitive.
| Quadrant | MT2 polarity | Gate polarity | Relative \(I_{GT}\) | Mechanism |
|---|---|---|---|---|
| I (I+) | Positive | Positive | 1.0 | Direct, like an SCR |
| II (I−) | Positive | Negative | 1.1 | Remote gate injection |
| III (III−) | Negative | Negative | 1.2 | Direct on the second SCR |
| IV (III+) | Negative | Positive | 2.0 to 2.5 | Indirect and slow |
Quadrant IV is the awkward one: it needs twice the gate current, triggers more slowly and has the poorest \(dV/dt\) immunity. Many modern TRIACs are specified as three-quadrant devices with quadrant IV simply not guaranteed, and drive circuits are arranged to avoid it — a DIAC trigger naturally uses quadrants I and III, which is one more reason for its popularity.
The application that dominates all of these is phase control: delaying the firing instant by an angle \(\alpha\) after each zero crossing, so that the load receives only the tail of each half-cycle. For a resistive load controlled by a TRIAC, integrating the truncated sinusoid gives
and since a resistive load's power goes as the square of the RMS voltage, the fractional power is simply the quantity under the root.
Figure 15.3 draws two firing angles, and the table below gives the whole range.
| \(\alpha\) | \(V_{rms}/V_s\) | Power fraction | \(V_{rms}\) from 230 V |
|---|---|---|---|
| 0° | 1.000 | 100 % | 230.0 V |
| 30° | 0.986 | 97.1 % | 226.7 V |
| 60° | 0.897 | 80.4 % | 206.3 V |
| 90° | 0.707 | 50.0 % | 162.6 V |
| 120° | 0.442 | 19.6 % | 101.7 V |
| 150° | 0.170 | 2.9 % | 39.1 V |
Notice how non-linear the control is. The first 30° of delay removes only 2.9 % of the power, and the last 30° removes 17 %; the useful range is concentrated between about 45° and 135°, which is why dimmer knobs feel unresponsive at the ends of their travel. Phase control is efficient — the switch is either off or dropping 1.5 V — but the abrupt current step at each firing instant contains harmonics reaching into the megahertz, so a mains filter of a series inductor and a shunt capacitor is mandatory rather than optional.
6 The UJT and the Relaxation Oscillator
A unijunction transistor is not a thyristor and not really a transistor: it is a bar of lightly doped n-type silicon with ohmic contacts at each end, called base 1 and base 2, and a single p-type emitter junction part-way along. It has no amplifying action at all. What it has is a negative-resistance characteristic, and that is what makes it the natural trigger generator for thyristors.
The bar behaves as a potential divider. With \(V_{BB}\) applied between the bases, the fraction of that voltage appearing at the emitter's position is the intrinsic standoff ratio:
a fixed geometric property of the device, between 0.51 and 0.82 for common types and typically 0.63. The interbase resistance \(R_{BB} = R_{B1}+R_{B2}\) is 4 to 10 k\(\Omega\).
Raise the emitter voltage from zero. Nothing happens until the emitter junction becomes forward biased, which requires the emitter to be one diode drop above the internal divider point. That is the peak-point voltage:
At that instant the junction injects holes into the lower half of the bar. Those holes are majority-carrier-like in effect: they raise the conductivity of \(R_{B1}\), which lowers the divider point, which forward biases the emitter still harder, which injects more holes. The result is regenerative, exactly like the thyristor's, and the emitter voltage falls while the emitter current rises — a negative resistance running from the peak point \((V_P, I_P \approx 5\ \mu\text{A})\) to the valley point \((V_V \approx 1\ \text{V}, I_V \approx 4\ \text{mA})\).
Put a resistor and capacitor on the emitter and the device oscillates, as Figure 15.4 shows. The capacitor charges through \(R\) towards \(V_{BB}\); when it reaches \(V_P\) the UJT fires and discharges it rapidly through the low resistance of \(R_{B1}\) and a small resistor \(R_1\); when the current falls below \(I_V\) the device turns off and the cycle repeats.
A 2N2646 (\(\eta = 0.63\), \(I_P = 5\) µA, \(I_V = 4\) mA, \(V_V = 1\) V) runs from \(V_{BB} = 12\) V with \(R = 47\ \text{k}\Omega\) and \(C = 0.1\) µF. Find \(V_P\), the frequency, and the permitted range of \(R\).
Peak-point voltage. \(V_P = \eta V_{BB} + V_D = 0.63\times12 + 0.7 = 8.26\) V.
Period, textbook form. Assuming the capacitor starts from zero, \(V_P = V_{BB}(1-e^{-T/RC})\), so \(T = RC\ln[1/(1-\eta)]\). With \(\ln(1/0.37) = 0.9943\), \(T = 47\times10^3\times0.1\times10^{-6}\times0.9943 = 4.673\) ms and \(f = 214.0\) Hz.
Period, corrected. In the steady state the capacitor does not start from zero but from \(V_V = 1\) V, so \(T = RC\ln[(V_{BB}-V_V)/(V_{BB}-V_P)] = 4.7\ \text{ms}\times\ln(11/3.74) = 4.7\times1.0788 = 5.070\) ms and \(f = 197.2\) Hz. The textbook formula is 8.5 % optimistic, and this is the discrepancy students meet on the bench.
Upper limit on \(R\). The charging current at the peak point must exceed \(I_P\), or the capacitor stalls just below \(V_P\) and the circuit never fires: \(R < (V_{BB}-V_P)/I_P = 3.74/5\ \mu\text{A} = 748\ \text{k}\Omega\).
Lower limit on \(R\). After firing, the current through \(R\) must fall below \(I_V\) or the UJT never turns off and the circuit latches: \(R > (V_{BB}-V_V)/I_V = 11/4\ \text{mA} = 2.75\ \text{k}\Omega\).
Design range. 2.75 k\(\Omega\) to 748 k\(\Omega\), a range of 272:1 in frequency from one component. With \(C = 0.047\) µF and \(R = 22\ \text{k}\Omega\) the textbook formula gives 973 Hz, so a 1 kHz trigger source needs no exotic parts.
The reason this circuit and the thyristor belong in the same chapter is phase control. Synchronise the oscillator to the mains — typically by powering it from a clipped, zero-crossing-referenced supply so that \(C\) starts charging afresh at each zero crossing — and the firing instant becomes \(t = RC\ln[1/(1-\eta)]\), directly proportional to \(R\). Since a 50 Hz half-cycle lasts 10 ms, the firing angle is \(\alpha = 180^\circ\times t/10\ \text{ms}\):
| \(R\) (with \(C\) = 0.1 µF) | Delay \(t\) | Firing angle \(\alpha\) | Load power |
|---|---|---|---|
| 10 k\(\Omega\) | 0.99 ms | 17.9° | 99 % |
| 22 k\(\Omega\) | 2.19 ms | 39.4° | 92 % |
| 47 k\(\Omega\) | 4.67 ms | 84.1° | 55 % |
| 100 k\(\Omega\) | 9.94 ms | 179.0° | < 1 % |
A single 100 k\(\Omega\) potentiometer therefore covers the whole control range, which is why this circuit — a UJT, a capacitor, a potentiometer, a pulse transformer and an SCR — was the standard motor speed controller for thirty years. Modern designs replace the UJT with a programmable unijunction transistor, whose \(\eta\) is set by two external resistors rather than fixed at manufacture, or with a microcontroller measuring the zero crossing and timing the pulse digitally. The device physics of the thyristor it drives, however, is unchanged, and Chapter 16 now leaves switching behind for the transistor treated as a continuous amplifier.
7 Summary and Key Results
| Quantity | Expression | Value |
|---|---|---|
| Two-transistor model | \(I_A = (\alpha_2I_G + I_{CBO})/(1-\alpha_1-\alpha_2)\) | 50 mA at \(\alpha\) sum 0.95, \(I_G\) = 5 mA |
| Latching condition | \(\alpha_1 + \alpha_2 = 1\) | Reached by raising current, since \(\alpha\) rises with \(I\) |
| Latching current | \(I_L\), gate still applied | 40 mA — must be reached during the gate pulse |
| Holding current | \(I_H\), gate removed | 20 mA — below it the device turns off |
| On-state loss | \(P = V_{T0}I_{T(AV)} + r_TI_{T(RMS)}^2\) | 8.47 W at 8 A average, 12.6 A RMS |
| Gate resistor | \(R_G = (V_S - V_{GT})/I_G\) | 330 \(\Omega\) from 12 V gives 31.8 mA, \(P_G\) = 47.7 mW |
| \(dV/dt\) triggering | \(i = C_j\,dV/dt\) | 25 mA at 500 V/µs with \(C_j\) = 50 pF; \(I_{GT}\) is 15 mA |
| Snubber | \(dV/dt|_0 = V/RC\) | 34 V/µs for 100 \(\Omega\), 0.1 µF at 340 V; 0.58 W |
| Forced commutation | \(C \ge I_Tt_q/V_C\) | 5 µF for 10 A, 50 µs, 100 V |
| Commutation loss | \(\tfrac12CV_C^2f\) | 25 W at 1 kHz — why thyristor inverters are slow |
| DIAC breakover | \(V_{BO}\), symmetric, no gate | 32 V with 5 V breakback |
| TRIAC quadrants | I, II, III sensitive; IV poor | \(I_{GT}\) ratio 1.0 : 1.1 : 1.2 : 2.0–2.5 |
| Phase control | \(V_{rms}/V_s = \sqrt{1-\alpha/\pi+\sin2\alpha/2\pi}\) | 0.897 at 60° (80.4 %); 0.707 at 90° (50 %) |
| UJT peak point | \(V_P = \eta V_{BB} + V_D\) | 8.26 V for \(\eta\) = 0.63, \(V_{BB}\) = 12 V |
| UJT period | \(T = RC\ln[1/(1-\eta)]\) | 4.673 ms, 214.0 Hz at 47 k\(\Omega\), 0.1 µF |
| UJT period, corrected | \(T = RC\ln[(V_{BB}-V_V)/(V_{BB}-V_P)]\) | 5.070 ms, 197.2 Hz — 8.5 % lower |
| UJT resistor range | \((V_{BB}-V_V)/I_V < R < (V_{BB}-V_P)/I_P\) | 2.75 k\(\Omega\) to 748 k\(\Omega\) |
8 Common Mistakes
They are different quantities measured under different conditions. \(I_L\) is the anode current that must be reached while the gate drive is present for the device to stay on after the gate is removed; \(I_H\) is the smaller current below which an already latched device drops out, measured with no gate drive. For a typical device \(I_L = 40\) mA and \(I_H = 20\) mA. The practical difference shows up with inductive loads, where the current rises slowly: a 10 µs gate pulse into a load with \(L/R = 5\) ms leaves the anode current far below \(I_L\), so the SCR fires and immediately turns off again. The remedy is a longer pulse, a pulse train, or a resistor across the load to guarantee an initial current step.
False triggering by \(dV/dt\) is not a rare event; it is what happens the first time the equipment is switched on into a supply that is already at its peak, or when a contactor elsewhere on the same circuit opens. With \(C_j = 50\) pF, a rate of 300 V/µs injects 15 mA into the gate region, exactly the specified \(I_{GT}\). A bench supply with a soft start never produces such a rate, so the fault appears only in the field and only intermittently. Fit the RC snubber, and fit the resistor as well as the capacitor — a capacitor alone discharges through the SCR at turn-on with a peak current of hundreds of amperes.
\(T = RC\ln[1/(1-\eta)]\) assumes the capacitor starts each cycle from zero volts. It does not: the UJT stops conducting at its valley voltage, typically 1 V, so in the steady state charging begins from there. The correct expression is \(T = RC\ln[(V_{BB}-V_V)/(V_{BB}-V_P)]\), which for the worked example gives 5.070 ms rather than 4.673 ms — a measured frequency of 197 Hz against a predicted 214 Hz, an error of 8.5 %. The simple formula is a good first estimate and a poor final answer, and the difference grows as \(V_V\) becomes a larger fraction of \(V_{BB}\), so it matters most in low-voltage designs.
9 Chapter Review
1. Derive the anode-current expression for an SCR from the two-transistor model and use it to explain why the device latches.
Split the four-layer PNPN structure diagonally into a PNP transistor \(Q_1\) (whose emitter is the anode) and an NPN transistor \(Q_2\) (whose emitter is the cathode), with the collector of each connected to the base of the other. For a common-base transistor \(I_C = \alpha I_E + I_{CBO}\). Here \(Q_1\)'s emitter current is \(I_A\) and \(Q_2\)'s is \(I_A + I_G\) (since \(I_K = I_A + I_G\)). Applying Kirchhoff's current law at the internal node where the two collectors meet the anode path: \(I_A = I_{C1} + I_{C2} = \alpha_1I_A + I_{CBO1} + \alpha_2(I_A + I_G) + I_{CBO2}\). Collecting terms, \(I_A[1 - (\alpha_1+\alpha_2)] = \alpha_2I_G + I_{CBO1} + I_{CBO2}\), so \(I_A = (\alpha_2I_G + I_{CBO})/[1 - (\alpha_1+\alpha_2)]\). Latching follows from the denominator. As \(\alpha_1+\alpha_2\) approaches unity the denominator approaches zero and \(I_A\) rises without bound, limited only by the external circuit. What makes this reachable is that \(\alpha\) is not constant: at the microampere leakage currents of the blocking state, recombination in the base consumes most of the injected carriers and \(\alpha\) may be 0.1, but as the current rises the base transport efficiency improves and \(\alpha\) climbs towards 0.99. So any increase in current increases the loop gain, which increases the current: the process is regenerative and runs to completion in a few microseconds. Once complete, the two transistors are supplying each other's base drive, the numerator's \(I_G\) term is irrelevant, and the gate has no further control — the device is latched.
2. A 230 V 50 Hz lamp dimmer uses a TRIAC to control a 60 W lamp. Compute the load current and power at firing angles of 0°, 90° and 150°, and explain why the lamp flickers at the low end.
The lamp's resistance at full power is \(R = V^2/P = 230^2/60 = 881.7\ \Omega\), and its full-power RMS current is \(60/230 = 261\) mA. Phase control multiplies the RMS voltage by \(k = \sqrt{1 - \alpha/\pi + \sin2\alpha/2\pi}\) and the power by \(k^2\). At \(\alpha = 0^\circ\), \(k = 1\): 230 V, 261 mA, 60.0 W. At \(\alpha = 90^\circ\), \(k = \sqrt{1-0.5+0} = 0.7071\): 162.6 V, 184 mA, 30.0 W. At \(\alpha = 150^\circ\), \(k = \sqrt{1-0.8333+0.0796} = 0.1698\): 39.1 V, 44.3 mA, 1.73 W. The flicker at the low end has two causes and both are visible in those numbers. First, the RMS current of 44.3 mA is only about twice the holding current of a typical small TRIAC (20 mA), and the instantaneous current at the firing instant is smaller still, so the device may fail to latch on some half-cycles — and since the two half-cycles are triggered in different quadrants with different sensitivities, it may latch on one and not the other, producing a DC component and a strong 50 Hz flicker. Second, near \(\alpha = 150^\circ\) the control is extremely non-linear: the derivative \(dP/d\alpha\) is steep, so a small jitter in the firing instant, caused for example by mains noise reaching the DIAC trigger, produces a large change in power. A practical dimmer limits \(\alpha\) to about 140° and adds a small resistor in parallel with the lamp to keep the current above \(I_H\).
3. An SCR has \(C_j = 40\) pF and \(I_{GT} = 10\) mA. Find the \(dV/dt\) that will trigger it spuriously, and design an RC snubber that keeps a 400 V supply below one fifth of that rate.
The junction capacitance carries a displacement current \(i = C_j\,dV/dt\) that reaches the internal base regions and is indistinguishable from gate current. Setting \(i = I_{GT}\): \(dV/dt = I_{GT}/C_j = 0.010/(40\times10^{-12}) = 2.5\times10^8\) V/s \(= 250\) V/µs. The target is one fifth of that, 50 V/µs. An RC snubber across the device presents an initial rate of \(dV/dt|_0 = V/(RC)\), because at \(t = 0\) the capacitor is uncharged and the whole supply voltage appears across \(R\), so the capacitor current is \(V/R\) and \(dV_C/dt = I/C = V/(RC)\). Requiring \(400/(RC) \le 5\times10^7\) V/s gives \(RC \ge 8\ \mu\text{s}\). Choose \(C = 0.1\) µF and \(R = 100\ \Omega\), giving \(RC = 10\) µs and an initial rate of 40 V/µs — comfortably inside the target. Now check the resistor. At the moment the SCR turns on, the snubber capacitor discharges through \(R\) into the device with a peak current of \(V/R = 400/100 = 4\) A, which is within the surge rating of any medium SCR but is exactly why the resistor must be there; a bare capacitor would discharge through the device with only the wiring inductance to limit it. The resistor's dissipation is the energy \(\tfrac12CV^2\) lost twice per cycle, that is \(CV^2f = 0.1\times10^{-6}\times400^2\times50 = 0.80\) W, so specify a 2 W non-inductive part.
4. Design a UJT relaxation oscillator to trigger an SCR at 500 Hz from a 15 V supply, using a UJT with \(\eta = 0.66\), \(I_P = 2\) µA, \(I_V = 6\) mA and \(V_V = 1.2\) V. Verify that the chosen \(R\) lies within the permitted range.
First the peak-point voltage: \(V_P = \eta V_{BB} + V_D = 0.66\times15 + 0.7 = 10.6\) V. For the period, use the corrected expression that starts from the valley voltage: \(T = RC\ln[(V_{BB}-V_V)/(V_{BB}-V_P)] = RC\ln(13.8/4.4) = RC\times1.1426\). For \(f = 500\) Hz, \(T = 2\) ms, so \(RC = 2\times10^{-3}/1.1426 = 1.7504\) ms. Choosing \(C = 0.047\) µF gives \(R = 1.7504\times10^{-3}/47\times10^{-9} = 37.2\ \text{k}\Omega\); the nearest standard value is 39 k\(\Omega\), which gives \(T = 39\times10^3\times47\times10^{-9}\times1.1426 = 2.094\) ms and \(f = 477\) Hz — within 5 %, and a trimmer or the next value down (33 k\(\Omega\), 564 Hz) brackets the target. Now the two limits on \(R\). The upper limit ensures the capacitor can actually reach \(V_P\): the charging current there must exceed \(I_P\), so \(R < (V_{BB}-V_P)/I_P = 4.4/(2\times10^{-6}) = 2.2\ \text{M}\Omega\). The lower limit ensures the UJT can turn off after firing: the current supplied through \(R\) must fall below \(I_V\), so \(R > (V_{BB}-V_V)/I_V = 13.8/(6\times10^{-3}) = 2.30\ \text{k}\Omega\). The chosen 39 k\(\Omega\) sits comfortably between 2.30 k\(\Omega\) and 2.2 M\(\Omega\). Finally, take the output from a small resistor of 100 \(\Omega\) in series with base 1; the discharge time constant is \(100\times47\ \text{nF} = 4.7\) µs, giving a pulse of a few volts and about 10 µs duration, which is ample to trigger an SCR into a resistive load.
5. Explain the difference between natural and forced commutation, and calculate the commutating capacitor and its associated loss for a 20 A DC chopper switching at 400 Hz with \(t_q = 40\) µs and a commutating voltage of 150 V.
A latched thyristor cannot be turned off by its gate, so the anode current must be reduced below the holding current and the device held at zero or reverse voltage for at least the circuit turn-off time \(t_q\), during which the stored charge in the four layers recombines. In natural or line commutation the AC supply does this for free: the current passes through zero every half-cycle and the device is then reverse biased for the whole of the next half-cycle, 10 ms at 50 Hz, which is 200 times a typical \(t_q\). No extra components are needed, and this is why thyristors dominate mains phase control. In forced commutation the supply is DC and never reverses, so an auxiliary circuit must do the job — usually a pre-charged capacitor switched across the conducting device by a second thyristor, so that its discharge current opposes and cancels the load current and then holds the main device in reverse. The capacitor must supply the load current for at least \(t_q\): \(C \ge I_Tt_q/V_C = 20\times40\times10^{-6}/150 = 5.33\) µF. Applying the usual safety factor of 1.5 on \(t_q\) gives \(C = 8\) µF, so specify a 10 µF pulse-rated capacitor. The energy stored is \(\tfrac12CV_C^2 = 0.5\times10\times10^{-6}\times150^2 = 0.1125\) J, and it is dissipated once per switching cycle, so the loss is \(0.1125\times400 = 45\) W. That figure is the whole argument against thyristor choppers: it is proportional to frequency, so raising the switching frequency to 4 kHz would cost 450 W, and the capacitor, its charging inductor, its diode and its auxiliary thyristor cost more than the main device. A power MOSFET or IGBT turns off by having its gate drive removed, at any frequency and at negligible cost, which is why every modern DC chopper uses one.